2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 VIA Technologies, Inc.
5 * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
6 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
34 #include "northbridge.h"
37 static void memctrl_init(device_t dev)
41 u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8;
44 printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n");
46 vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
47 PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
49 /* Setup Low Memory Top */
50 /* 0x47 == HA(32:25) */
51 /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
52 ranks = pci_read_config8(dev, 0x47);
53 reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
55 pci_write_config16(dev, 0x84, reg16);
56 printk(BIOS_SPEW, "Low Top Address = 0x%04X\n", reg16);
58 /* Set up the VGA framebuffer size and Base Address */
59 /* Note dependencies between agp.c and vga.c and here */
60 reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15) | 0xF00;
61 pci_write_config16(dev, 0xa0, reg16);
64 for (ranks = 0x4b; ranks >= 0x48; ranks--) {
65 if (pci_read_config8(dev, ranks)) {
74 /* GMINT Misc. FrameBuffer rank */
75 pci_write_config16(dev, 0xb0, reg16);
77 pci_write_config8(dev, 0xb8, 0x08);
79 /* Arbritation Counters */
80 pci_write_config8(dev, 0xb2, 0xaa);
82 /* Write FIFO Setup */
83 pci_write_config8(dev, 0xb3, 0x5a);
85 /* Graphics control optimisation */
86 pci_write_config8(dev, 0xb4, 0x0f);
89 pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
90 /* PAGE C, D, E are all read write enable */
91 pci_write_config8(dev, 0x80, pagec);
92 pci_write_config8(dev, 0x81, paged);
93 pci_write_config8(dev, 0x83, pagee);
94 /* PAGE F are read/writable */
95 shadowreg = pci_read_config8(dev, 0x82);
97 pci_write_config8(dev, 0x82, shadowreg);
98 pci_write_config8(vlink_dev, 0x61, pagec);
99 pci_write_config8(vlink_dev, 0x62, paged);
100 pci_write_config8(vlink_dev, 0x64, pagee);
102 shadowreg = pci_read_config8(vlink_dev, 0x63);
104 pci_write_config8(vlink_dev, 0x63, shadowreg);
106 /* Activate VGA Frame Buffer */
108 reg8 = pci_read_config8(dev, 0xA0);
110 pci_write_config8(dev, 0xA0, reg8);
113 printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
115 for (i = 0 ; i < 16; i++)
117 printk(BIOS_SPEW, "%02X: ", i*16);
118 for (j = 0; j < 16; j++)
120 reg8 = pci_read_config8(dev, j+(i*16));
121 printk(BIOS_SPEW, "%02X ", reg8);
123 printk(BIOS_SPEW, "\n");
126 printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__);
129 static const struct device_operations memctrl_operations = {
130 .read_resources = cn400_noop,
131 .set_resources = cn400_noop,
132 .enable_resources = cn400_noop,
133 .init = memctrl_init,
137 static const struct pci_driver memctrl_driver __pci_driver = {
138 .ops = &memctrl_operations,
139 .vendor = PCI_VENDOR_ID_VIA,
140 .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
143 static void cn400_domain_read_resources(device_t dev)
145 struct resource *resource;
147 printk(BIOS_SPEW, "Entering %s.\n", __func__);
149 /* Initialize the system wide I/O space constraints. */
150 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
151 resource->limit = 0xffffUL;
152 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
155 /* Initialize the system wide memory resources constraints. */
156 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
157 resource->limit = 0xffffffffULL;
158 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
161 printk(BIOS_SPEW, "Leaving %s.\n", __func__);
164 static void ram_resource(device_t dev, unsigned long index,
165 unsigned long basek, unsigned long sizek)
167 struct resource *resource;
171 resource = new_resource(dev, index);
172 resource->base = (resource_t) (basek << 10);
173 resource->size = (resource_t) (sizek << 10);
174 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
175 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
179 static void ram_reservation(device_t dev, unsigned long index,
180 unsigned long base, unsigned long size)
182 struct resource *res;
184 printk(BIOS_SPEW, "Configuring Via C3 LAPIC Fixed Resource\n");
185 /* Fixed LAPIC resource */
186 res = new_resource(dev, 1);
187 res->base = (resource_t) base;
189 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
190 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
194 static void tolm_test(void *gp, struct device *dev, struct resource *new)
196 struct resource **best_p = gp;
197 struct resource *best;
200 if (!best || (best->base > new->base))
205 static u32 find_pci_tolm(struct bus *bus)
207 struct resource *min = NULL;
210 printk(BIOS_SPEW, "Entering CN400 find_pci_tolm\n");
212 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
215 if (min && tolm > min->base)
218 printk(BIOS_SPEW, "Leaving CN400 find_pci_tolm\n");
223 #if CONFIG_WRITE_HIGH_TABLES==1
224 /* maximum size of high tables in KB */
225 #define HIGH_TABLES_SIZE 64
226 extern uint64_t high_tables_base, high_tables_size;
229 static void cn400_domain_set_resources(device_t dev)
234 printk(BIOS_SPEW, "Entering %s.\n", __func__);
236 pci_tolm = find_pci_tolm(dev->link_list);
237 mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
238 PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0);
241 unsigned long tomk, tolmk;
242 unsigned char rambits;
245 rambits = pci_read_config8(mc_dev, 0x47);
246 tomk = rambits * 32 * 1024;
247 /* Compute the Top Of Low Memory (TOLM), in Kb. */
248 tolmk = pci_tolm >> 10;
249 printk(BIOS_SPEW, "tomk is 0x%lx, tolmk is 0x%08lX\n", tomk, tolmk);
251 /* The PCI hole does does not overlap the memory. */
255 #if CONFIG_WRITE_HIGH_TABLES == 1
256 /* Locate the High Tables at the Top of Low Memory below the Video RAM */
257 high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024;
258 high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024;
259 printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
262 /* Report the memory regions. */
264 /* TODO: Hole needed? */
265 ram_resource(dev, idx++, 0, 640); /* First 640k */
266 /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
267 ram_resource(dev, idx++, 768,
268 (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
270 assign_resources(dev->link_list);
272 printk(BIOS_SPEW, "Leaving %s.\n", __func__);
275 static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
277 printk(BIOS_DEBUG, "Entering %s.\n", __func__);
279 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
283 static struct device_operations pci_domain_ops = {
284 .read_resources = cn400_domain_read_resources,
285 .set_resources = cn400_domain_set_resources,
286 .enable_resources = NULL,
288 .scan_bus = cn400_domain_scan_bus,
291 static void cpu_bus_init(device_t dev)
293 initialize_cpus(dev->link_list);
296 static void cpu_bus_noop(device_t dev)
300 static struct device_operations cpu_bus_ops = {
301 .read_resources = cpu_bus_noop,
302 .set_resources = cpu_bus_noop,
303 .enable_resources = cpu_bus_noop,
304 .init = cpu_bus_init,
308 static void enable_dev(struct device *dev)
310 printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev));
312 /* Set the operations if it is a special bus type. */
313 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
314 dev->ops = &pci_domain_ops;
316 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
317 dev->ops = &cpu_bus_ops;
321 struct chip_operations northbridge_via_cn400_ops = {
322 CHIP_NAME("VIA CN400 Northbridge")
323 .enable_dev = enable_dev,