src/northbridge/transmeta/tm5800/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include "chip.h"
  12 #include "northbridge.h"
  13
  14 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  15
  16 static void pci_domain_read_resources(device_t dev)
  17 {
  18         struct resource *resource;
  19         unsigned reg;
  20
  21         /* Initialize the system wide io space constraints */
  22         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  23         resource->limit = 0xffffUL;
  24         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  25
  26         /* Initialize the system wide memory resources constraints */
  27         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  28         resource->limit = 0xffffffffULL;
  29         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  30 }
  31
  32 static void ram_resource(device_t dev, unsigned long index,
  33         unsigned long basek, unsigned long sizek)
  34 {
  35         struct resource *resource;
  36
  37         if (!sizek) {
  38                 return;
  39         }
  40         resource = new_resource(dev, index);
  41         resource->base  = ((resource_t)basek) << 10;
  42         resource->size  = ((resource_t)sizek) << 10;
  43         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  44                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  45 }
  46
  47 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  48 {
  49         struct resource **best_p = gp;
  50         struct resource *best;
  51         best = *best_p;
  52         if (!best || (best->base > new->base)) {
  53                 best = new;
  54         }
  55         *best_p = best;
  56 }
  57
  58 static uint32_t find_pci_tolm(struct bus *bus)
  59 {
  60         struct resource *min;
  61         uint32_t tolm;
  62         min = 0;
  63         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  64         tolm = 0xffffffffUL;
  65         if (min && tolm > min->base) {
  66                 tolm = min->base;
  67         }
  68         return tolm;
  69 }
  70
  71 static void pci_domain_set_resources(device_t dev)
  72 {
  73         struct resource *resource, *last;
  74         device_t mc_dev;
  75         uint32_t pci_tolm;
  76
  77         pci_tolm = find_pci_tolm(&dev->link[0]);
  78         mc_dev = dev->link[0].children;
  79         if (mc_dev) {
  80                 /* Figure out which areas are/should be occupied by RAM.
  81                  * This is all computed in kilobytes and converted to/from
  82                  * the memory controller right at the edges.
  83                  * Having different variables in different units is
  84                  * too confusing to get right.  Kilobytes are good up to
  85                  * 4 Terabytes of RAM...
  86                  */
  87                 unsigned long tomk, tolmk;
  88                 int idx;
  89
  90 #warning "This is hardcoded to 1MiB of RAM for now"
  91                 tomk = 1024;
  92                 /* Compute the top of Low memory */
  93                 tolmk = pci_tolm >> 10;
  94                 if (tolmk >= tomk) {
  95                         /* The PCI hole does does not overlap the memory.
  96                          */
  97                         tolmk = tomk;
  98                 }
  99                 /* Report the memory regions */
 100                 idx = 10;
 101                 ram_resource(dev, idx++, 0, 640);
 102                 ram_resource(dev, idx++, 768, tolmk - 768);
 103         }
 104         assign_resources(&dev->link[0]);
 105 }
 106
 107 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 108 {
 109         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 110         return max;
 111 }
 112
 113 static struct device_operations pci_domain_ops = {
 114         .read_resources   = pci_domain_read_resources,
 115         .set_resources    = pci_domain_set_resources,
 116         .enable_resources = enable_childrens_resources,
 117         .init             = 0,
 118         .scan_bus         = pci_domain_scan_bus,
 119 };
 120
 121 static void cpu_bus_init(device_t dev)
 122 {
 123         initialize_cpus(&dev->link[0]);
 124 }
 125
 126 static void cpu_bus_noop(device_t dev)
 127 {
 128 }
 129
 130 static struct device_operations cpu_bus_ops = {
 131         .read_resources   = cpu_bus_noop,
 132         .set_resources    = cpu_bus_noop,
 133         .enable_resources = cpu_bus_noop,
 134         .init             = cpu_bus_init,
 135         .scan_bus         = 0,
 136 };
 137
 138 static void enable_dev(struct device *dev)
 139 {
 140         struct device_path path;
 141
 142         /* Set the operations if it is a special bus type */
 143         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 144                 dev->ops = &pci_domain_ops;
 145                 pci_set_method();
 146         }
 147         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 148                 dev->ops = &cpu_bus_ops;
 149         }
 150 }
 151
 152 struct chip_operations northbridge_transmeta_tm5800_control = {
 153         CHIP_NAME("Transmeta tm5800 Northbridge")
 154         .enable_dev = enable_dev,
 155 };