src/northbridge/intel/i945/raminit.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #ifndef RAMINIT_H
  21 #define RAMINIT_H
  22
  23 #define DIMM_SOCKETS 2
  24
  25 #define DIMM_SPD_BASE 0x50
  26 #define DIMM_TCO_BASE 0x30
  27
  28 /* Burst length is always 8 */
  29 #define BURSTLENGTH      8
  30
  31 struct sys_info {
  32         u16 memory_frequency;   /* 400, 533 or 667 */
  33         u16 fsb_frequency;      /* 400, 533 or 667 */
  34
  35         u8 trp;                 /* calculated by sdram_detect_smallest_tRP() */
  36         u8 trcd;                /* calculated by sdram_detect_smallest_tRCD() */
  37         u8 tras;                /* calculated by sdram_detect_smallest_tRAS() */
  38         u8 trfc;                /* calculated by sdram_detect_smallest_tRFC() */
  39         u8 twr;                 /* calculated by sdram_detect_smallest_tWR() */
  40
  41         u8 cas;                 /* 3, 4 or 5 */
  42         u8 refresh;             /* 0 = 15.6us, 1 = 7.8us */
  43
  44         u8 dual_channel;        /* 0 or 1 */
  45         u8 interleaved;
  46
  47         u8 mvco4x;              /* 0 (8x) or 1 (4x) */
  48         u8 clkcfg_bit7;
  49         u8 boot_path;
  50 #define BOOT_PATH_NORMAL        0
  51 #define BOOT_PATH_RESET         1
  52 #define BOOT_PATH_RESUME        2
  53
  54         u8 package;             /* 0 = planar, 1 = stacked */
  55 #define SYSINFO_PACKAGE_PLANAR          0x00
  56 #define SYSINFO_PACKAGE_STACKED         0x01
  57         u8 dimm[2 * DIMM_SOCKETS];
  58 #define SYSINFO_DIMM_X16DS              0x00
  59 #define SYSINFO_DIMM_X8DS               0x01
  60 #define SYSINFO_DIMM_X16SS              0x02
  61 #define SYSINFO_DIMM_X8DDS              0x03
  62 #define SYSINFO_DIMM_NOT_POPULATED      0x04
  63
  64         u8 banks[2 * DIMM_SOCKETS];
  65
  66         u8 banksize[2 * 2 * DIMM_SOCKETS];
  67
  68 } __attribute__ ((packed));
  69
  70 void receive_enable_adjust(struct sys_info *sysinfo);
  71 void sdram_initialize(int boot_path);
  72 unsigned long get_top_of_ram(void);
  73 int fixup_i945_errata(void);
  74 void udelay(u32 us);
  75
  76 #endif                          /* RAMINIT_H */