src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <cpu/x86/mem.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <spd.h>
  24 #include "raminit.h"
  25 #include "i945.h"
  26
  27 /* Debugging macros. */
  28 #if CONFIG_DEBUG_RAM_SETUP
  29 #define PRINTK_DEBUG(x...)      printk_debug(x)
  30 #else
  31 #define PRINTK_DEBUG(x...)
  32 #endif
  33
  34 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  35
  36 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  37 #define RAM_COMMAND_NOP                 (0x1 << 16)
  38 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  39 #define RAM_COMMAND_MRS                 (0x3 << 16)
  40 #define RAM_COMMAND_EMRS                (0x4 << 16)
  41 #define RAM_COMMAND_CBR                 (0x6 << 16)
  42 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  43
  44 #define RAM_EMRS_1                      (0x0 << 21)
  45 #define RAM_EMRS_2                      (0x1 << 21)
  46 #define RAM_EMRS_3                      (0x2 << 21)
  47
  48 static void do_ram_command(u32 command)
  49 {
  50         u32 reg32;
  51
  52         reg32 = MCHBAR32(DCC);
  53         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  54         reg32 |= command;
  55
  56         /* Also set Init Complete */
  57         if (command == RAM_COMMAND_NORMAL)
  58                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  59
  60         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  61
  62         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  63
  64         PRINTK_DEBUG("...done\n");
  65 }
  66
  67 static void ram_read32(u32 offset)
  68 {
  69         PRINTK_DEBUG("   ram read: %08x\n", offset);
  70
  71         read32(offset);
  72 }
  73
  74 #if CONFIG_DEBUG_RAM_SETUP
  75 static void sdram_dump_mchbar_registers(void)
  76 {
  77         int i;
  78         printk_debug("Dumping MCHBAR Registers\n");
  79
  80         for (i=0; i<0xfff; i+=4) {
  81                 if (MCHBAR32(i) == 0)
  82                         continue;
  83                 printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
  84         }
  85 }
  86 #endif
  87
  88 static int memclk(void)
  89 {
  90         int offset = 0;
  91 #ifdef CHIPSET_I945GM
  92         offset++;
  93 #endif
  94         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
  95         case 1: return 400;
  96         case 2: return 533;
  97         case 3: return 667;
  98         default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
  99         }
 100         return -1;
 101 }
 102
 103 #ifdef CHIPSET_I945GM
 104 static int fsbclk(void)
 105 {
 106         switch (MCHBAR32(CLKCFG) & 7) {
 107         case 0: return 400;
 108         case 1: return 533;
 109         case 3: return 667;
 110         default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 111         }
 112         return -1;
 113 }
 114 #endif
 115 #ifdef CHIPSET_I945GC
 116 static int fsbclk(void)
 117 {
 118         switch (MCHBAR32(CLKCFG) & 7) {
 119         case 0: return 1066;
 120         case 1: return 533;
 121         case 2: return 800;
 122         default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 123         }
 124         return -1;
 125 }
 126 #endif
 127
 128 static int sdram_capabilities_max_supported_memory_frequency(void)
 129 {
 130         u32 reg32;
 131
 132 #ifdef MAXIMUM_SUPPORTED_FREQUENCY
 133         return MAXIMUM_SUPPORTED_FREQUENCY;
 134 #endif
 135
 136         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
 137         reg32 &= (7 << 0);
 138
 139         switch (reg32) {
 140         case 4: return 400;
 141         case 3: return 533;
 142         case 2: return 667;
 143         }
 144         /* Newer revisions of this chipset rather support faster memory clocks,
 145          * so if it's a reserved value, return the fastest memory clock that we
 146          * know of and can handle
 147          */
 148         return 667;
 149 }
 150
 151 /**
 152  * @brief determine whether chipset is capable of dual channel interleaved mode
 153  *
 154  * @return 1 if interleaving is supported, 0 otherwise
 155  */
 156 static int sdram_capabilities_interleave(void)
 157 {
 158         u32 reg32;
 159
 160         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 161         reg32 >>= 25;
 162         reg32 &= 1;
 163
 164         return (!reg32);
 165 }
 166
 167 /**
 168  * @brief determine whether chipset is capable of two memory channels
 169  *
 170  * @return 1 if dual channel operation is supported, 0 otherwise
 171  */
 172 static int sdram_capabilities_dual_channel(void)
 173 {
 174         u32 reg32;
 175
 176         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 177         reg32 >>= 24;
 178         reg32 &= 1;
 179
 180         return (!reg32);
 181 }
 182
 183 static int sdram_capabilities_enhanced_addressing_xor(void)
 184 {
 185         u8 reg8;
 186
 187         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 188         reg8 &= (1 << 7);
 189
 190         return (!reg8);
 191 }
 192
 193 static int sdram_capabilities_two_dimms_per_channel(void)
 194 {
 195         u8 reg8;
 196
 197         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 198         reg8 &= (1 << 0);
 199
 200         return (reg8 != 0);
 201 }
 202
 203 static int sdram_capabilities_MEM4G_disable(void)
 204 {
 205         u8 reg8;
 206
 207         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
 208         reg8 &= (1 << 0);
 209
 210         return (reg8 != 0);
 211 }
 212
 213 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 214 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 215 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 216 #define GFX_FREQUENCY_CAP_ALL           0x00
 217
 218 static int sdram_capabilities_core_frequencies(void)
 219 {
 220         u8 reg8;
 221
 222         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 223         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 224         reg8 >>= 1;
 225
 226         return (reg8);
 227 }
 228
 229 static void sdram_detect_errors(void)
 230 {
 231         u8 reg8;
 232         u8 do_reset = 0;
 233
 234         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 235
 236         if (reg8 & ((1<<7)|(1<<2))) {
 237                 if (reg8 & (1<<2)) {
 238                         printk_debug("SLP S4# Assertion Width Violation.\n");
 239                         /* Write back clears bit 2 */
 240                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 241                         do_reset = 1;
 242
 243                 }
 244
 245                 if (reg8 & (1<<7)) {
 246                         printk_debug("DRAM initialization was interrupted.\n");
 247                         reg8 &= ~(1<<7);
 248                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 249                         do_reset = 1;
 250                 }
 251
 252                 /* Set SLP_S3# Assertion Stretch Enable */
 253                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 254                 reg8 |= (1 << 3);
 255                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 256
 257                 if (do_reset) {
 258                         printk_debug("Reset required.\n");
 259                         outb(0x00, 0xcf9);
 260                         outb(0x0e, 0xcf9);
 261                         for (;;) asm("hlt"); /* Wait for reset! */
 262                 }
 263         }
 264
 265         /* Set DRAM initialization bit in ICH7 */
 266         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 267         reg8 |= (1<<7);
 268         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 269
 270 }
 271
 272 /**
 273  * @brief Get generic DIMM parameters.
 274  * @param sysinfo Central memory controller information structure
 275  *
 276  * This function gathers several pieces of information for each system DIMM:
 277  *  o DIMM width (x8 / x16)
 278  *  o DIMM sides (single sided / dual sided)
 279  *
 280  *  Also, some non-supported scenarios are detected.
 281  */
 282
 283 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 284 {
 285         u32 dimm_mask = 0;
 286         int i;
 287
 288         /**
 289          * i945 supports two DIMMs, in two configurations:
 290          *
 291          * - single channel with two dimms
 292          * - dual channel with one dimm per channel
 293          *
 294          * In practice dual channel mainboards have their spd at 0x50, 0x52
 295          * whereas single channel configurations have their spd at 0x50/x51
 296          *
 297          * The capability register knows a lot about the channel configuration
 298          * but for now we stick with the information we gather from the SPD
 299          * ROMs
 300          */
 301
 302         if (sdram_capabilities_dual_channel()) {
 303                 sysinfo->dual_channel = 1;
 304                 printk_debug("This mainboard supports Dual Channel Operation.\n");
 305         } else {
 306                 sysinfo->dual_channel = 0;
 307                 printk_debug("This mainboard supports only Single Channel Operation.\n");
 308         }
 309
 310         /**
 311          * Since we only support two DIMMs in total, there is a limited number
 312          * of combinations. This function returns the type of DIMMs.
 313          * return value:
 314          *   [0:7]  lower DIMM population
 315          *   [8-15] higher DIMM population
 316          *   [16]   dual channel?
 317          *
 318          * There are 5 different possible populations for a DIMM socket:
 319          * 1. x16 double sided (X16DS)
 320          * 2. x8 double sided  (X8DS)
 321          * 3. x16 single sided (X16SS)
 322          * 4. x8 double stacked (X8DDS)
 323          * 5. not populated (NC)
 324          *
 325          * For the return value we start counting at zero.
 326          *
 327          */
 328
 329         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 330                 u8 reg8, device = DIMM_SPD_BASE + i;
 331
 332                 /* Initialize the socket information with a sane value */
 333                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 334
 335                 /* Dual Channel not supported, but Channel 1? Bail out */
 336                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 337                         continue;
 338
 339                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 340                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 341                         continue;
 342
 343                 printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 344
 345                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 346                         printk_debug("N/A\n");
 347                         continue;
 348                 }
 349
 350                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 351                 if (reg8 == ERROR_SCHEME_ECC)
 352                         die("Error: ECC memory not supported by this chipset\n");
 353
 354                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 355                 if (reg8 & MODULE_BUFFERED)
 356                         die("Error: Buffered memory not supported by this chipset\n");
 357                 if (reg8 & MODULE_REGISTERED)
 358                         die("Error: Registered memory not supported by this chipset\n");
 359
 360                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 361                 case 0x08:
 362                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 363                         case 1:
 364                                 printk_debug("x8DDS\n");
 365                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 366                                 break;
 367                         case 0:
 368                                 printk_debug("x8DS\n");
 369                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 370                                 break;
 371                         default:
 372                                 printk_debug ("Unsupported.\n");
 373                         }
 374                         break;
 375                 case 0x10:
 376                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 377                         case 1:
 378                                 printk_debug("x16DS\n");
 379                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 380                                 break;
 381                         case 0:
 382                                 printk_debug("x16SS\n");
 383                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 384                                 break;
 385                         default:
 386                                 printk_debug ("Unsupported.\n");
 387                         }
 388                         break;
 389                 default:
 390                         die("Unsupported DDR-II memory width.\n");
 391                 }
 392
 393                 dimm_mask |= (1 << i);
 394         }
 395
 396         if (!dimm_mask) {
 397                 die("No memory installed.\n");
 398         }
 399
 400         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 401                 printk_info("Channel 0 has no memory populated.\n");
 402         }
 403 }
 404
 405 /**
 406  * @brief determine if any DIMMs are stacked
 407  *
 408  * @param sysinfo central sysinfo data structure.
 409  */
 410 static void sdram_verify_package_type(struct sys_info * sysinfo)
 411 {
 412         int i;
 413
 414         /* Assume no stacked DIMMs are available until we find one */
 415         sysinfo->package = 0;
 416         for (i=0; i<2*DIMM_SOCKETS; i++) {
 417                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 418                         continue;
 419
 420                 /* Is the current DIMM a stacked DIMM? */
 421                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 422                         sysinfo->package = 1;
 423         }
 424 }
 425
 426 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 427 {
 428         int i;
 429         u8 cas_mask;
 430
 431         /* Setup CAS mask with all supported CAS Latencies */
 432         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 433                    SPD_CAS_LATENCY_DDR2_4 |
 434                    SPD_CAS_LATENCY_DDR2_5;
 435
 436         for (i=0; i<2*DIMM_SOCKETS; i++) {
 437                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 438                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 439         }
 440
 441         if(!cas_mask) {
 442                 die("No DDR-II modules with accepted CAS latencies found.\n");
 443         }
 444
 445         return cas_mask;
 446 }
 447
 448 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 449 {
 450         int i, j, idx;
 451         int lowest_common_cas = 0;
 452         int max_ram_speed = 0;
 453
 454         const u8 ddr2_speeds_table[] = {
 455                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 456                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 457                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 458         };
 459
 460         const u8 spd_lookup_table[] = {
 461                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 462                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 463                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 464         };
 465
 466         switch (sdram_capabilities_max_supported_memory_frequency()) {
 467         case 400: max_ram_speed = 0; break;
 468         case 533: max_ram_speed = 1; break;
 469         case 667: max_ram_speed = 2; break;
 470         }
 471
 472         if (fsbclk() == 533)
 473                 max_ram_speed = 1;
 474
 475         sysinfo->memory_frequency = 0;
 476         sysinfo->cas = 0;
 477
 478         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 479                 lowest_common_cas = 3;
 480         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 481                 lowest_common_cas = 4;
 482         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 483                 lowest_common_cas = 5;
 484         }
 485         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 486
 487         for (j = max_ram_speed; j>=0; j--) {
 488                 int freq_cas_mask = cas_mask;
 489
 490                 PRINTK_DEBUG("Probing Speed %d\n", j);
 491                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 492                         int current_cas_mask;
 493
 494                         PRINTK_DEBUG("  DIMM: %d\n", i);
 495                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 496                                 continue;
 497                         }
 498
 499                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 500
 501                         while (current_cas_mask) {
 502                                 int highest_supported_cas = 0, current_cas = 0;
 503                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 504                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 505                                         highest_supported_cas = 5;
 506                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 507                                         highest_supported_cas = 4;
 508                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 509                                         highest_supported_cas = 3;
 510                                 }
 511                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 512                                         current_cas = 3;
 513                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 514                                         current_cas = 4;
 515                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 516                                         current_cas = 5;
 517                                 }
 518
 519                                 idx = highest_supported_cas - current_cas;
 520                                 PRINTK_DEBUG("idx=%d, ", idx);
 521                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 522                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 523
 524                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 525                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 526                                         PRINTK_DEBUG(":    OK\n");
 527                                         break;
 528                                 }
 529
 530                                 PRINTK_DEBUG(":    Not fast enough!\n");
 531
 532                                 current_cas_mask &= ~(1 << (current_cas));
 533                         }
 534
 535                         freq_cas_mask &= current_cas_mask;
 536                         if (!current_cas_mask) {
 537                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 538                                 break;
 539                         }
 540                 }
 541                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 542                 if (freq_cas_mask) {
 543                         switch (j) {
 544                         case 0: sysinfo->memory_frequency = 400; break;
 545                         case 1: sysinfo->memory_frequency = 533; break;
 546                         case 2: sysinfo->memory_frequency = 667; break;
 547                         }
 548                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 549                                 sysinfo->cas = 3;
 550                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 551                                 sysinfo->cas = 4;
 552                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 553                                 sysinfo->cas = 5;
 554                         }
 555                         break;
 556                 }
 557         }
 558
 559         if (sysinfo->memory_frequency && sysinfo->cas) {
 560                 printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
 561                                 sysinfo->memory_frequency, sysinfo->cas);
 562         } else {
 563                 die("Could not find common memory frequency and CAS\n");
 564         }
 565 }
 566
 567 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 568 {
 569         int i;
 570         int tRAS_time;
 571         int tRAS_cycles;
 572         int freq_multiplier = 0;
 573
 574         switch (sysinfo->memory_frequency) {
 575         case 400: freq_multiplier = 0x14; break; /* 5ns */
 576         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 577         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 578         }
 579
 580         tRAS_cycles = 4; /* 4 clocks minimum */
 581         tRAS_time = tRAS_cycles * freq_multiplier;
 582
 583         for (i=0; i<2*DIMM_SOCKETS; i++) {
 584                 u8 reg8;
 585
 586                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 587                         continue;
 588
 589                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 590                 if (!reg8) {
 591                         die("Invalid tRAS value.\n");
 592                 }
 593
 594                 while ((tRAS_time >> 2) < reg8) {
 595                         tRAS_time += freq_multiplier;
 596                         tRAS_cycles++;
 597                 }
 598         }
 599         if(tRAS_cycles > 0x18) {
 600                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 601         }
 602
 603         printk_debug("tRAS = %d cycles\n", tRAS_cycles);
 604         sysinfo->tras = tRAS_cycles;
 605 }
 606
 607 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 608 {
 609         int i;
 610         int tRP_time;
 611         int tRP_cycles;
 612         int freq_multiplier = 0;
 613
 614         switch (sysinfo->memory_frequency) {
 615         case 400: freq_multiplier = 0x14; break; /* 5ns */
 616         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 617         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 618         }
 619
 620         tRP_cycles = 2; /* 2 clocks minimum */
 621         tRP_time = tRP_cycles * freq_multiplier;
 622
 623         for (i=0; i<2*DIMM_SOCKETS; i++) {
 624                 u8 reg8;
 625
 626                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 627                         continue;
 628
 629                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 630                 if (!reg8) {
 631                         die("Invalid tRP value.\n");
 632                 }
 633
 634                 while (tRP_time < reg8) {
 635                         tRP_time += freq_multiplier;
 636                         tRP_cycles++;
 637                 }
 638         }
 639
 640         if(tRP_cycles > 6) {
 641                 die("DDR-II Module does not support this frequency (tRP error)\n");
 642         }
 643
 644         printk_debug("tRP = %d cycles\n", tRP_cycles);
 645         sysinfo->trp = tRP_cycles;
 646 }
 647
 648 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 649 {
 650         int i;
 651         int tRCD_time;
 652         int tRCD_cycles;
 653         int freq_multiplier = 0;
 654
 655         switch (sysinfo->memory_frequency) {
 656         case 400: freq_multiplier = 0x14; break; /* 5ns */
 657         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 658         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 659         }
 660
 661         tRCD_cycles = 2; /* 2 clocks minimum */
 662         tRCD_time = tRCD_cycles * freq_multiplier;
 663
 664         for (i=0; i<2*DIMM_SOCKETS; i++) {
 665                 u8 reg8;
 666
 667                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 668                         continue;
 669
 670                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 671                 if (!reg8) {
 672                         die("Invalid tRCD value.\n");
 673                 }
 674
 675                 while (tRCD_time < reg8) {
 676                         tRCD_time += freq_multiplier;
 677                         tRCD_cycles++;
 678                 }
 679         }
 680         if(tRCD_cycles > 6) {
 681                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 682         }
 683
 684         printk_debug("tRCD = %d cycles\n", tRCD_cycles);
 685         sysinfo->trcd = tRCD_cycles;
 686 }
 687
 688 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 689 {
 690         int i;
 691         int tWR_time;
 692         int tWR_cycles;
 693         int freq_multiplier = 0;
 694
 695         switch (sysinfo->memory_frequency) {
 696         case 400: freq_multiplier = 0x14; break; /* 5ns */
 697         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 698         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 699         }
 700
 701         tWR_cycles = 2; /* 2 clocks minimum */
 702         tWR_time = tWR_cycles * freq_multiplier;
 703
 704         for (i=0; i<2*DIMM_SOCKETS; i++) {
 705                 u8 reg8;
 706
 707                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 708                         continue;
 709
 710                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 711                 if (!reg8) {
 712                         die("Invalid tWR value.\n");
 713                 }
 714
 715                 while (tWR_time < reg8) {
 716                         tWR_time += freq_multiplier;
 717                         tWR_cycles++;
 718                 }
 719         }
 720         if(tWR_cycles > 5) {
 721                 die("DDR-II Module does not support this frequency (tWR error)\n");
 722         }
 723
 724         printk_debug("tWR = %d cycles\n", tWR_cycles);
 725         sysinfo->twr = tWR_cycles;
 726 }
 727
 728 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 729 {
 730         int i, index = 0;
 731
 732         const u8 tRFC_cycles[] = {
 733              /* 75 105 127.5 */
 734                 15, 21, 26,     /* DDR2-400 */
 735                 20, 28, 34,     /* DDR2-533 */
 736                 25, 35, 43      /* DDR2-667 */
 737         };
 738
 739         for (i=0; i<2*DIMM_SOCKETS; i++) {
 740                 u8 reg8;
 741
 742                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 743                         continue;
 744
 745                 reg8 = sysinfo->banksize[i*2];
 746                 switch (reg8) {
 747                 case 0x04: reg8 = 0; break;
 748                 case 0x08: reg8 = 1; break;
 749                 case 0x10: reg8 = 2; break;
 750                 case 0x20: reg8 = 3; break;
 751                 }
 752
 753                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 754                         reg8++;
 755
 756                 if (reg8 > 3) {
 757                         /* Can this happen? Go back to 127.5ns just to be sure
 758                          * we don't run out of the array. This may be wrong
 759                          */
 760                         printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
 761                         reg8 = 3;
 762                 }
 763
 764                 if (reg8 > index)
 765                         index = reg8;
 766
 767         }
 768         index--;
 769         switch (sysinfo->memory_frequency) {
 770         case 667: index += 3; /* Fallthrough */
 771         case 533: index += 3; /* Fallthrough */
 772         case 400: break;
 773         }
 774
 775         sysinfo->trfc = tRFC_cycles[index];
 776         printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
 777 }
 778
 779 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 780 {
 781         int i;
 782
 783         sysinfo->refresh = 0;
 784
 785         for (i=0; i<2*DIMM_SOCKETS; i++) {
 786                 int refresh;
 787
 788                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 789                         continue;
 790
 791                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 792
 793                 /* 15.6us */
 794                 if (!refresh)
 795                         continue;
 796
 797                 /* Refresh is slower than 15.6us, use 15.6us */
 798                 if (refresh > 2)
 799                         continue;
 800
 801                 if (refresh == 2) {
 802                         sysinfo->refresh = 1;
 803                         break;
 804                 }
 805
 806                 die("DDR-II module has unsupported refresh value\n");
 807         }
 808         printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 809 }
 810
 811 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 812 {
 813         int i;
 814
 815         for (i=0; i<2*DIMM_SOCKETS; i++) {
 816                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 817                         continue;
 818
 819                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 820                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 821         }
 822 }
 823
 824 static void sdram_program_dram_width(struct sys_info * sysinfo)
 825 {
 826         u16 c0dramw=0, c1dramw=0;
 827         int idx;
 828
 829         if (sysinfo->dual_channel)
 830                 idx = 2;
 831         else
 832                 idx = 1;
 833
 834         switch (sysinfo->dimm[0]) {
 835         case 0: c0dramw = 0x0000; break; /* x16DS */
 836         case 1: c0dramw = 0x0001; break; /* x8DS */
 837         case 2: c0dramw = 0x0000; break; /* x16SS */
 838         case 3: c0dramw = 0x0005; break; /* x8DDS */
 839         case 4: c0dramw = 0x0000; break; /* NC */
 840         }
 841
 842         switch (sysinfo->dimm[idx]) {
 843         case 0: c1dramw = 0x0000; break; /* x16DS */
 844         case 1: c1dramw = 0x0010; break; /* x8DS */
 845         case 2: c1dramw = 0x0000; break; /* x16SS */
 846         case 3: c1dramw = 0x0050; break; /* x8DDS */
 847         case 4: c1dramw = 0x0000; break; /* NC */
 848         }
 849
 850         if ( !sdram_capabilities_dual_channel() ) {
 851                 /* Single Channel */
 852                 c0dramw |= c1dramw;
 853                 c1dramw = 0;
 854         }
 855
 856         MCHBAR16(C0DRAMW) = c0dramw;
 857         MCHBAR16(C1DRAMW) = c1dramw;
 858 }
 859
 860 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 861 {
 862         int i;
 863
 864         for (i=0; i<16; i++)
 865                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 866 }
 867
 868 static const u32 dq2030[] = {
 869         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 870         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 871         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 872         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 873 };
 874
 875 static const u32 dq2330[] = {
 876         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 877         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 878         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 879         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 880 };
 881
 882 static const u32 cmd2710[] = {
 883         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 884         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 885         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 886         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 887 };
 888
 889 static const u32 cmd3210[] = {
 890         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 891         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 892         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 893         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 894 };
 895
 896 static const u32 clk2030[] = {
 897         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 898         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 899         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 900         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 901 };
 902
 903 static const u32 ctl3215[] = {
 904         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 905         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 906         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 907         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 908 };
 909
 910 static const u32 ctl3220[] = {
 911         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 912         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 913         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 914         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 915 };
 916
 917 static const u32 nc[] = {
 918         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 919         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 920         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 921         0x00000000, 0x00000000, 0x00000000, 0x00000000
 922 };
 923
 924 enum {
 925         DQ2030,
 926         DQ2330,
 927         CMD2710,
 928         CMD3210,
 929         CLK2030,
 930         CTL3215,
 931         CTL3220,
 932         NC,
 933 };
 934
 935 static const u8 dual_channel_slew_group_lookup[] = {
 936         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 937         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 938         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 939         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 940         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 941
 942         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 943         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 944         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 945         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 946         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 947
 948         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 949         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 950         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 951         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 952         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 953
 954         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 955         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 956         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 957         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 958         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 959
 960         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 961         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 962         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 963         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 964 };
 965
 966 static const u8 single_channel_slew_group_lookup[] = {
 967         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 968         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 969         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 970         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 971         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 972
 973         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 974         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 975         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 976         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 977         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 978
 979         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 980         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 981         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 982         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 983         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 984
 985         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 986         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 987         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 988         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 989         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 990
 991         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 992         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 993         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 994         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
 995 };
 996
 997 static const u32 *slew_group_lookup(int dual_channel, int index)
 998 {
 999         const u8 *slew_group;
1000         /* Dual Channel needs different tables. */
1001         if (dual_channel)
1002                 slew_group   = dual_channel_slew_group_lookup;
1003         else
1004                 slew_group   = single_channel_slew_group_lookup;
1005
1006         switch (slew_group[index]) {
1007         case DQ2030:    return dq2030;
1008         case DQ2330:    return dq2330;
1009         case CMD2710:   return cmd2710;
1010         case CMD3210:   return cmd3210;
1011         case CLK2030:   return clk2030;
1012         case CTL3215:   return ctl3215;
1013         case CTL3220:   return ctl3220;
1014         case NC:        return nc;
1015         }
1016
1017         return nc;
1018 }
1019
1020 #ifdef CHIPSET_I945GM
1021 /* Strength multiplier tables */
1022 static const u8 dual_channel_strength_multiplier[] = {
1023         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1024         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1025         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1026         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1027         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1028         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1029         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1030         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1031         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1032         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1033         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1034         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1035         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1036         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1037         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1038         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1039         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1040         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1041         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1042         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1043         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1044         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1045         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1046         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1047 };
1048
1049 static const u8 single_channel_strength_multiplier[] = {
1050         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1051         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1052         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1053         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1054         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1055         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1056         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1057         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1058         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1059         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1060         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1061         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1062         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1063         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1064         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1065         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1066         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1067         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1068         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1069         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1070         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1071         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1072         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1073         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1074 };
1075 #endif
1076 #ifdef CHIPSET_I945GC
1077 static const u8 dual_channel_strength_multiplier[] = {
1078         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1079         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1080         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1081         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1082         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1083         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1084         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1085         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1086         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1087         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1088         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1089         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1090         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1091         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1092         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1093         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1094         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1095         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1096         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1097         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1098         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1099         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1100         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1101         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1102 };
1103
1104 static const u8 single_channel_strength_multiplier[] = {
1105         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1106         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1107         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1108         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1109         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1110         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1111         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1112         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1113         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1114         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1115         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1116         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1117         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1118         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1119         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1120         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1121         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1122         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1123         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1124         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1125         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1126         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1127         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1128         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1129 };
1130 #endif
1131
1132 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1133 {
1134         const u8 * strength_multiplier;
1135         int idx, dual_channel;
1136
1137         /* Set Strength Multipliers */
1138
1139         /* Dual Channel needs different tables. */
1140         if (sdram_capabilities_dual_channel()) {
1141                 printk_debug("Programming Dual Channel RCOMP\n");
1142                 strength_multiplier = dual_channel_strength_multiplier;
1143                 dual_channel = 1;
1144                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1145         } else {
1146                 printk_debug("Programming Single Channel RCOMP\n");
1147                 strength_multiplier = single_channel_strength_multiplier;
1148                 dual_channel = 0;
1149                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1150         }
1151
1152         printk_debug("Table Index: %d\n", idx);
1153
1154         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1155         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1156         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1157         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1158         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1159         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1160         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1161         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1162
1163         /* Channel 0 */
1164         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1165         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1166         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1167
1168                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1169         } else {
1170                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1171         }
1172         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1173         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1174         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1175
1176         /* Channel 1 */
1177         if (sysinfo->dual_channel) {
1178                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1179                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1180         } else {
1181                 sdram_write_slew_rates(G7SRPUT, nc);
1182                 sdram_write_slew_rates(G8SRPUT, nc);
1183         }
1184 }
1185
1186 static void sdram_enable_rcomp(void)
1187 {
1188         u32 reg32;
1189         /* Enable Global Periodic RCOMP */
1190         udelay(300);
1191         reg32 = MCHBAR32(GBRCOMPCTL);
1192         reg32 &= ~(1 << 23);
1193         MCHBAR32(GBRCOMPCTL) = reg32;
1194 }
1195
1196 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1197 {
1198         u32 chan0dll = 0, chan1dll = 0;
1199         int i;
1200
1201         printk_debug ("Programming DLL Timings... \n");
1202
1203         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1204         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1205
1206         /* We drive both channels with the same speed */
1207         switch (sysinfo->memory_frequency) {
1208         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1209         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1210         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1211         }
1212
1213         for (i=0; i < 4; i++) {
1214                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1215                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1216                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1217                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1218         }
1219 }
1220
1221 static void sdram_force_rcomp(void)
1222 {
1223         u32 reg32;
1224         u8 reg8;
1225
1226         reg32 = MCHBAR32(ODTC);
1227         reg32 |= (1 << 28);
1228         MCHBAR32(ODTC) = reg32;
1229
1230         reg32 = MCHBAR32(SMSRCTL);
1231         reg32 |= (1 << 0);
1232         MCHBAR32(SMSRCTL) = reg32;
1233
1234         /* Start initial RCOMP */
1235         reg32 = MCHBAR32(GBRCOMPCTL);
1236         reg32 |= (1 << 8);
1237         MCHBAR32(GBRCOMPCTL) = reg32;
1238
1239         reg8 = i945_silicon_revision();
1240         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1241
1242                 reg32 = MCHBAR32(GBRCOMPCTL);
1243                 reg32 |= (3 << 5);
1244                 MCHBAR32(GBRCOMPCTL) = reg32;
1245         }
1246 }
1247
1248 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1249 {
1250         u8 reg8;
1251         u32 reg32;
1252
1253         printk_debug ("Initializing System Memory IO... \n");
1254         /* Enable Data Half Clock Pushout */
1255         reg8 = MCHBAR8(C0HCTC);
1256         reg8 &= ~0x1f;
1257         reg8 |= ( 1 << 0);
1258         MCHBAR8(C0HCTC) = reg8;
1259
1260         reg8 = MCHBAR8(C1HCTC);
1261         reg8 &= ~0x1f;
1262         reg8 |= ( 1 << 0);
1263         MCHBAR8(C1HCTC) = reg8;
1264
1265         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1266         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1267
1268         MCHBAR8(C0WDLLCMC) = 0;
1269         MCHBAR8(C1WDLLCMC) = 0;
1270
1271         /* Program RCOMP Settings */
1272         sdram_program_dram_width(sysinfo);
1273
1274         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1275
1276         /* Indicate that RCOMP programming is done */
1277         reg32 = MCHBAR32(GBRCOMPCTL);
1278         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1279         reg32 |= (3 << 27) | (3 << 0);
1280         MCHBAR32(GBRCOMPCTL) = reg32;
1281
1282         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1283
1284         /* Program DLL Timings */
1285         sdram_program_dll_timings(sysinfo);
1286
1287         /* Force RCOMP cycle */
1288         sdram_force_rcomp();
1289 }
1290
1291 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1292 {
1293         u32 reg32;
1294
1295         printk_debug ("Enabling System Memory IO... \n");
1296
1297         reg32 = MCHBAR32(RCVENMT);
1298         reg32 &= ~(0x3f << 6);
1299         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1300
1301         reg32 |= (1 << 11) | (1 << 9);
1302         MCHBAR32(RCVENMT) = reg32;
1303
1304         reg32 = MCHBAR32(DRTST);
1305         reg32 |= (1 << 3) | (1 << 2);
1306         MCHBAR32(DRTST) = reg32;
1307
1308         reg32 = MCHBAR32(DRTST);
1309         reg32 |= (1 << 6) | (1 << 4);
1310         MCHBAR32(DRTST) = reg32;
1311
1312         asm volatile ("nop; nop;");
1313
1314         reg32 = MCHBAR32(DRTST);
1315
1316         /* Is channel 0 populated? */
1317         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1318                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1319                 reg32 |= (1 << 7) | (1 << 5);
1320         else
1321                 reg32 |= (1 << 31);
1322
1323         /* Is channel 1 populated? */
1324         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1325                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1326                 reg32 |= (1 << 9) | (1 << 8);
1327         else
1328                 reg32 |= (1 << 30);
1329
1330         MCHBAR32(DRTST) = reg32;
1331
1332         /* Activate DRAM Channel IO Buffers */
1333         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1334                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1335                 reg32 = MCHBAR32(C0DRC1);
1336                 reg32 |= (1 << 8);
1337                 MCHBAR32(C0DRC1) = reg32;
1338         }
1339         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1340                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1341                 reg32 = MCHBAR32(C1DRC1);
1342                 reg32 |= (1 << 8);
1343                 MCHBAR32(C1DRC1) = reg32;
1344         }
1345 }
1346
1347 struct dimm_size {
1348         unsigned long side1;
1349         unsigned long side2;
1350 };
1351
1352 static struct dimm_size sdram_get_dimm_size(u16 device)
1353 {
1354         /* Calculate the log base 2 size of a DIMM in bits */
1355         struct dimm_size sz;
1356         int value, low, rows, columns;
1357
1358         sz.side1 = 0;
1359         sz.side2 = 0;
1360
1361         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1362         if (rows < 0) goto hw_err;
1363         if ((rows & 0xf) == 0) goto val_err;
1364         sz.side1 += rows & 0xf;
1365
1366         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1367         if (columns < 0) goto hw_err;
1368         if ((columns & 0xf) == 0) goto val_err;
1369         sz.side1 += columns & 0xf;
1370
1371         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1372         if (value < 0) goto hw_err;
1373         if ((value & 0xff) == 0) goto val_err;
1374         sz.side1 += log2(value & 0xff);
1375
1376         /* Get the module data width and convert it to a power of two */
1377         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1378         if (value < 0) goto hw_err;
1379         value &= 0xff;
1380         value <<= 8;
1381
1382         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1383         if (low < 0) goto hw_err;
1384         value = value | (low & 0xff);
1385         if ((value != 72) && (value != 64)) goto val_err;
1386         sz.side1 += log2(value);
1387
1388         /* side 2 */
1389         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1390
1391         if (value < 0) goto hw_err;
1392         value &= 7;
1393         value++;
1394         if (value == 1) goto out;
1395         if (value != 2) goto val_err;
1396
1397         /* Start with the symmetrical case */
1398         sz.side2 = sz.side1;
1399
1400         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1401
1402         /* Don't die here, I have not come across any of these to test what
1403          * actually happens.
1404          */
1405         printk_err("Assymetric DIMMs are not supported by this chipset\n");
1406
1407         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1408         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1409
1410         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1411         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1412
1413         goto out;
1414
1415  val_err:
1416         die("Bad SPD value\n");
1417  hw_err:
1418         /* If a hardware error occurs the spd rom probably does not exist.
1419          * In this case report that there is no memory
1420          */
1421         sz.side1 = 0;
1422         sz.side2 = 0;
1423  out:
1424         return sz;
1425 }
1426
1427 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1428 {
1429         int i;
1430
1431         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1432                 struct dimm_size sz;
1433
1434                 sysinfo->banksize[i * 2] = 0;
1435                 sysinfo->banksize[(i * 2) + 1] = 0;
1436
1437                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1438                         continue;
1439
1440                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1441
1442                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1443
1444                 if (sz.side1 < 30)
1445                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1446
1447                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1448
1449                 printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1450
1451                 if (!sz.side2)
1452                         continue;
1453
1454                 /* If there is a second side, it has to have at least 128M, too */
1455                 if (sz.side2 < 30)
1456                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1457
1458                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1459
1460                 printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1461         }
1462 }
1463
1464 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1465 {
1466         int i;
1467         int cum0, cum1, tolud, tom;
1468
1469         printk_debug ("Setting RAM size... \n");
1470
1471         cum0 = 0;
1472         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1473                 cum0 += sysinfo->banksize[i];
1474                 MCHBAR8(C0DRB0+i) = cum0;
1475         }
1476
1477         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1478         cum1 = cum0;
1479
1480         /* Exception: Interleaved starts from the beginning */
1481         if (sysinfo->interleaved)
1482                 cum1 = 0;
1483
1484 #if 0
1485         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1486         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1487                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1488                 cum1 = 0;
1489 #endif
1490
1491         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1492                 cum1 += sysinfo->banksize[i + 4];
1493                 MCHBAR8(C1DRB0+i) = cum1;
1494         }
1495
1496         /* Set TOLUD Top Of Low Usable DRAM */
1497         if (sysinfo->interleaved)
1498                 tolud = (cum0 + cum1) << 1;
1499         else
1500                 tolud = (cum1 ? cum1 : cum0)  << 1;
1501
1502         /* The TOM register has a different format */
1503         tom = tolud >> 3;
1504
1505         /* Limit the value of TOLUD to leave some space for PCI memory. */
1506         if (tolud > 0xd0)
1507                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1508
1509         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1510
1511         printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1512         printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1513         printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1514
1515         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1516
1517         return 0;
1518 }
1519
1520 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1521 {
1522         int i, value;
1523         u16 dra0=0, dra1=0, dra = 0;
1524
1525         printk_debug ("Setting row attributes... \n");
1526         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1527                 u16 device;
1528                 u8 columnsrows;
1529
1530                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1531                         continue;
1532                 }
1533
1534                 device = DIMM_SPD_BASE + i;
1535
1536                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1537                 columnsrows = (value & 0x0f);
1538
1539                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1540                 columnsrows |= (value & 0xf) << 4;
1541
1542                 switch (columnsrows) {
1543                 case 0x9d: dra = 2; break;
1544                 case 0xad: dra = 3; break;
1545                 case 0xbd: dra = 4; break;
1546                 case 0xae: dra = 3; break;
1547                 case 0xbe: dra = 4; break;
1548                 default: die("Unsupported Rows/Columns. (DRA)");
1549                 }
1550
1551                 /* Double Sided DIMMs? */
1552                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1553                         dra = (dra << 4) | dra;
1554                 }
1555
1556                 if (i < DIMM_SOCKETS)
1557                         dra0 |= (dra << (i*8));
1558                 else
1559                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1560         }
1561
1562         MCHBAR16(C0DRA0) = dra0;
1563         MCHBAR16(C1DRA0) = dra1;
1564
1565         printk_debug("C0DRA = 0x%04x\n", dra0);
1566         printk_debug("C1DRA = 0x%04x\n", dra1);
1567
1568         return 0;
1569 }
1570
1571 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1572 {
1573         u32 off32;
1574         int i;
1575
1576         MCHBAR16(C1BNKARC) &= 0xff00;
1577         MCHBAR16(C0BNKARC) &= 0xff00;
1578
1579         off32 = C0BNKARC;
1580         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1581                 /* Switch to second channel */
1582                 if (i == DIMM_SOCKETS)
1583                         off32 = C1BNKARC;
1584
1585                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1586                         continue;
1587
1588                 if (sysinfo->banks[i] != 8)
1589                         continue;
1590
1591                 printk_spew("DIMM%d has 8 banks.\n", i);
1592
1593                 if (i & 1)
1594                         MCHBAR16(off32) |= 0x50;
1595                 else
1596                         MCHBAR16(off32) |= 0x05;
1597         }
1598 }
1599
1600 #define REFRESH_7_8US   1
1601 #define REFRESH_15_6US  0
1602 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1603 {
1604         u32 reg32;
1605
1606         if (sysinfo->refresh == REFRESH_7_8US) {
1607                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1608         } else {
1609                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1610         }
1611
1612         MCHBAR32(C0DRC0) &= ~(7 << 8);
1613         MCHBAR32(C0DRC0) |= reg32;
1614
1615         MCHBAR32(C1DRC0) &= ~(7 << 8);
1616         MCHBAR32(C1DRC0) |= reg32;
1617 }
1618
1619 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1620 {
1621         u32 reg32;
1622         int i;
1623
1624         reg32 = MCHBAR32(C0DRC1);
1625
1626         for (i=0; i < 4; i++) {
1627                 if (sysinfo->banksize[i] == 0) {
1628                         reg32 |= (1 << (16 + i));
1629                 }
1630         }
1631
1632         reg32 |= (1 << 12);
1633
1634         reg32 |= (1 << 11);
1635         MCHBAR32(C0DRC1) = reg32;
1636
1637         /* Do we have to do this if we're in Single Channel Mode?  */
1638         reg32 = MCHBAR32(C1DRC1);
1639
1640         for (i=4; i < 8; i++) {
1641                 if (sysinfo->banksize[i] == 0) {
1642                         reg32 |= (1 << (12 + i));
1643                 }
1644         }
1645
1646         reg32 |= (1 << 12);
1647
1648         reg32 |= (1 << 11);
1649         MCHBAR32(C1DRC1) = reg32;
1650 }
1651
1652 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1653 {
1654         u32 reg32;
1655         int i;
1656
1657         reg32 = MCHBAR32(C0DRC2);
1658
1659         for (i=0; i < 4; i++) {
1660                 if (sysinfo->banksize[i] == 0) {
1661                         reg32 |= (1 << (24 + i));
1662                 }
1663         }
1664         MCHBAR32(C0DRC2) = reg32;
1665
1666         reg32 = MCHBAR32(C1DRC2);
1667
1668         for (i=4; i < 8; i++) {
1669                 if (sysinfo->banksize[i] == 0) {
1670                         reg32 |= (1 << (20 + i));
1671                 }
1672         }
1673         MCHBAR32(C1DRC2) = reg32;
1674 }
1675
1676 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1677 {
1678         u32 reg32, off32;
1679         u32 tWTR;
1680         u32 temp_drt;
1681         int i, page_size;
1682
1683         static const u8 const drt0_table[] = {
1684           /* CL 3, 4, 5 */
1685                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1686                 4, 5, 6,        /* FSB667, DDR533/400 */
1687                 4, 5, 6,        /* FSB667, DDR667 */
1688         };
1689
1690         static const u8 const cas_table[] = {
1691                 2, 1, 0, 3
1692         };
1693
1694         reg32 = MCHBAR32(C0DRC0);
1695         reg32 |= (1 << 2);      /* Burst Length 8 */
1696         reg32 &= ~( (1 << 13) | (1 << 12) );
1697         MCHBAR32(C0DRC0) = reg32;
1698
1699         reg32 = MCHBAR32(C1DRC0);
1700         reg32 |= (1 << 2);      /* Burst Length 8 */
1701         reg32 &= ~( (1 << 13) | (1 << 12) );
1702         MCHBAR32(C1DRC0) = reg32;
1703
1704         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1705                         SYSINFO_DIMM_NOT_POPULATED) {
1706                 reg32 = MCHBAR32(C0DRC0);
1707                 reg32 |= (1 << 15);
1708                 MCHBAR32(C0DRC0) = reg32;
1709         }
1710
1711         sdram_program_refresh_rate(sysinfo);
1712
1713         sdram_program_cke_tristate(sysinfo);
1714
1715         sdram_program_odt_tristate(sysinfo);
1716
1717         /* Calculate DRT0 */
1718
1719         temp_drt = 0;
1720
1721         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1722         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1723         temp_drt |= (reg32 << 28);
1724
1725         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1726         reg32 += sysinfo->trp;
1727         temp_drt |= (reg32 << 4);
1728
1729         if (sysinfo->memory_frequency == 667) {
1730                 tWTR = 3; /* 667MHz */
1731         } else {
1732                 tWTR = 2; /* 400 and 533 */
1733         }
1734
1735         /* B2B Write to Read Command Spacing */
1736         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1737         temp_drt |= (reg32 << 24);
1738
1739         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1740         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1741
1742         /* Program Write Auto Precharge to Activate */
1743         off32 = 0;
1744         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1745                 off32 += 3;
1746         }
1747         if (sysinfo->memory_frequency == 667) {
1748                 off32 += 3;
1749         }
1750         off32 += sysinfo->cas - 3;
1751         reg32 = drt0_table[off32];
1752         temp_drt |= (reg32 << 11);
1753
1754         /* Read Auto Precharge to Activate */
1755
1756         temp_drt |= (8 << 0);
1757
1758         MCHBAR32(C0DRT0) = temp_drt;
1759         MCHBAR32(C1DRT0) = temp_drt;
1760
1761         /* Calculate DRT1 */
1762
1763         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1764
1765         /* DRAM RASB Precharge */
1766         temp_drt |= (sysinfo->trp - 2) << 0;
1767
1768         /* DRAM RASB to CASB Delay */
1769         temp_drt |= (sysinfo->trcd - 2) << 4;
1770
1771         /* CASB Latency */
1772         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1773
1774         /* Refresh Cycle Time */
1775         temp_drt |= (sysinfo->trfc) << 10;
1776
1777         /* Pre-All to Activate Delay */
1778         temp_drt |= (0 << 16);
1779
1780         /* Precharge to Precharge Delay stays at 1 clock */
1781         temp_drt |= (0 << 18);
1782
1783         /* Activate to Precharge Delay */
1784         temp_drt |= (sysinfo->tras << 19);
1785
1786         /* Read to Precharge (tRTP) */
1787         if (sysinfo->memory_frequency == 667) {
1788                 temp_drt |= (1 << 28);
1789         } else {
1790                 temp_drt |= (0 << 28);
1791         }
1792
1793         /* Determine page size */
1794         reg32 = 0;
1795         page_size = 1; /* Default: 1k pagesize */
1796         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1797                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1798                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1799                         page_size = 2; /* 2k pagesize */
1800         }
1801
1802         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1803                 reg32 = 1;
1804         }
1805         if (sysinfo->memory_frequency == 667) {
1806                 reg32 = page_size;
1807         }
1808
1809         temp_drt |= (reg32 << 30);
1810
1811         MCHBAR32(C0DRT1) = temp_drt;
1812         MCHBAR32(C1DRT1) = temp_drt;
1813
1814         /* Program DRT2 */
1815         reg32 = MCHBAR32(C0DRT2);
1816         reg32 &= ~(1 << 8);
1817         MCHBAR32(C0DRT2) = reg32;
1818
1819         reg32 = MCHBAR32(C1DRT2);
1820         reg32 &= ~(1 << 8);
1821         MCHBAR32(C1DRT2) = reg32;
1822
1823         /* Calculate DRT3 */
1824         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1825
1826         /* Get old tRFC value */
1827         reg32 = MCHBAR32(C0DRT1) >> 10;
1828         reg32 &= 0x3f;
1829
1830         /* 788nS - tRFC */
1831         switch (sysinfo->memory_frequency) {
1832         case 400: /* 5nS */
1833                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1834                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1835                 break;
1836         case 533: /* 3.75nS */
1837                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1838                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1839                 break;
1840         case 667: /* 3nS */
1841                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1842                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1843                 break;
1844         }
1845
1846         temp_drt |= reg32;
1847
1848         MCHBAR32(C0DRT3) = temp_drt;
1849         MCHBAR32(C1DRT3) = temp_drt;
1850 }
1851
1852 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1853 {
1854         u32 reg32;
1855
1856         printk_debug("Setting mode of operation for memory channels...");
1857
1858         if (sdram_capabilities_interleave() &&
1859                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1860                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1861                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1862                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1863                 /* Both channels equipped with DIMMs of the same size */
1864                 sysinfo->interleaved = 1;
1865         } else {
1866                 sysinfo->interleaved = 0;
1867         }
1868
1869         reg32 = MCHBAR32(DCC);
1870         reg32 &= ~(7 << 0);
1871
1872         if(sysinfo->interleaved) {
1873                 /* Dual Channel Interleaved */
1874                 printk_debug("Dual Channel Interleaved.\n");
1875                 reg32 |= (1 << 1);
1876         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1877                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1878                 /* Channel 1 only */
1879                 printk_debug("Single Channel 1 only.\n");
1880                 reg32 |= (1 << 2);
1881         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1882                         SYSINFO_DIMM_NOT_POPULATED) {
1883                 /* Dual Channel Assymetric */
1884                 printk_debug("Dual Channel Assymetric.\n");
1885                 reg32 |= (1 << 0);
1886         } else {
1887                 /* All bits 0 means Single Channel 0 operation */
1888                 printk_debug("Single Channel 0 only.\n");
1889         }
1890
1891         reg32 |= (1 << 10);
1892
1893         MCHBAR32(DCC) = reg32;
1894
1895         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1896 }
1897
1898 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1899 {
1900         volatile u16 reg16;
1901
1902         MCHBAR32(PLLMON) = 0x80800000;
1903
1904         sysinfo->fsb_frequency = fsbclk();
1905         if (sysinfo->fsb_frequency == -1)
1906                 die("Unsupported FSB speed");
1907
1908         /* Program CPCTL according to FSB speed */
1909         /* Only write the lower byte */
1910         switch (sysinfo->fsb_frequency) {
1911         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1912         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1913         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1914         }
1915
1916         MCHBAR16(CPCTL) &= ~(1 << 11);
1917
1918         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1919 }
1920
1921 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1922 {
1923         u8  reg8;
1924         u16 reg16;
1925         u8  freq, second_vco, voltage;
1926
1927 #define CRCLK_166MHz    0x00
1928 #define CRCLK_200MHz    0x01
1929 #define CRCLK_250MHz    0x03
1930 #define CRCLK_400MHz    0x05
1931
1932 #define CDCLK_200MHz    0x00
1933 #define CDCLK_320MHz    0x40
1934
1935 #define VOLTAGE_1_05    0x00
1936 #define VOLTAGE_1_50    0x01
1937
1938         printk_debug ("Setting Graphics Frequency... \n");
1939
1940         printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
1941
1942         voltage = VOLTAGE_1_05;
1943         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1944                 voltage = VOLTAGE_1_50;
1945         printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1946
1947         /* Gate graphics hardware for frequency change */
1948         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1949         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1950         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1951
1952         /* Get graphics frequency capabilities */
1953         reg8 = sdram_capabilities_core_frequencies();
1954
1955         freq = CRCLK_250MHz;
1956         switch (reg8) {
1957         case GFX_FREQUENCY_CAP_ALL:
1958                 if (voltage == VOLTAGE_1_05)
1959                         freq = CRCLK_250MHz;
1960                 else
1961                         freq = CRCLK_400MHz;
1962                 break;
1963         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1964         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1965         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
1966         }
1967
1968         if (freq != CRCLK_400MHz) {
1969                 /* What chipset are we? Force 166MHz for GMS */
1970                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1971                 if (reg8==2)
1972                         freq = CRCLK_166MHz;
1973         }
1974
1975         printk_debug("Render: ");
1976         switch (freq) {
1977         case CRCLK_166MHz: printk_debug("166Mhz"); break;
1978         case CRCLK_200MHz: printk_debug("200Mhz"); break;
1979         case CRCLK_250MHz: printk_debug("250Mhz"); break;
1980         case CRCLK_400MHz: printk_debug("400Mhz"); break;
1981         }
1982
1983         if (i945_silicon_revision() == 0) {
1984                 sysinfo->mvco4x = 1;
1985         } else {
1986                 sysinfo->mvco4x = 0;
1987         }
1988
1989         second_vco = 0;
1990
1991         if (voltage == VOLTAGE_1_50) {
1992                 second_vco = 1;
1993         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
1994                 u16 mem = sysinfo->memory_frequency;
1995                 u16 fsb = sysinfo->fsb_frequency;
1996
1997                 if ( (fsb == 667 && mem == 533) ||
1998                      (fsb == 533 && mem == 533) ||
1999                      (fsb == 533 && mem == 400)) {
2000                         second_vco = 1;
2001                 }
2002
2003                 if (fsb == 667 && mem == 533)
2004                         sysinfo->mvco4x = 1;
2005         }
2006
2007         if (second_vco) {
2008                 sysinfo->clkcfg_bit7=1;
2009         } else {
2010                 sysinfo->clkcfg_bit7=0;
2011         }
2012
2013         /* Graphics Core Render Clock */
2014         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2015         reg16 &= ~( (7 << 0) | (1 << 13) );
2016         reg16 |= freq;
2017         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2018
2019         /* Graphics Core Display Clock */
2020         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2021         reg8 &= ~( (1<<7) | (7<<4) );
2022
2023         if (voltage == VOLTAGE_1_05) {
2024                 reg8 |= CDCLK_200MHz;
2025                 printk_debug(" Display: 200MHz\n");
2026         } else {
2027                 reg8 |= CDCLK_320MHz;
2028                 printk_debug(" Display: 320MHz\n");
2029         }
2030         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2031
2032         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2033
2034         reg8 |= (1<<3) | (1<<1);
2035         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2036
2037         reg8 |= 0x0f;
2038         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2039
2040         /* Ungate core render and display clocks */
2041         reg8 &= 0xf0;
2042         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2043 }
2044
2045 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2046 {
2047         u32 clkcfg;
2048         u8 reg8;
2049         u8 offset = 0;
2050 #ifdef CHIPSET_I945GM
2051         offset++;
2052 #endif
2053
2054         printk_debug ("Setting Memory Frequency... ");
2055
2056         clkcfg = MCHBAR32(CLKCFG);
2057
2058         printk_debug("CLKCFG=0x%08x, ", clkcfg);
2059
2060         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2061
2062         if (sysinfo->mvco4x) {
2063                 printk_debug("MVCO 4x, ");
2064                 clkcfg &= ~(1 << 12);
2065         }
2066
2067         if (sysinfo->clkcfg_bit7) {
2068                 printk_debug("second VCO, ");
2069
2070                 clkcfg |= (1 << 7);
2071         }
2072
2073         switch (sysinfo->memory_frequency) {
2074         case 400: clkcfg |= ((1+offset) << 4); break;
2075         case 533: clkcfg |= ((2+offset) << 4); break;
2076         case 667: clkcfg |= ((3+offset) << 4); break;
2077         default: die("Target Memory Frequency Error");
2078         }
2079
2080         if (MCHBAR32(CLKCFG) == clkcfg) {
2081                 printk_debug ("ok (unchanged)\n");
2082                 return;
2083         }
2084
2085         MCHBAR32(CLKCFG) = clkcfg;
2086
2087         /* Make sure the following code is in the
2088          * cache before we execute it.
2089          */
2090         goto cache_code;
2091 vco_update:
2092         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2093         reg8 &= ~(1 << 7);
2094         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2095
2096         clkcfg &= ~(1 << 10);
2097         MCHBAR32(CLKCFG) = clkcfg;
2098         clkcfg |= (1 << 10);
2099         MCHBAR32(CLKCFG) = clkcfg;
2100
2101         __asm__ __volatile__ (
2102                 "       movl $0x100, %%ecx\n"
2103                 "delay_update:\n"
2104                 "       nop\n"
2105                 "       nop\n"
2106                 "       nop\n"
2107                 "       nop\n"
2108                 "       loop delay_update\n"
2109                 : /* No outputs */
2110                 : /* No inputs */
2111                 : "%ecx"
2112                 );
2113
2114         clkcfg &= ~(1 << 10);
2115         MCHBAR32(CLKCFG) = clkcfg;
2116
2117         goto out;
2118 cache_code:
2119         goto vco_update;
2120 out:
2121
2122         printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2123         printk_debug ("ok\n");
2124 }
2125
2126 static void sdram_program_clock_crossing(void)
2127 {
2128         int idx = 0;
2129
2130         /**
2131          * We add the indices according to our clocks from CLKCFG.
2132          */
2133 #ifdef CHIPSET_I945GM
2134         static const u32 data_clock_crossing[] = {
2135                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2136                 0xffffffff, 0xffffffff, /*  nonexistant  */
2137                 0xffffffff, 0xffffffff, /*  nonexistant  */
2138
2139                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2140                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2141                 0xffffffff, 0xffffffff, /*  nonexistant  */
2142
2143                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2144                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2145                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2146
2147                 0xffffffff, 0xffffffff, /*  nonexistant  */
2148                 0xffffffff, 0xffffffff, /*  nonexistant  */
2149                 0xffffffff, 0xffffffff, /*  nonexistant  */
2150
2151                 0xffffffff, 0xffffffff, /*  nonexistant  */
2152                 0xffffffff, 0xffffffff, /*  nonexistant  */
2153                 0xffffffff, 0xffffffff, /*  nonexistant  */
2154         };
2155
2156         static const u32 command_clock_crossing[] = {
2157                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2158                 0xffffffff, 0xffffffff, /*  nonexistant  */
2159                 0xffffffff, 0xffffffff, /*  nonexistant  */
2160
2161                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2162                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2163                 0xffffffff, 0xffffffff, /*  nonexistant  */
2164
2165                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2166                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2167                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2168
2169                 0xffffffff, 0xffffffff, /*  nonexistant  */
2170                 0xffffffff, 0xffffffff, /*  nonexistant  */
2171                 0xffffffff, 0xffffffff, /*  nonexistant  */
2172
2173                 0xffffffff, 0xffffffff, /*  nonexistant  */
2174                 0xffffffff, 0xffffffff, /*  nonexistant  */
2175                 0xffffffff, 0xffffffff, /*  nonexistant  */
2176         };
2177
2178 #endif
2179 #ifdef CHIPSET_I945GC
2180         /* i945 G/P */
2181         static const u32 data_clock_crossing[] = {
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183                 0xffffffff, 0xffffffff, /*  nonexistant  */
2184                 0xffffffff, 0xffffffff, /*  nonexistant  */
2185
2186                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2187                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2188                 0xffffffff, 0xffffffff, /*  nonexistant  */
2189
2190                 0xffffffff, 0xffffffff, /*  nonexistant  */
2191                 0xffffffff, 0xffffffff, /*  nonexistant  */
2192                 0xffffffff, 0xffffffff, /*  nonexistant  */
2193
2194                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2195                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2196                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2197
2198                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2199                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2200                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2201         };
2202
2203         static const u32 command_clock_crossing[] = {
2204                 0xffffffff, 0xffffffff, /*  nonexistant  */
2205                 0xffffffff, 0xffffffff, /*  nonexistant  */
2206                 0xffffffff, 0xffffffff, /*  nonexistant  */
2207
2208                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2209                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2210                 0xffffffff, 0xffffffff, /*  nonexistant  */
2211
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214                 0xffffffff, 0xffffffff, /*  nonexistant  */
2215
2216                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2217                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2218                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2219
2220                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2221                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2222                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2223         };
2224 #endif
2225
2226         printk_debug("Programming Clock Crossing...");
2227
2228         printk_debug("MEM=");
2229         switch (memclk()) {
2230         case 400:       printk_debug("400"); idx += 0; break;
2231         case 533:       printk_debug("533"); idx += 2; break;
2232         case 667:       printk_debug("667"); idx += 4; break;
2233         default: printk_debug("RSVD %x", memclk()); return;
2234         }
2235
2236         printk_debug(" FSB=");
2237         switch (fsbclk()) {
2238         case 400:       printk_debug("400"); idx += 0; break;
2239         case 533:       printk_debug("533"); idx += 6; break;
2240         case 667:       printk_debug("667"); idx += 12; break;
2241         case 800:       printk_debug("800"); idx += 18; break;
2242         case 1066:      printk_debug("1066"); idx += 24; break;
2243         default: printk_debug("RSVD %x\n", fsbclk()); return;
2244         }
2245
2246         if (command_clock_crossing[idx]==0xffffffff) {
2247                 printk_debug("Invalid MEM/FSB combination!\n");
2248         }
2249
2250         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2251         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2252
2253         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2254         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2255         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2256         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2257
2258         printk_debug("... ok\n");
2259 }
2260
2261 static void sdram_disable_fast_dispatch(void)
2262 {
2263         u32 reg32;
2264
2265         reg32 = MCHBAR32(FSBPMC3);
2266         reg32 |= (1 << 1);
2267         MCHBAR32(FSBPMC3) = reg32;
2268
2269         reg32 = MCHBAR32(SBTEST);
2270         reg32 |= (3 << 1);
2271         MCHBAR32(SBTEST) = reg32;
2272 }
2273
2274 static void sdram_pre_jedec_initialization(void)
2275 {
2276         u32 reg32;
2277
2278         reg32 = MCHBAR32(WCC);
2279         reg32 &= 0x113ff3ff;
2280         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2281         MCHBAR32(WCC) = reg32;
2282
2283         MCHBAR32(SMVREFC) |= (1 << 6);
2284
2285         MCHBAR32(MMARB0) &= ~(3 << 17);
2286         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2287
2288         MCHBAR32(MMARB1) &= ~(7 << 8);
2289         MCHBAR32(MMARB1) |= (3 << 8);
2290
2291         /* Adaptive Idle Timer Control */
2292         MCHBAR32(C0AIT) = 0x000006c4;
2293         MCHBAR32(C0AIT+4) = 0x871a066d;
2294
2295         MCHBAR32(C1AIT) = 0x000006c4;
2296         MCHBAR32(C1AIT+4) = 0x871a066d;
2297 }
2298
2299 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2300 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2301 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2302 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2303 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2304 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2305 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2306 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2307
2308 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2309 {
2310         u32 chan0 = 0, chan1 = 0;
2311         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2312
2313         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2314                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2315         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2316                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2317         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2318         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2319
2320         if (sdram_capabilities_enhanced_addressing_xor()) {
2321                 if (!sysinfo->interleaved) {
2322                         /* Single Channel & Dual Channel Assymetric */
2323                         if (chan0_populated) {
2324                                 if (chan0_dualsided) {
2325                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2326                                 } else {
2327                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2328                                 }
2329                         }
2330                         if (chan1_populated) {
2331                                 if (chan1_dualsided) {
2332                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2333                                 } else {
2334                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2335                                 }
2336                         }
2337                 } else {
2338                         /* Interleaved has always both channels populated */
2339                         if (chan0_dualsided) {
2340                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2341                         } else {
2342                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2343                         }
2344
2345                         if (chan1_dualsided) {
2346                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2347                         } else {
2348                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2349                         }
2350                 }
2351         } else {
2352                 if (!sysinfo->interleaved) {
2353                         /* Single Channel & Dual Channel Assymetric */
2354                         if (chan0_populated) {
2355                                 if (chan0_dualsided) {
2356                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2357                                 } else {
2358                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2359                                 }
2360                         }
2361                         if (chan1_populated) {
2362                                 if (chan1_dualsided) {
2363                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2364                                 } else {
2365                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2366                                 }
2367                         }
2368                 } else {
2369                         /* Interleaved has always both channels populated */
2370                         if (chan0_dualsided) {
2371                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2372                         } else {
2373                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2374                         }
2375
2376                         if (chan1_dualsided) {
2377                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2378                         } else {
2379                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2380                         }
2381                 }
2382         }
2383
2384         MCHBAR32(C0DRC1) &= 0x00ffffff;
2385         MCHBAR32(C0DRC1) |= chan0;
2386         MCHBAR32(C1DRC1) &= 0x00ffffff;
2387         MCHBAR32(C1DRC1) |= chan1;
2388 }
2389
2390 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2391 {
2392         u32 reg32;
2393
2394         /* Enable Channel XORing for Dual Channel Interleave */
2395         if (sysinfo->interleaved) {
2396
2397                 reg32 = MCHBAR32(DCC);
2398 #if CHANNEL_XOR_RANDOMIZATION
2399                 reg32 &= ~(1 << 10);
2400                 reg32 |= (1 << 9);
2401 #else
2402                 reg32 &= ~(1 << 9);
2403 #endif
2404                 MCHBAR32(DCC) = reg32;
2405         }
2406
2407         /* DRAM mode optimizations */
2408         sdram_enhanced_addressing_mode(sysinfo);
2409
2410         reg32 = MCHBAR32(FSBPMC3);
2411         reg32 &= ~(1 << 1);
2412         MCHBAR32(FSBPMC3) = reg32;
2413
2414         reg32 = MCHBAR32(SBTEST);
2415         reg32 &= ~(1 << 2);
2416         MCHBAR32(SBTEST) = reg32;
2417
2418         reg32 = MCHBAR32(SBOCC);
2419         reg32 &= 0xffbdb6ff;
2420         reg32 |= (0xbdb6 << 8) | (1 << 0);
2421         MCHBAR32(SBOCC) = reg32;
2422 }
2423
2424 static void sdram_power_management(struct sys_info *sysinfo)
2425 {
2426         u8 reg8;
2427         u16 reg16;
2428         u32 reg32;
2429         int integrated_graphics = 1;
2430         int i;
2431
2432         reg32 = MCHBAR32(C0DRT2);
2433         reg32 &= 0xffffff00;
2434         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2435         reg32 |= (1 << 5) | (1 << 4);
2436         MCHBAR32(C0DRT2) = reg32;
2437
2438         reg32 = MCHBAR32(C1DRT2);
2439         reg32 &= 0xffffff00;
2440         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2441         reg32 |= (1 << 5) | (1 << 4);
2442         MCHBAR32(C1DRT2) = reg32;
2443
2444         reg32 = MCHBAR32(C0DRC1);
2445
2446         reg32 |= (1 << 12) | (1 << 11);
2447         MCHBAR32(C0DRC1) = reg32;
2448
2449         reg32 = MCHBAR32(C1DRC1);
2450
2451         reg32 |= (1 << 12) | (1 << 11);
2452         MCHBAR32(C1DRC1) = reg32;
2453
2454         if (i945_silicon_revision()>1) {
2455                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2456                 u16 peg_bits = (1 << 5) | (1 << 0);
2457
2458                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2459         } else {
2460                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2461                 u16 peg_bits = (1 << 5) | (1 << 0);
2462
2463                 /* Rev 0 and 1 */
2464                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2465         }
2466
2467         reg16 = MCHBAR16(UPMC2);
2468         reg16 &= 0xfc00;
2469         reg16 |= 0x0100;
2470         MCHBAR16(UPMC2) = reg16;
2471
2472         MCHBAR32(UPMC3) = 0x000f06ff;
2473
2474         for (i=0; i<5; i++) {
2475                 MCHBAR32(UPMC3) &= ~(1 << 16);
2476                 MCHBAR32(UPMC3) |= (1 << 16);
2477         }
2478
2479         MCHBAR32(GIPMC1) = 0x8000000c;
2480
2481         reg16 = MCHBAR16(CPCTL);
2482         reg16 &= ~(7 << 11);
2483         if (i945_silicon_revision()>2) {
2484                 reg16 |= (6 << 11);
2485         } else {
2486                 reg16 |= (4 << 11);
2487         }
2488         MCHBAR16(CPCTL) = reg16;
2489
2490 #if 0
2491         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2492 #else
2493         if (i945_silicon_revision() != 0) {
2494 #endif
2495                 switch (sysinfo->fsb_frequency) {
2496                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2497                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2498                 }
2499         } else {
2500                 switch (sysinfo->fsb_frequency) {
2501                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2502                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2503                 }
2504         }
2505
2506         MCHBAR32(FSBPMC1) = 0x8000000c;
2507
2508         reg32 = MCHBAR32(C2C3TT);
2509         reg32 &= 0xffff0000;
2510         switch (sysinfo->fsb_frequency) {
2511         case 667: reg32 |= 0x0600; break;
2512         case 533: reg32 |= 0x0480; break;
2513         }
2514         MCHBAR32(C2C3TT) = reg32;
2515
2516         reg32 = MCHBAR32(C3C4TT);
2517         reg32 &= 0xffff0000;
2518         switch (sysinfo->fsb_frequency) {
2519         case 667: reg32 |= 0x0b80; break;
2520         case 533: reg32 |= 0x0980; break;
2521         }
2522         MCHBAR32(C3C4TT) = reg32;
2523
2524         if (i945_silicon_revision() == 0) {
2525                 MCHBAR32(ECO) &= ~(1 << 16);
2526         } else {
2527                 MCHBAR32(ECO) |= (1 << 16);
2528         }
2529
2530 #if 0
2531
2532         if (i945_silicon_revision() == 0) {
2533                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2534         } else {
2535                 MCHBAR32(FSBPMC3) |= (1 << 29);
2536         }
2537 #endif
2538         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2539
2540         MCHBAR32(FSBPMC3) |= (1 << 21);
2541
2542         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2543
2544         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2545
2546         reg32 = MCHBAR32(FSBPMC4);
2547         reg32 &= ~(3 << 24);
2548         reg32 |= ( 2 << 24);
2549         MCHBAR32(FSBPMC4) = reg32;
2550
2551         MCHBAR32(FSBPMC4) |= (1 << 21);
2552
2553         MCHBAR32(FSBPMC4) |= (1 << 5);
2554
2555         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2556                 /* stepping 0 and 1 or CPUID 6e8 */
2557                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2558         } else {
2559                 MCHBAR32(FSBPMC4) |= (1 << 4);
2560         }
2561
2562         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2563         reg8 |= (1 << 4);
2564         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2565
2566         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2567         reg8 |= (1 << 2);
2568         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2569
2570 #ifdef C2_SELF_REFRESH_DISABLE
2571
2572         if (integrated_graphics) {
2573                 printk_debug("C2 self-refresh with IGD\n");
2574                 MCHBAR16(MIPMC4) = 0x0468;
2575                 MCHBAR16(MIPMC5) = 0x046c;
2576                 MCHBAR16(MIPMC6) = 0x046c;
2577         } else {
2578                 MCHBAR16(MIPMC4) = 0x6468;
2579                 MCHBAR16(MIPMC5) = 0x646c;
2580                 MCHBAR16(MIPMC6) = 0x646c;
2581         }
2582 #else
2583         if (integrated_graphics) {
2584                 MCHBAR16(MIPMC4) = 0x04f8;
2585                 MCHBAR16(MIPMC5) = 0x04fc;
2586                 MCHBAR16(MIPMC6) = 0x04fc;
2587         } else {
2588                 MCHBAR16(MIPMC4) = 0x64f8;
2589                 MCHBAR16(MIPMC5) = 0x64fc;
2590                 MCHBAR16(MIPMC6) = 0x64fc;
2591         }
2592
2593 #endif
2594
2595         reg32 = MCHBAR32(PMCFG);
2596         reg32 &= ~(3 << 17);
2597         reg32 |= (2 << 17);
2598         MCHBAR32(PMCFG) = reg32;
2599
2600         MCHBAR32(PMCFG) |= (1 << 4);
2601
2602         reg32 = MCHBAR32(0xc30);
2603         reg32 &= 0xffffff00;
2604         reg32 |= 0x01;
2605         MCHBAR32(0xc30) = reg32;
2606
2607         MCHBAR32(0xb18) &= ~(1 << 21);
2608 }
2609
2610 static void sdram_thermal_management(void)
2611 {
2612
2613         MCHBAR8(TCO1) = 0x00;
2614         MCHBAR8(TCO0) = 0x00;
2615
2616         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2617          * 0x30/0x32.
2618          */
2619
2620 }
2621
2622 static void sdram_save_receive_enable(void)
2623 {
2624         int i;
2625         u32 reg32;
2626         u8 values[4];
2627
2628         /* The following values are stored to an unused CMOS
2629          * area and restored instead of recalculated in case
2630          * of an S3 resume.
2631          *
2632          * C0WL0REOST [7:0]             -> 8 bit
2633          * C1WL0REOST [7:0]             -> 8 bit
2634          * RCVENMT    [11:8] [3:0]      -> 8 bit
2635          * C0DRT1     [27:24]           -> 4 bit
2636          * C1DRT1     [27:24]           -> 4 bit
2637          */
2638
2639         values[0] = MCHBAR8(C0WL0REOST);
2640         values[1] = MCHBAR8(C1WL0REOST);
2641
2642         reg32 = MCHBAR32(RCVENMT);
2643         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2644
2645         reg32 = MCHBAR32(C0DRT1);
2646         values[3] = (reg32 >> 24) & 0x0f;
2647         reg32 = MCHBAR32(C1DRT1);
2648         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2649
2650         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2651          * so we grad bytes 128 - 131 to save the receive enable values
2652          */
2653
2654         for (i=0; i<4; i++)
2655                 cmos_write(values[i], 128 + i);
2656 }
2657
2658 static void sdram_recover_receive_enable(void)
2659 {
2660         int i;
2661         u32 reg32;
2662         u8 values[4];
2663
2664         for (i=0; i<4; i++)
2665                 values[i] = cmos_read(128 + i);
2666
2667         MCHBAR8(C0WL0REOST) = values[0];
2668         MCHBAR8(C1WL0REOST) = values[1];
2669
2670         reg32 = MCHBAR32(RCVENMT);
2671         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2672         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2673         MCHBAR32(RCVENMT) = reg32;
2674
2675         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2676         reg32 |= (u32)(values[3] & 0x0f) << 24;
2677         MCHBAR32(C0DRT1) = reg32;
2678
2679         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2680         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2681         MCHBAR32(C1DRT1) = reg32;
2682 }
2683
2684 #include "rcven.c"
2685
2686 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2687 {
2688         MCHBAR32(REPC) |= (1 << 0);
2689
2690         /* enable upper CMOS */
2691         RCBA32(0x3400) = (1 << 2);
2692
2693         /* Program Receive Enable Timings */
2694         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2695                 sdram_recover_receive_enable();
2696         } else {
2697                 receive_enable_adjust(sysinfo);
2698                 sdram_save_receive_enable();
2699         }
2700
2701         MCHBAR32(C0DRC1) |= (1 << 6);
2702         MCHBAR32(C1DRC1) |= (1 << 6);
2703         MCHBAR32(C0DRC1) &= ~(1 << 6);
2704         MCHBAR32(C1DRC1) &= ~(1 << 6);
2705
2706         MCHBAR32(MIPMC3) |= (0x0f << 0);
2707 }
2708
2709 /**
2710  * @brief Enable On-Die Termination for DDR2.
2711  *
2712  */
2713
2714 static void sdram_on_die_termination(struct sys_info *sysinfo)
2715 {
2716         static const u32 odt[] = {
2717                 0x00024911, 0xe0010000,
2718                 0x00049211, 0xe0020000,
2719                 0x0006db11, 0xe0030000,
2720         };
2721
2722         u32 reg32;
2723         int cas;
2724
2725         reg32 = MCHBAR32(ODTC);
2726         reg32 &= ~(3 << 16);
2727         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2728         MCHBAR32(ODTC) = reg32;
2729
2730         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2731                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2732                 printk_debug("one dimm per channel config.. \n");
2733
2734                 reg32 = MCHBAR32(C0ODT);
2735                 reg32 &= ~(7 << 28);
2736                 MCHBAR32(C0ODT) = reg32;
2737                 reg32 = MCHBAR32(C1ODT);
2738                 reg32 &= ~(7 << 28);
2739                 MCHBAR32(C1ODT) = reg32;
2740         }
2741
2742         cas = sysinfo->cas;
2743
2744         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2745         reg32 |= odt[(cas-3) * 2];
2746         MCHBAR32(C0ODT) = reg32;
2747
2748         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2749         reg32 |= odt[(cas-3) * 2];
2750         MCHBAR32(C1ODT) = reg32;
2751
2752         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2753         reg32 |= odt[((cas-3) * 2) + 1];
2754         MCHBAR32(C0ODT + 4) = reg32;
2755
2756         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2757         reg32 |= odt[((cas-3) * 2) + 1];
2758         MCHBAR32(C1ODT + 4) = reg32;
2759 }
2760
2761 /**
2762  * @brief Enable clocks to populated sockets
2763  */
2764
2765 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2766 {
2767         u8 clocks[2] = { 0, 0 };
2768
2769 #ifdef CHIPSET_I945GM
2770 #define CLOCKS_WIDTH 2
2771 #endif
2772 #ifdef CHIPSET_I945GC
2773 #define CLOCKS_WIDTH 3
2774 #endif
2775         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2776                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2777
2778         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2779                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2780
2781         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2782                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2783
2784         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2785                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2786
2787 #ifdef OVERRIDE_CLOCK_DISABLE
2788         /* Usually system firmware turns off system memory clock signals
2789          * to unused SO-DIMM slots to reduce EMI and power consumption.
2790          * However, the Kontron 986LCD-M does not like unused clock
2791          * signals to be disabled.
2792          * If other similar mainboard occur, it would make sense to make
2793          * this an entry in the sysinfo structure, and pre-initialize that
2794          * structure in the mainboard's romstage.c main() function.
2795          * For now an #ifdef will do.
2796          */
2797
2798         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2799         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2800 #endif
2801
2802         MCHBAR8(C0DCLKDIS) = clocks[0];
2803         MCHBAR8(C1DCLKDIS) = clocks[1];
2804 }
2805
2806 #define RTT_ODT_NONE    0
2807 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2808 #define RTT_ODT_75_OHM  (1 << 5)
2809 #define RTT_ODT_150_OHM (1 << 9)
2810
2811 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2812
2813 #define MRS_CAS_3       (3 << 7)
2814 #define MRS_CAS_4       (4 << 7)
2815 #define MRS_CAS_5       (5 << 7)
2816
2817 #define MRS_TWR_3       (2 << 12)
2818 #define MRS_TWR_4       (3 << 12)
2819 #define MRS_TWR_5       (4 << 12)
2820
2821 #define MRS_BT          (1 << 6)
2822
2823 #define MRS_BL4         (2 << 3)
2824 #define MRS_BL8         (3 << 3)
2825
2826 static void sdram_jedec_enable(struct sys_info *sysinfo)
2827 {
2828         int i, nonzero;
2829         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2830
2831         for (i = 0, nonzero = -1; i < 8; i++) {
2832                 if (sysinfo->banksize[i]  == 0) {
2833                         continue;
2834                 }
2835
2836                 printk_debug("jedec enable sequence: bank %d\n", i);
2837                 switch (i) {
2838                 case 0:
2839                         /* Start at address 0 */
2840                         bankaddr = 0;
2841                         break;
2842                 case 4:
2843                         if (sysinfo->interleaved) {
2844                                 bankaddr = 0x40;
2845                                 break;
2846                         }
2847                 default:
2848                         if (nonzero != -1) {
2849                                 printk_debug("bankaddr from bank size of rank %d\n", nonzero);
2850                                 bankaddr += sysinfo->banksize[nonzero] <<
2851                                         (sysinfo->interleaved ? 26 : 25);
2852                                 break;
2853                         }
2854                         /* No populated bank hit before. Start at address 0 */
2855                         bankaddr = 0;
2856                 }
2857
2858                 /* We have a bank with a non-zero size.. Remember it
2859                  * for the next offset we have to calculate
2860                  */
2861                 nonzero = i;
2862
2863                 /* Get CAS latency set up */
2864                 switch (sysinfo->cas) {
2865                 case 5: mrsaddr = MRS_CAS_5; break;
2866                 case 4: mrsaddr = MRS_CAS_4; break;
2867                 case 3: mrsaddr = MRS_CAS_3; break;
2868                 default: die("Jedec Error (CAS).\n");
2869                 }
2870
2871                 /* Get tWR set */
2872                 switch (sysinfo->twr) {
2873                 case 5: mrsaddr |= MRS_TWR_5; break;
2874                 case 4: mrsaddr |= MRS_TWR_4; break;
2875                 case 3: mrsaddr |= MRS_TWR_3; break;
2876                 default: die("Jedec Error (tWR).\n");
2877                 }
2878
2879                 /* Set "Burst Type" */
2880                 mrsaddr |= MRS_BT;
2881
2882                 /* Interleaved */
2883                 if (sysinfo->interleaved) {
2884                         mrsaddr = mrsaddr << 1;
2885                 }
2886
2887                 /* Only burst length 8 supported */
2888                 mrsaddr |= MRS_BL8;
2889
2890                 /* Apply NOP */
2891                 PRINTK_DEBUG("Apply NOP\n");
2892                 do_ram_command(RAM_COMMAND_NOP);
2893                 ram_read32(bankaddr);
2894
2895                 /* Precharge all banks */
2896                 PRINTK_DEBUG("All Banks Precharge\n");
2897                 do_ram_command(RAM_COMMAND_PRECHARGE);
2898                 ram_read32(bankaddr);
2899
2900                 /* Extended Mode Register Set (2) */
2901                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2902                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2903                 ram_read32(bankaddr);
2904
2905                 /* Extended Mode Register Set (3) */
2906                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2907                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2908                 ram_read32(bankaddr);
2909
2910                 /* Extended Mode Register Set */
2911                 PRINTK_DEBUG("Extended Mode Register Set\n");
2912                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2913                 tmpaddr = bankaddr;
2914                 if (!sdram_capabilities_dual_channel()) {
2915                         tmpaddr |= RTT_ODT_75_OHM;
2916                 } else if (sysinfo->interleaved) {
2917                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2918                 } else {
2919                         tmpaddr |= RTT_ODT_150_OHM;
2920                 }
2921                 ram_read32(tmpaddr);
2922
2923                 /* Mode Register Set: Reset DLLs */
2924                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2925                 do_ram_command(RAM_COMMAND_MRS);
2926                 tmpaddr = bankaddr;
2927                 tmpaddr |= mrsaddr;
2928                 /* Set DLL reset bit */
2929                 if (sysinfo->interleaved)
2930                         tmpaddr |= (1 << 12);
2931                 else
2932                         tmpaddr |= (1 << 11);
2933                 ram_read32(tmpaddr);
2934
2935                 /* Precharge all banks */
2936                 PRINTK_DEBUG("All Banks Precharge\n");
2937                 do_ram_command(RAM_COMMAND_PRECHARGE);
2938                 ram_read32(bankaddr);
2939
2940                 /* CAS before RAS Refresh */
2941                 PRINTK_DEBUG("CAS before RAS\n");
2942                 do_ram_command(RAM_COMMAND_CBR);
2943
2944                 /* CBR wants two READs */
2945                 ram_read32(bankaddr);
2946                 ram_read32(bankaddr);
2947
2948                 /* Mode Register Set: Enable DLLs */
2949                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2950                 do_ram_command(RAM_COMMAND_MRS);
2951
2952                 tmpaddr = bankaddr;
2953                 tmpaddr |= mrsaddr;
2954                 ram_read32(tmpaddr);
2955
2956                 /* Extended Mode Register Set */
2957                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2958                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2959
2960                 tmpaddr = bankaddr;
2961                 if (!sdram_capabilities_dual_channel()) {
2962
2963                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2964                 } else if (sysinfo->interleaved) {
2965                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2966                 } else {
2967                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2968                 }
2969                 ram_read32(tmpaddr);
2970
2971                 /* Extended Mode Register Set */
2972                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2973                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2974
2975                 tmpaddr = bankaddr;
2976                 if (!sdram_capabilities_dual_channel()) {
2977                         tmpaddr |= RTT_ODT_75_OHM;
2978                 } else if (sysinfo->interleaved) {
2979                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2980                 } else {
2981                         tmpaddr |= RTT_ODT_150_OHM;
2982                 }
2983                 ram_read32(tmpaddr);
2984         }
2985 }
2986
2987 static void sdram_init_complete(void)
2988 {
2989         PRINTK_DEBUG("Normal Operation\n");
2990         do_ram_command(RAM_COMMAND_NORMAL);
2991 }
2992
2993 static void sdram_setup_processor_side(void)
2994 {
2995         if (i945_silicon_revision() == 0)
2996                 MCHBAR32(FSBPMC3) |= (1 << 2);
2997
2998         MCHBAR8(0xb00) |= 1;
2999
3000         if (i945_silicon_revision() == 0)
3001                 MCHBAR32(SLPCTL) |= (1 << 8);
3002 }
3003
3004 /**
3005  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3006  */
3007 void sdram_initialize(int boot_path)
3008 {
3009         struct sys_info sysinfo;
3010         u8 reg8, cas_mask;
3011
3012         sdram_detect_errors();
3013
3014         printk_debug ("Setting up RAM controller.\n");
3015
3016         memset(&sysinfo, 0, sizeof(sysinfo));
3017
3018         sysinfo.boot_path = boot_path;
3019
3020         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3021         sdram_get_dram_configuration(&sysinfo);
3022
3023         /* Check whether we have stacked DIMMs */
3024         sdram_verify_package_type(&sysinfo);
3025
3026         /* Determine common CAS */
3027         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3028
3029         /* Choose Common Frequency */
3030         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3031
3032         /* Determine smallest common tRAS */
3033         sdram_detect_smallest_tRAS(&sysinfo);
3034
3035         /* Determine tRP */
3036         sdram_detect_smallest_tRP(&sysinfo);
3037
3038         /* Determine tRCD */
3039         sdram_detect_smallest_tRCD(&sysinfo);
3040
3041         /* Determine smallest refresh period */
3042         sdram_detect_smallest_refresh(&sysinfo);
3043
3044         /* Verify all DIMMs support burst length 8 */
3045         sdram_verify_burst_length(&sysinfo);
3046
3047         /* determine tWR */
3048         sdram_detect_smallest_tWR(&sysinfo);
3049
3050         /* Determine DIMM size parameters (rows, columns banks) */
3051         sdram_detect_dimm_size(&sysinfo);
3052
3053         /* determine tRFC */
3054         sdram_detect_smallest_tRFC(&sysinfo);
3055
3056         /* Program PLL settings */
3057         sdram_program_pll_settings(&sysinfo);
3058
3059         /* Program Graphics Frequency */
3060         sdram_program_graphics_frequency(&sysinfo);
3061
3062         /* Program System Memory Frequency */
3063         sdram_program_memory_frequency(&sysinfo);
3064
3065         /* Determine Mode of Operation (Interleaved etc) */
3066         sdram_set_channel_mode(&sysinfo);
3067
3068         /* Program Clock Crossing values */
3069         sdram_program_clock_crossing();
3070
3071         /* Disable fast dispatch */
3072         sdram_disable_fast_dispatch();
3073
3074         /* Enable WIODLL Power Down in ACPI states */
3075         MCHBAR32(C0DMC) |= (1 << 24);
3076         MCHBAR32(C1DMC) |= (1 << 24);
3077
3078         /* Program DRAM Row Boundary/Attribute Registers */
3079
3080         /* program row size DRB and set TOLUD */
3081         sdram_program_row_boundaries(&sysinfo);
3082
3083         /* program page size DRA */
3084         sdram_set_row_attributes(&sysinfo);
3085
3086         /* Program CxBNKARC */
3087         sdram_set_bank_architecture(&sysinfo);
3088
3089         /* Program DRAM Timing and Control registers based on SPD */
3090         sdram_set_timing_and_control(&sysinfo);
3091
3092         /* On-Die Termination Adjustment */
3093         sdram_on_die_termination(&sysinfo);
3094
3095         /* Pre Jedec Initialization */
3096         sdram_pre_jedec_initialization();
3097
3098         /* Perform System Memory IO Initialization */
3099         sdram_initialize_system_memory_io(&sysinfo);
3100
3101         /* Perform System Memory IO Buffer Enable */
3102         sdram_enable_system_memory_io(&sysinfo);
3103
3104         /* Enable System Memory Clocks */
3105         sdram_enable_memory_clocks(&sysinfo);
3106
3107         if (boot_path == BOOT_PATH_NORMAL) {
3108                 /* Jedec Initialization sequence */
3109                 sdram_jedec_enable(&sysinfo);
3110         }
3111
3112         /* Program Power Management Registers */
3113         sdram_power_management(&sysinfo);
3114
3115         /* Post Jedec Init */
3116         sdram_post_jedec_initialization(&sysinfo);
3117
3118         /* Program DRAM Throttling */
3119         sdram_thermal_management();
3120
3121         /* Normal Operations */
3122         sdram_init_complete();
3123
3124         /* Program Receive Enable Timings */
3125         sdram_program_receive_enable(&sysinfo);
3126
3127         /* Enable Periodic RCOMP */
3128         sdram_enable_rcomp();
3129
3130         /* Tell ICH7 that we're done */
3131         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3132         reg8 &= ~(1 << 7);
3133         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3134
3135         printk_debug("RAM initialization finished.\n");
3136
3137         sdram_setup_processor_side();
3138 }
3139
3140 unsigned long get_top_of_ram(void)
3141 {
3142         /* This will not work if TSEG is in place! */
3143         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3144
3145         return (unsigned long) tom;
3146 }
3147