src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <pc80/mc146818rtc.h>
  24 #include <spd.h>
  25 #include <string.h>
  26 #include <arch/romcc_io.h>
  27 #include "raminit.h"
  28 #include "i945.h"
  29
  30 /* Debugging macros. */
  31 #if CONFIG_DEBUG_RAM_SETUP
  32 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  33 #else
  34 #define PRINTK_DEBUG(x...)
  35 #endif
  36
  37 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  38
  39 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  40 #define RAM_COMMAND_NOP                 (0x1 << 16)
  41 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  42 #define RAM_COMMAND_MRS                 (0x3 << 16)
  43 #define RAM_COMMAND_EMRS                (0x4 << 16)
  44 #define RAM_COMMAND_CBR                 (0x6 << 16)
  45 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  46
  47 #define RAM_EMRS_1                      (0x0 << 21)
  48 #define RAM_EMRS_2                      (0x1 << 21)
  49 #define RAM_EMRS_3                      (0x2 << 21)
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 static __attribute__((noinline)) void do_ram_command(u32 command)
  57 {
  58         u32 reg32;
  59
  60         reg32 = MCHBAR32(DCC);
  61         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  62         reg32 |= command;
  63
  64         /* Also set Init Complete */
  65         if (command == RAM_COMMAND_NORMAL)
  66                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  67
  68         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  69
  70         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  71
  72         PRINTK_DEBUG("...done\n");
  73
  74         udelay(1);
  75 }
  76
  77 static void ram_read32(u32 offset)
  78 {
  79         PRINTK_DEBUG("   ram read: %08x\n", offset);
  80
  81         read32(offset);
  82 }
  83
  84 #if CONFIG_DEBUG_RAM_SETUP
  85 static void sdram_dump_mchbar_registers(void)
  86 {
  87         int i;
  88         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  89
  90         for (i=0; i<0xfff; i+=4) {
  91                 if (MCHBAR32(i) == 0)
  92                         continue;
  93                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  94         }
  95 }
  96 #endif
  97
  98 static int memclk(void)
  99 {
 100         int offset = 0;
 101 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 102         offset++;
 103 #endif
 104         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
 105         case 1: return 400;
 106         case 2: return 533;
 107         case 3: return 667;
 108         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 109         }
 110         return -1;
 111 }
 112
 113 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 114 static u16 fsbclk(void)
 115 {
 116         switch (MCHBAR32(CLKCFG) & 7) {
 117         case 0: return 400;
 118         case 1: return 533;
 119         case 3: return 667;
 120         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 121         }
 122         return 0xffff;
 123 }
 124 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 125 static u16 fsbclk(void)
 126 {
 127         switch (MCHBAR32(CLKCFG) & 7) {
 128         case 0: return 1066;
 129         case 1: return 533;
 130         case 2: return 800;
 131         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 132         }
 133         return 0xffff;
 134 }
 135 #endif
 136
 137 static int sdram_capabilities_max_supported_memory_frequency(void)
 138 {
 139         u32 reg32;
 140
 141 #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
 142         return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 143 #endif
 144
 145         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 146         reg32 &= (7 << 0);
 147
 148         switch (reg32) {
 149         case 4: return 400;
 150         case 3: return 533;
 151         case 2: return 667;
 152         }
 153         /* Newer revisions of this chipset rather support faster memory clocks,
 154          * so if it's a reserved value, return the fastest memory clock that we
 155          * know of and can handle
 156          */
 157         return 667;
 158 }
 159
 160 /**
 161  * @brief determine whether chipset is capable of dual channel interleaved mode
 162  *
 163  * @return 1 if interleaving is supported, 0 otherwise
 164  */
 165 static int sdram_capabilities_interleave(void)
 166 {
 167         u32 reg32;
 168
 169         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 170         reg32 >>= 25;
 171         reg32 &= 1;
 172
 173         return (!reg32);
 174 }
 175
 176 /**
 177  * @brief determine whether chipset is capable of two memory channels
 178  *
 179  * @return 1 if dual channel operation is supported, 0 otherwise
 180  */
 181 static int sdram_capabilities_dual_channel(void)
 182 {
 183         u32 reg32;
 184
 185         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 186         reg32 >>= 24;
 187         reg32 &= 1;
 188
 189         return (!reg32);
 190 }
 191
 192 static int sdram_capabilities_enhanced_addressing_xor(void)
 193 {
 194         u8 reg8;
 195
 196         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 197         reg8 &= (1 << 7);
 198
 199         return (!reg8);
 200 }
 201
 202 static int sdram_capabilities_two_dimms_per_channel(void)
 203 {
 204         u8 reg8;
 205
 206         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 207         reg8 &= (1 << 0);
 208
 209         return (reg8 != 0);
 210 }
 211
 212 // TODO check if we ever need this function
 213 #if 0
 214 static int sdram_capabilities_MEM4G_disable(void)
 215 {
 216         u8 reg8;
 217
 218         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 219         reg8 &= (1 << 0);
 220
 221         return (reg8 != 0);
 222 }
 223 #endif
 224
 225 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 226 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 227 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 228 #define GFX_FREQUENCY_CAP_ALL           0x00
 229
 230 static int sdram_capabilities_core_frequencies(void)
 231 {
 232         u8 reg8;
 233
 234         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 235         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 236         reg8 >>= 1;
 237
 238         return (reg8);
 239 }
 240
 241 static void sdram_detect_errors(struct sys_info *sysinfo)
 242 {
 243         u8 reg8;
 244         u8 do_reset = 0;
 245
 246         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 247
 248         if (reg8 & ((1<<7)|(1<<2))) {
 249                 if (reg8 & (1<<2)) {
 250                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 251                         /* Write back clears bit 2 */
 252                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 253                         do_reset = 1;
 254
 255                 }
 256
 257                 if (reg8 & (1<<7)) {
 258                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 259                         reg8 &= ~(1<<7);
 260                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 261                         do_reset = 1;
 262                 }
 263
 264                 /* Set SLP_S3# Assertion Stretch Enable */
 265                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 266                 reg8 |= (1 << 3);
 267                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 268
 269                 if (do_reset) {
 270                         printk(BIOS_DEBUG, "Reset required.\n");
 271                         outb(0x00, 0xcf9);
 272                         outb(0x0e, 0xcf9);
 273                         for (;;) asm("hlt"); /* Wait for reset! */
 274                 }
 275         }
 276
 277         /* Set DRAM initialization bit in ICH7 */
 278         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 279         reg8 |= (1<<7);
 280         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 281
 282         /* clear self refresh if not wake-up from suspend */
 283         if (sysinfo->boot_path != 2) {
 284                 MCHBAR8(0xf14) |= 3;
 285         } else {
 286                 /* Validate self refresh config */
 287                 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
 288                      (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
 289                     !(MCHBAR8(0xf14) & (1<<0))) {
 290                         do_reset = 1;
 291                 }
 292                 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
 293                      (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
 294                     !(MCHBAR8(0xf14) & (1<<1))) {
 295                         do_reset = 1;
 296                 }
 297         }
 298
 299         if (do_reset) {
 300                 printk(BIOS_DEBUG, "Reset required.\n");
 301                 outb(0x00, 0xcf9);
 302                 outb(0x0e, 0xcf9);
 303                 for (;;) asm("hlt"); /* Wait for reset! */
 304         }
 305 }
 306
 307 /**
 308  * @brief Get generic DIMM parameters.
 309  * @param sysinfo Central memory controller information structure
 310  *
 311  * This function gathers several pieces of information for each system DIMM:
 312  *  o DIMM width (x8 / x16)
 313  *  o DIMM sides (single sided / dual sided)
 314  *
 315  *  Also, some non-supported scenarios are detected.
 316  */
 317
 318 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 319 {
 320         u32 dimm_mask = 0;
 321         int i;
 322
 323         /**
 324          * i945 supports two DIMMs, in two configurations:
 325          *
 326          * - single channel with two dimms
 327          * - dual channel with one dimm per channel
 328          *
 329          * In practice dual channel mainboards have their spd at 0x50, 0x52
 330          * whereas single channel configurations have their spd at 0x50/x51
 331          *
 332          * The capability register knows a lot about the channel configuration
 333          * but for now we stick with the information we gather from the SPD
 334          * ROMs
 335          */
 336
 337         if (sdram_capabilities_dual_channel()) {
 338                 sysinfo->dual_channel = 1;
 339                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 340         } else {
 341                 sysinfo->dual_channel = 0;
 342                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 343         }
 344
 345         /**
 346          * Since we only support two DIMMs in total, there is a limited number
 347          * of combinations. This function returns the type of DIMMs.
 348          * return value:
 349          *   [0:7]  lower DIMM population
 350          *   [8-15] higher DIMM population
 351          *   [16]   dual channel?
 352          *
 353          * There are 5 different possible populations for a DIMM socket:
 354          * 1. x16 double sided (X16DS)
 355          * 2. x8 double sided  (X8DS)
 356          * 3. x16 single sided (X16SS)
 357          * 4. x8 double stacked (X8DDS)
 358          * 5. not populated (NC)
 359          *
 360          * For the return value we start counting at zero.
 361          *
 362          */
 363
 364         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 365                 u8 reg8, device = DIMM_SPD_BASE + i;
 366
 367                 /* Initialize the socket information with a sane value */
 368                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 369
 370                 /* Dual Channel not supported, but Channel 1? Bail out */
 371                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 372                         continue;
 373
 374                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 375                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 376                         continue;
 377
 378                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 379
 380                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 381                         printk(BIOS_DEBUG, "N/A\n");
 382                         continue;
 383                 }
 384
 385                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 386                 if (reg8 == ERROR_SCHEME_ECC)
 387                         die("Error: ECC memory not supported by this chipset\n");
 388
 389                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 390                 if (reg8 & MODULE_BUFFERED)
 391                         die("Error: Buffered memory not supported by this chipset\n");
 392                 if (reg8 & MODULE_REGISTERED)
 393                         die("Error: Registered memory not supported by this chipset\n");
 394
 395                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 396                 case 0x08:
 397                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 398                         case 1:
 399                                 printk(BIOS_DEBUG, "x8DDS\n");
 400                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 401                                 break;
 402                         case 0:
 403                                 printk(BIOS_DEBUG, "x8DS\n");
 404                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 405                                 break;
 406                         default:
 407                                 printk(BIOS_DEBUG, "Unsupported.\n");
 408                         }
 409                         break;
 410                 case 0x10:
 411                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 412                         case 1:
 413                                 printk(BIOS_DEBUG, "x16DS\n");
 414                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 415                                 break;
 416                         case 0:
 417                                 printk(BIOS_DEBUG, "x16SS\n");
 418                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 419                                 break;
 420                         default:
 421                                 printk(BIOS_DEBUG, "Unsupported.\n");
 422                         }
 423                         break;
 424                 default:
 425                         die("Unsupported DDR-II memory width.\n");
 426                 }
 427
 428                 dimm_mask |= (1 << i);
 429         }
 430
 431         if (!dimm_mask) {
 432                 die("No memory installed.\n");
 433         }
 434
 435         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 436                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 437         }
 438 }
 439
 440 /**
 441  * @brief determine if any DIMMs are stacked
 442  *
 443  * @param sysinfo central sysinfo data structure.
 444  */
 445 static void sdram_verify_package_type(struct sys_info * sysinfo)
 446 {
 447         int i;
 448
 449         /* Assume no stacked DIMMs are available until we find one */
 450         sysinfo->package = 0;
 451         for (i=0; i<2*DIMM_SOCKETS; i++) {
 452                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 453                         continue;
 454
 455                 /* Is the current DIMM a stacked DIMM? */
 456                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 457                         sysinfo->package = 1;
 458         }
 459 }
 460
 461 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 462 {
 463         int i;
 464         u8 cas_mask;
 465
 466         /* Setup CAS mask with all supported CAS Latencies */
 467         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 468                    SPD_CAS_LATENCY_DDR2_4 |
 469                    SPD_CAS_LATENCY_DDR2_5;
 470
 471         for (i=0; i<2*DIMM_SOCKETS; i++) {
 472                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 473                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 474         }
 475
 476         if(!cas_mask) {
 477                 die("No DDR-II modules with accepted CAS latencies found.\n");
 478         }
 479
 480         return cas_mask;
 481 }
 482
 483 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 484 {
 485         int i, j, idx;
 486         int lowest_common_cas = 0;
 487         int max_ram_speed = 0;
 488
 489         const u8 ddr2_speeds_table[] = {
 490                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 491                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 492                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 493         };
 494
 495         const u8 spd_lookup_table[] = {
 496                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 497                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 498                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 499         };
 500
 501         switch (sdram_capabilities_max_supported_memory_frequency()) {
 502         case 400: max_ram_speed = 0; break;
 503         case 533: max_ram_speed = 1; break;
 504         case 667: max_ram_speed = 2; break;
 505         }
 506
 507         if (fsbclk() == 533)
 508                 max_ram_speed = 1;
 509
 510         sysinfo->memory_frequency = 0;
 511         sysinfo->cas = 0;
 512
 513         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 514                 lowest_common_cas = 3;
 515         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 516                 lowest_common_cas = 4;
 517         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 518                 lowest_common_cas = 5;
 519         }
 520         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 521
 522         for (j = max_ram_speed; j>=0; j--) {
 523                 int freq_cas_mask = cas_mask;
 524
 525                 PRINTK_DEBUG("Probing Speed %d\n", j);
 526                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 527                         int current_cas_mask;
 528
 529                         PRINTK_DEBUG("  DIMM: %d\n", i);
 530                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 531                                 continue;
 532                         }
 533
 534                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 535
 536                         while (current_cas_mask) {
 537                                 int highest_supported_cas = 0, current_cas = 0;
 538                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 539                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 540                                         highest_supported_cas = 5;
 541                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 542                                         highest_supported_cas = 4;
 543                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 544                                         highest_supported_cas = 3;
 545                                 }
 546                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 547                                         current_cas = 3;
 548                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 549                                         current_cas = 4;
 550                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 551                                         current_cas = 5;
 552                                 }
 553
 554                                 idx = highest_supported_cas - current_cas;
 555                                 PRINTK_DEBUG("idx=%d, ", idx);
 556                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 557                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 558
 559                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 560                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 561                                         PRINTK_DEBUG(":    OK\n");
 562                                         break;
 563                                 }
 564
 565                                 PRINTK_DEBUG(":    Not fast enough!\n");
 566
 567                                 current_cas_mask &= ~(1 << (current_cas));
 568                         }
 569
 570                         freq_cas_mask &= current_cas_mask;
 571                         if (!current_cas_mask) {
 572                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 573                                 break;
 574                         }
 575                 }
 576                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 577                 if (freq_cas_mask) {
 578                         switch (j) {
 579                         case 0: sysinfo->memory_frequency = 400; break;
 580                         case 1: sysinfo->memory_frequency = 533; break;
 581                         case 2: sysinfo->memory_frequency = 667; break;
 582                         }
 583                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 584                                 sysinfo->cas = 3;
 585                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 586                                 sysinfo->cas = 4;
 587                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 588                                 sysinfo->cas = 5;
 589                         }
 590                         break;
 591                 }
 592         }
 593
 594         if (sysinfo->memory_frequency && sysinfo->cas) {
 595                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 596                                 sysinfo->memory_frequency, sysinfo->cas);
 597         } else {
 598                 die("Could not find common memory frequency and CAS\n");
 599         }
 600 }
 601
 602 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 603 {
 604         int i;
 605         int tRAS_time;
 606         int tRAS_cycles;
 607         int freq_multiplier = 0;
 608
 609         switch (sysinfo->memory_frequency) {
 610         case 400: freq_multiplier = 0x14; break; /* 5ns */
 611         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 612         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 613         }
 614
 615         tRAS_cycles = 4; /* 4 clocks minimum */
 616         tRAS_time = tRAS_cycles * freq_multiplier;
 617
 618         for (i=0; i<2*DIMM_SOCKETS; i++) {
 619                 u8 reg8;
 620
 621                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 622                         continue;
 623
 624                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 625                 if (!reg8) {
 626                         die("Invalid tRAS value.\n");
 627                 }
 628
 629                 while ((tRAS_time >> 2) < reg8) {
 630                         tRAS_time += freq_multiplier;
 631                         tRAS_cycles++;
 632                 }
 633         }
 634         if(tRAS_cycles > 0x18) {
 635                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 636         }
 637
 638         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 639         sysinfo->tras = tRAS_cycles;
 640 }
 641
 642 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 643 {
 644         int i;
 645         int tRP_time;
 646         int tRP_cycles;
 647         int freq_multiplier = 0;
 648
 649         switch (sysinfo->memory_frequency) {
 650         case 400: freq_multiplier = 0x14; break; /* 5ns */
 651         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 652         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 653         }
 654
 655         tRP_cycles = 2; /* 2 clocks minimum */
 656         tRP_time = tRP_cycles * freq_multiplier;
 657
 658         for (i=0; i<2*DIMM_SOCKETS; i++) {
 659                 u8 reg8;
 660
 661                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 662                         continue;
 663
 664                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 665                 if (!reg8) {
 666                         die("Invalid tRP value.\n");
 667                 }
 668
 669                 while (tRP_time < reg8) {
 670                         tRP_time += freq_multiplier;
 671                         tRP_cycles++;
 672                 }
 673         }
 674
 675         if(tRP_cycles > 6) {
 676                 die("DDR-II Module does not support this frequency (tRP error)\n");
 677         }
 678
 679         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 680         sysinfo->trp = tRP_cycles;
 681 }
 682
 683 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 684 {
 685         int i;
 686         int tRCD_time;
 687         int tRCD_cycles;
 688         int freq_multiplier = 0;
 689
 690         switch (sysinfo->memory_frequency) {
 691         case 400: freq_multiplier = 0x14; break; /* 5ns */
 692         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 693         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 694         }
 695
 696         tRCD_cycles = 2; /* 2 clocks minimum */
 697         tRCD_time = tRCD_cycles * freq_multiplier;
 698
 699         for (i=0; i<2*DIMM_SOCKETS; i++) {
 700                 u8 reg8;
 701
 702                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 703                         continue;
 704
 705                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 706                 if (!reg8) {
 707                         die("Invalid tRCD value.\n");
 708                 }
 709
 710                 while (tRCD_time < reg8) {
 711                         tRCD_time += freq_multiplier;
 712                         tRCD_cycles++;
 713                 }
 714         }
 715         if(tRCD_cycles > 6) {
 716                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 717         }
 718
 719         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 720         sysinfo->trcd = tRCD_cycles;
 721 }
 722
 723 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 724 {
 725         int i;
 726         int tWR_time;
 727         int tWR_cycles;
 728         int freq_multiplier = 0;
 729
 730         switch (sysinfo->memory_frequency) {
 731         case 400: freq_multiplier = 0x14; break; /* 5ns */
 732         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 733         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 734         }
 735
 736         tWR_cycles = 2; /* 2 clocks minimum */
 737         tWR_time = tWR_cycles * freq_multiplier;
 738
 739         for (i=0; i<2*DIMM_SOCKETS; i++) {
 740                 u8 reg8;
 741
 742                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 743                         continue;
 744
 745                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 746                 if (!reg8) {
 747                         die("Invalid tWR value.\n");
 748                 }
 749
 750                 while (tWR_time < reg8) {
 751                         tWR_time += freq_multiplier;
 752                         tWR_cycles++;
 753                 }
 754         }
 755         if(tWR_cycles > 5) {
 756                 die("DDR-II Module does not support this frequency (tWR error)\n");
 757         }
 758
 759         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 760         sysinfo->twr = tWR_cycles;
 761 }
 762
 763 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 764 {
 765         int i, index = 0;
 766
 767         const u8 tRFC_cycles[] = {
 768              /* 75 105 127.5 */
 769                 15, 21, 26,     /* DDR2-400 */
 770                 20, 28, 34,     /* DDR2-533 */
 771                 25, 35, 43      /* DDR2-667 */
 772         };
 773
 774         for (i=0; i<2*DIMM_SOCKETS; i++) {
 775                 u8 reg8;
 776
 777                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 778                         continue;
 779
 780                 reg8 = sysinfo->banksize[i*2];
 781                 switch (reg8) {
 782                 case 0x04: reg8 = 0; break;
 783                 case 0x08: reg8 = 1; break;
 784                 case 0x10: reg8 = 2; break;
 785                 case 0x20: reg8 = 3; break;
 786                 }
 787
 788                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 789                         reg8++;
 790
 791                 if (reg8 > 3) {
 792                         /* Can this happen? Go back to 127.5ns just to be sure
 793                          * we don't run out of the array. This may be wrong
 794                          */
 795                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 796                         reg8 = 3;
 797                 }
 798
 799                 if (reg8 > index)
 800                         index = reg8;
 801
 802         }
 803         index--;
 804         switch (sysinfo->memory_frequency) {
 805         case 667: index += 3; /* Fallthrough */
 806         case 533: index += 3; /* Fallthrough */
 807         case 400: break;
 808         }
 809
 810         sysinfo->trfc = tRFC_cycles[index];
 811         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 812 }
 813
 814 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 815 {
 816         int i;
 817
 818         sysinfo->refresh = 0;
 819
 820         for (i=0; i<2*DIMM_SOCKETS; i++) {
 821                 int refresh;
 822
 823                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 824                         continue;
 825
 826                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 827
 828                 /* 15.6us */
 829                 if (!refresh)
 830                         continue;
 831
 832                 /* Refresh is slower than 15.6us, use 15.6us */
 833                 if (refresh > 2)
 834                         continue;
 835
 836                 if (refresh == 2) {
 837                         sysinfo->refresh = 1;
 838                         break;
 839                 }
 840
 841                 die("DDR-II module has unsupported refresh value\n");
 842         }
 843         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 844 }
 845
 846 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 847 {
 848         int i;
 849
 850         for (i=0; i<2*DIMM_SOCKETS; i++) {
 851                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 852                         continue;
 853
 854                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 855                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 856         }
 857 }
 858
 859 static void sdram_program_dram_width(struct sys_info * sysinfo)
 860 {
 861         u16 c0dramw=0, c1dramw=0;
 862         int idx;
 863
 864         if (sysinfo->dual_channel)
 865                 idx = 2;
 866         else
 867                 idx = 1;
 868
 869         switch (sysinfo->dimm[0]) {
 870         case 0: c0dramw = 0x0000; break; /* x16DS */
 871         case 1: c0dramw = 0x0001; break; /* x8DS */
 872         case 2: c0dramw = 0x0000; break; /* x16SS */
 873         case 3: c0dramw = 0x0005; break; /* x8DDS */
 874         case 4: c0dramw = 0x0000; break; /* NC */
 875         }
 876
 877         switch (sysinfo->dimm[idx]) {
 878         case 0: c1dramw = 0x0000; break; /* x16DS */
 879         case 1: c1dramw = 0x0010; break; /* x8DS */
 880         case 2: c1dramw = 0x0000; break; /* x16SS */
 881         case 3: c1dramw = 0x0050; break; /* x8DDS */
 882         case 4: c1dramw = 0x0000; break; /* NC */
 883         }
 884
 885         if ( !sdram_capabilities_dual_channel() ) {
 886                 /* Single Channel */
 887                 c0dramw |= c1dramw;
 888                 c1dramw = 0;
 889         }
 890
 891         MCHBAR16(C0DRAMW) = c0dramw;
 892         MCHBAR16(C1DRAMW) = c1dramw;
 893 }
 894
 895 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 896 {
 897         int i;
 898
 899         for (i=0; i<16; i++)
 900                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 901 }
 902
 903 static const u32 dq2030[] = {
 904         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 905         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 906         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 907         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 908 };
 909
 910 static const u32 dq2330[] = {
 911         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 912         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 913         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 914         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 915 };
 916
 917 static const u32 cmd2710[] = {
 918         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 919         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 920         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 921         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 922 };
 923
 924 static const u32 cmd3210[] = {
 925         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 926         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 927         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 928         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 929 };
 930
 931 static const u32 clk2030[] = {
 932         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 933         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 934         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 935         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 936 };
 937
 938 static const u32 ctl3215[] = {
 939         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 940         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 941         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 942         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 943 };
 944
 945 static const u32 ctl3220[] = {
 946         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 947         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 948         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 949         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 950 };
 951
 952 static const u32 nc[] = {
 953         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 954         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 955         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 956         0x00000000, 0x00000000, 0x00000000, 0x00000000
 957 };
 958
 959 enum {
 960         DQ2030,
 961         DQ2330,
 962         CMD2710,
 963         CMD3210,
 964         CLK2030,
 965         CTL3215,
 966         CTL3220,
 967         NC,
 968 };
 969
 970 static const u8 dual_channel_slew_group_lookup[] = {
 971         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 972         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 973         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 974         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 975         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 976
 977         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 978         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 979         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 980         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 981         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 982
 983         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 984         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 985         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 986         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 987         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 988
 989         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 990         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 991         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 992         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 993         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 994
 995         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 996         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 997         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 998         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 999 };
1000
1001 static const u8 single_channel_slew_group_lookup[] = {
1002         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1003         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1004         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1005         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1006         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1007
1008         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1009         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1010         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1011         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1012         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1013
1014         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1015         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1016         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1017         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1018         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1019
1020         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1021         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1022         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1023         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1024         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1025
1026         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1027         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1028         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1029         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
1030 };
1031
1032 static const u32 *slew_group_lookup(int dual_channel, int index)
1033 {
1034         const u8 *slew_group;
1035         /* Dual Channel needs different tables. */
1036         if (dual_channel)
1037                 slew_group   = dual_channel_slew_group_lookup;
1038         else
1039                 slew_group   = single_channel_slew_group_lookup;
1040
1041         switch (slew_group[index]) {
1042         case DQ2030:    return dq2030;
1043         case DQ2330:    return dq2330;
1044         case CMD2710:   return cmd2710;
1045         case CMD3210:   return cmd3210;
1046         case CLK2030:   return clk2030;
1047         case CTL3215:   return ctl3215;
1048         case CTL3220:   return ctl3220;
1049         case NC:        return nc;
1050         }
1051
1052         return nc;
1053 }
1054
1055 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
1056 /* Strength multiplier tables */
1057 static const u8 dual_channel_strength_multiplier[] = {
1058         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1059         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1060         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1061         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1062         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1063         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1064         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1065         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1066         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1067         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1068         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1069         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1070         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1071         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1072         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1073         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1074         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1075         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1076         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1077         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1078         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1079         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1080         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1081         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1082 };
1083
1084 static const u8 single_channel_strength_multiplier[] = {
1085         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1086         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1087         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1088         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1089         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1090         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1091         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1092         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1093         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1094         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1095         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1096         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1097         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1098         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1099         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1100         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1101         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1102         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1103         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1104         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1105         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1106         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1107         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1108         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1109 };
1110 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
1111 static const u8 dual_channel_strength_multiplier[] = {
1112         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1113         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1114         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1115         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1116         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1117         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1118         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1119         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1120         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1121         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1122         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1123         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1124         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1125         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1126         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1127         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1128         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1129         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1130         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1131         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1132         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1133         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1134         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1135         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1136 };
1137
1138 static const u8 single_channel_strength_multiplier[] = {
1139         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1141         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1142         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1143         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1144         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1145         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1146         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1147         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1148         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1149         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1151         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1152         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1153         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1154         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1155         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1156         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1157         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1158         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1159         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1160         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1161         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1162         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1163 };
1164 #endif
1165
1166 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1167 {
1168         const u8 * strength_multiplier;
1169         int idx, dual_channel;
1170
1171         /* Set Strength Multipliers */
1172
1173         /* Dual Channel needs different tables. */
1174         if (sdram_capabilities_dual_channel()) {
1175                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1176                 strength_multiplier = dual_channel_strength_multiplier;
1177                 dual_channel = 1;
1178                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1179         } else {
1180                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1181                 strength_multiplier = single_channel_strength_multiplier;
1182                 dual_channel = 0;
1183                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1184         }
1185
1186         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1187
1188         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1189         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1190         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1191         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1192         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1193         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1194         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1195         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1196
1197         /* Channel 0 */
1198         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1199         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1200         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1201
1202                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1203         } else {
1204                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1205         }
1206         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1207         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1208         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1209
1210         /* Channel 1 */
1211         if (sysinfo->dual_channel) {
1212                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1213                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1214         } else {
1215                 sdram_write_slew_rates(G7SRPUT, nc);
1216                 sdram_write_slew_rates(G8SRPUT, nc);
1217         }
1218 }
1219
1220 static void sdram_enable_rcomp(void)
1221 {
1222         u32 reg32;
1223         /* Enable Global Periodic RCOMP */
1224         udelay(300);
1225         reg32 = MCHBAR32(GBRCOMPCTL);
1226         reg32 &= ~(1 << 23);
1227         MCHBAR32(GBRCOMPCTL) = reg32;
1228 }
1229
1230 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1231 {
1232         u32 chan0dll = 0, chan1dll = 0;
1233         int i;
1234
1235         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1236
1237         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1238         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1239
1240         /* We drive both channels with the same speed */
1241         switch (sysinfo->memory_frequency) {
1242         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1243         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1244         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1245         }
1246
1247         for (i=0; i < 4; i++) {
1248                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1249                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1250                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1251                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1252         }
1253 }
1254
1255 static void sdram_force_rcomp(void)
1256 {
1257         u32 reg32;
1258         u8 reg8;
1259
1260         reg32 = MCHBAR32(ODTC);
1261         reg32 |= (1 << 28);
1262         MCHBAR32(ODTC) = reg32;
1263
1264         reg32 = MCHBAR32(SMSRCTL);
1265         reg32 |= (1 << 0);
1266         MCHBAR32(SMSRCTL) = reg32;
1267
1268         /* Start initial RCOMP */
1269         reg32 = MCHBAR32(GBRCOMPCTL);
1270         reg32 |= (1 << 8);
1271         MCHBAR32(GBRCOMPCTL) = reg32;
1272
1273         reg8 = i945_silicon_revision();
1274         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1275
1276                 reg32 = MCHBAR32(GBRCOMPCTL);
1277                 reg32 |= (3 << 5);
1278                 MCHBAR32(GBRCOMPCTL) = reg32;
1279         }
1280 }
1281
1282 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1283 {
1284         u8 reg8;
1285         u32 reg32;
1286
1287         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1288         /* Enable Data Half Clock Pushout */
1289         reg8 = MCHBAR8(C0HCTC);
1290         reg8 &= ~0x1f;
1291         reg8 |= ( 1 << 0);
1292         MCHBAR8(C0HCTC) = reg8;
1293
1294         reg8 = MCHBAR8(C1HCTC);
1295         reg8 &= ~0x1f;
1296         reg8 |= ( 1 << 0);
1297         MCHBAR8(C1HCTC) = reg8;
1298
1299         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1300         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1301
1302         MCHBAR8(C0WDLLCMC) = 0;
1303         MCHBAR8(C1WDLLCMC) = 0;
1304
1305         /* Program RCOMP Settings */
1306         sdram_program_dram_width(sysinfo);
1307
1308         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1309
1310         /* Indicate that RCOMP programming is done */
1311         reg32 = MCHBAR32(GBRCOMPCTL);
1312         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1313         reg32 |= (3 << 27) | (3 << 0);
1314         MCHBAR32(GBRCOMPCTL) = reg32;
1315
1316         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1317
1318         /* Program DLL Timings */
1319         sdram_program_dll_timings(sysinfo);
1320
1321         /* Force RCOMP cycle */
1322         sdram_force_rcomp();
1323 }
1324
1325 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1326 {
1327         u32 reg32;
1328
1329         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1330
1331         reg32 = MCHBAR32(RCVENMT);
1332         reg32 &= ~(0x3f << 6);
1333         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1334
1335         reg32 |= (1 << 11) | (1 << 9);
1336         MCHBAR32(RCVENMT) = reg32;
1337
1338         reg32 = MCHBAR32(DRTST);
1339         reg32 |= (1 << 3) | (1 << 2);
1340         MCHBAR32(DRTST) = reg32;
1341
1342         reg32 = MCHBAR32(DRTST);
1343         reg32 |= (1 << 6) | (1 << 4);
1344         MCHBAR32(DRTST) = reg32;
1345
1346         asm volatile ("nop; nop;" ::: "memory");
1347
1348         reg32 = MCHBAR32(DRTST);
1349
1350         /* Is channel 0 populated? */
1351         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1352                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1353                 reg32 |= (1 << 7) | (1 << 5);
1354         else
1355                 reg32 |= (1 << 31);
1356
1357         /* Is channel 1 populated? */
1358         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1359                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1360                 reg32 |= (1 << 9) | (1 << 8);
1361         else
1362                 reg32 |= (1 << 30);
1363
1364         MCHBAR32(DRTST) = reg32;
1365
1366         /* Activate DRAM Channel IO Buffers */
1367         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1368                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1369                 reg32 = MCHBAR32(C0DRC1);
1370                 reg32 |= (1 << 8);
1371                 MCHBAR32(C0DRC1) = reg32;
1372         }
1373         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1374                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1375                 reg32 = MCHBAR32(C1DRC1);
1376                 reg32 |= (1 << 8);
1377                 MCHBAR32(C1DRC1) = reg32;
1378         }
1379 }
1380
1381 struct dimm_size {
1382         unsigned long side1;
1383         unsigned long side2;
1384 };
1385
1386 static struct dimm_size sdram_get_dimm_size(u16 device)
1387 {
1388         /* Calculate the log base 2 size of a DIMM in bits */
1389         struct dimm_size sz;
1390         int value, low, rows, columns;
1391
1392         sz.side1 = 0;
1393         sz.side2 = 0;
1394
1395         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1396         if (rows < 0) goto hw_err;
1397         if ((rows & 0xf) == 0) goto val_err;
1398         sz.side1 += rows & 0xf;
1399
1400         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1401         if (columns < 0) goto hw_err;
1402         if ((columns & 0xf) == 0) goto val_err;
1403         sz.side1 += columns & 0xf;
1404
1405         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1406         if (value < 0) goto hw_err;
1407         if ((value & 0xff) == 0) goto val_err;
1408         sz.side1 += log2(value & 0xff);
1409
1410         /* Get the module data width and convert it to a power of two */
1411         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1412         if (value < 0) goto hw_err;
1413         value &= 0xff;
1414         value <<= 8;
1415
1416         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1417         if (low < 0) goto hw_err;
1418         value = value | (low & 0xff);
1419         if ((value != 72) && (value != 64)) goto val_err;
1420         sz.side1 += log2(value);
1421
1422         /* side 2 */
1423         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1424
1425         if (value < 0) goto hw_err;
1426         value &= 7;
1427         value++;
1428         if (value == 1) goto out;
1429         if (value != 2) goto val_err;
1430
1431         /* Start with the symmetrical case */
1432         sz.side2 = sz.side1;
1433
1434         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1435
1436         /* Don't die here, I have not come across any of these to test what
1437          * actually happens.
1438          */
1439         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1440
1441         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1442         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1443
1444         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1445         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1446
1447         goto out;
1448
1449  val_err:
1450         die("Bad SPD value\n");
1451  hw_err:
1452         /* If a hardware error occurs the spd rom probably does not exist.
1453          * In this case report that there is no memory
1454          */
1455         sz.side1 = 0;
1456         sz.side2 = 0;
1457  out:
1458         return sz;
1459 }
1460
1461 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1462 {
1463         int i;
1464
1465         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1466                 struct dimm_size sz;
1467
1468                 sysinfo->banksize[i * 2] = 0;
1469                 sysinfo->banksize[(i * 2) + 1] = 0;
1470
1471                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1472                         continue;
1473
1474                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1475
1476                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1477
1478                 if (sz.side1 < 30)
1479                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1480
1481                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1482
1483                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1484
1485                 if (!sz.side2)
1486                         continue;
1487
1488                 /* If there is a second side, it has to have at least 128M, too */
1489                 if (sz.side2 < 30)
1490                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1491
1492                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1493
1494                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1495         }
1496 }
1497
1498 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1499 {
1500         int i;
1501         int cum0, cum1, tolud, tom;
1502
1503         printk(BIOS_DEBUG, "Setting RAM size... \n");
1504
1505         cum0 = 0;
1506         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1507                 cum0 += sysinfo->banksize[i];
1508                 MCHBAR8(C0DRB0+i) = cum0;
1509         }
1510
1511         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1512         cum1 = cum0;
1513
1514         /* Exception: Interleaved starts from the beginning */
1515         if (sysinfo->interleaved)
1516                 cum1 = 0;
1517
1518 #if 0
1519         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1520         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1521                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1522                 cum1 = 0;
1523 #endif
1524
1525         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1526                 cum1 += sysinfo->banksize[i + 4];
1527                 MCHBAR8(C1DRB0+i) = cum1;
1528         }
1529
1530         /* Set TOLUD Top Of Low Usable DRAM */
1531         if (sysinfo->interleaved)
1532                 tolud = (cum0 + cum1) << 1;
1533         else
1534                 tolud = (cum1 ? cum1 : cum0)  << 1;
1535
1536         /* The TOM register has a different format */
1537         tom = tolud >> 3;
1538
1539         /* Limit the value of TOLUD to leave some space for PCI memory. */
1540         if (tolud > 0xd0)
1541                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1542
1543         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1544
1545         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1546         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1547         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1548
1549         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1550
1551         return 0;
1552 }
1553
1554 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1555 {
1556         int i, value;
1557         u16 dra0=0, dra1=0, dra = 0;
1558
1559         printk(BIOS_DEBUG, "Setting row attributes... \n");
1560         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1561                 u16 device;
1562                 u8 columnsrows;
1563
1564                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1565                         continue;
1566                 }
1567
1568                 device = DIMM_SPD_BASE + i;
1569
1570                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1571                 columnsrows = (value & 0x0f);
1572
1573                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1574                 columnsrows |= (value & 0xf) << 4;
1575
1576                 switch (columnsrows) {
1577                 case 0x9d: dra = 2; break;
1578                 case 0xad: dra = 3; break;
1579                 case 0xbd: dra = 4; break;
1580                 case 0xae: dra = 3; break;
1581                 case 0xbe: dra = 4; break;
1582                 default: die("Unsupported Rows/Columns. (DRA)");
1583                 }
1584
1585                 /* Double Sided DIMMs? */
1586                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1587                         dra = (dra << 4) | dra;
1588                 }
1589
1590                 if (i < DIMM_SOCKETS)
1591                         dra0 |= (dra << (i*8));
1592                 else
1593                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1594         }
1595
1596         MCHBAR16(C0DRA0) = dra0;
1597         MCHBAR16(C1DRA0) = dra1;
1598
1599         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1600         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1601
1602         return 0;
1603 }
1604
1605 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1606 {
1607         u32 off32;
1608         int i;
1609
1610         MCHBAR16(C1BNKARC) &= 0xff00;
1611         MCHBAR16(C0BNKARC) &= 0xff00;
1612
1613         off32 = C0BNKARC;
1614         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1615                 /* Switch to second channel */
1616                 if (i == DIMM_SOCKETS)
1617                         off32 = C1BNKARC;
1618
1619                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1620                         continue;
1621
1622                 if (sysinfo->banks[i] != 8)
1623                         continue;
1624
1625                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1626
1627                 if (i & 1)
1628                         MCHBAR16(off32) |= 0x50;
1629                 else
1630                         MCHBAR16(off32) |= 0x05;
1631         }
1632 }
1633
1634 #define REFRESH_7_8US   1
1635 #define REFRESH_15_6US  0
1636 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1637 {
1638         u32 reg32;
1639
1640         if (sysinfo->refresh == REFRESH_7_8US) {
1641                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1642         } else {
1643                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1644         }
1645
1646         MCHBAR32(C0DRC0) &= ~(7 << 8);
1647         MCHBAR32(C0DRC0) |= reg32;
1648
1649         MCHBAR32(C1DRC0) &= ~(7 << 8);
1650         MCHBAR32(C1DRC0) |= reg32;
1651 }
1652
1653 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1654 {
1655         u32 reg32;
1656         int i;
1657
1658         reg32 = MCHBAR32(C0DRC1);
1659
1660         for (i=0; i < 4; i++) {
1661                 if (sysinfo->banksize[i] == 0) {
1662                         reg32 |= (1 << (16 + i));
1663                 }
1664         }
1665
1666         reg32 |= (1 << 12);
1667
1668         reg32 |= (1 << 11);
1669         MCHBAR32(C0DRC1) = reg32;
1670
1671         /* Do we have to do this if we're in Single Channel Mode?  */
1672         reg32 = MCHBAR32(C1DRC1);
1673
1674         for (i=4; i < 8; i++) {
1675                 if (sysinfo->banksize[i] == 0) {
1676                         reg32 |= (1 << (12 + i));
1677                 }
1678         }
1679
1680         reg32 |= (1 << 12);
1681
1682         reg32 |= (1 << 11);
1683         MCHBAR32(C1DRC1) = reg32;
1684 }
1685
1686 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1687 {
1688         u32 reg32;
1689         int i;
1690
1691         reg32 = MCHBAR32(C0DRC2);
1692
1693         for (i=0; i < 4; i++) {
1694                 if (sysinfo->banksize[i] == 0) {
1695                         reg32 |= (1 << (24 + i));
1696                 }
1697         }
1698         MCHBAR32(C0DRC2) = reg32;
1699
1700         reg32 = MCHBAR32(C1DRC2);
1701
1702         for (i=4; i < 8; i++) {
1703                 if (sysinfo->banksize[i] == 0) {
1704                         reg32 |= (1 << (20 + i));
1705                 }
1706         }
1707         MCHBAR32(C1DRC2) = reg32;
1708 }
1709
1710 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1711 {
1712         u32 reg32, off32;
1713         u32 tWTR;
1714         u32 temp_drt;
1715         int i, page_size;
1716
1717         static const u8 const drt0_table[] = {
1718           /* CL 3, 4, 5 */
1719                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1720                 4, 5, 6,        /* FSB667, DDR533/400 */
1721                 4, 5, 6,        /* FSB667, DDR667 */
1722         };
1723
1724         static const u8 const cas_table[] = {
1725                 2, 1, 0, 3
1726         };
1727
1728         reg32 = MCHBAR32(C0DRC0);
1729         reg32 |= (1 << 2);      /* Burst Length 8 */
1730         reg32 &= ~( (1 << 13) | (1 << 12) );
1731         MCHBAR32(C0DRC0) = reg32;
1732
1733         reg32 = MCHBAR32(C1DRC0);
1734         reg32 |= (1 << 2);      /* Burst Length 8 */
1735         reg32 &= ~( (1 << 13) | (1 << 12) );
1736         MCHBAR32(C1DRC0) = reg32;
1737
1738         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1739                         SYSINFO_DIMM_NOT_POPULATED) {
1740                 reg32 = MCHBAR32(C0DRC0);
1741                 reg32 |= (1 << 15);
1742                 MCHBAR32(C0DRC0) = reg32;
1743         }
1744
1745         sdram_program_refresh_rate(sysinfo);
1746
1747         sdram_program_cke_tristate(sysinfo);
1748
1749         sdram_program_odt_tristate(sysinfo);
1750
1751         /* Calculate DRT0 */
1752
1753         temp_drt = 0;
1754
1755         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1756         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1757         temp_drt |= (reg32 << 28);
1758
1759         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1760         reg32 += sysinfo->trp;
1761         temp_drt |= (reg32 << 4);
1762
1763         if (sysinfo->memory_frequency == 667) {
1764                 tWTR = 3; /* 667MHz */
1765         } else {
1766                 tWTR = 2; /* 400 and 533 */
1767         }
1768
1769         /* B2B Write to Read Command Spacing */
1770         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1771         temp_drt |= (reg32 << 24);
1772
1773         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1774         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1775
1776         /* Program Write Auto Precharge to Activate */
1777         off32 = 0;
1778         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1779                 off32 += 3;
1780         }
1781         if (sysinfo->memory_frequency == 667) {
1782                 off32 += 3;
1783         }
1784         off32 += sysinfo->cas - 3;
1785         reg32 = drt0_table[off32];
1786         temp_drt |= (reg32 << 11);
1787
1788         /* Read Auto Precharge to Activate */
1789
1790         temp_drt |= (8 << 0);
1791
1792         MCHBAR32(C0DRT0) = temp_drt;
1793         MCHBAR32(C1DRT0) = temp_drt;
1794
1795         /* Calculate DRT1 */
1796
1797         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1798
1799         /* DRAM RASB Precharge */
1800         temp_drt |= (sysinfo->trp - 2) << 0;
1801
1802         /* DRAM RASB to CASB Delay */
1803         temp_drt |= (sysinfo->trcd - 2) << 4;
1804
1805         /* CASB Latency */
1806         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1807
1808         /* Refresh Cycle Time */
1809         temp_drt |= (sysinfo->trfc) << 10;
1810
1811         /* Pre-All to Activate Delay */
1812         temp_drt |= (0 << 16);
1813
1814         /* Precharge to Precharge Delay stays at 1 clock */
1815         temp_drt |= (0 << 18);
1816
1817         /* Activate to Precharge Delay */
1818         temp_drt |= (sysinfo->tras << 19);
1819
1820         /* Read to Precharge (tRTP) */
1821         if (sysinfo->memory_frequency == 667) {
1822                 temp_drt |= (1 << 28);
1823         } else {
1824                 temp_drt |= (0 << 28);
1825         }
1826
1827         /* Determine page size */
1828         reg32 = 0;
1829         page_size = 1; /* Default: 1k pagesize */
1830         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1831                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1832                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1833                         page_size = 2; /* 2k pagesize */
1834         }
1835
1836         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1837                 reg32 = 1;
1838         }
1839         if (sysinfo->memory_frequency == 667) {
1840                 reg32 = page_size;
1841         }
1842
1843         temp_drt |= (reg32 << 30);
1844
1845         MCHBAR32(C0DRT1) = temp_drt;
1846         MCHBAR32(C1DRT1) = temp_drt;
1847
1848         /* Program DRT2 */
1849         reg32 = MCHBAR32(C0DRT2);
1850         reg32 &= ~(1 << 8);
1851         MCHBAR32(C0DRT2) = reg32;
1852
1853         reg32 = MCHBAR32(C1DRT2);
1854         reg32 &= ~(1 << 8);
1855         MCHBAR32(C1DRT2) = reg32;
1856
1857         /* Calculate DRT3 */
1858         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1859
1860         /* Get old tRFC value */
1861         reg32 = MCHBAR32(C0DRT1) >> 10;
1862         reg32 &= 0x3f;
1863
1864         /* 788nS - tRFC */
1865         switch (sysinfo->memory_frequency) {
1866         case 400: /* 5nS */
1867                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1868                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1869                 break;
1870         case 533: /* 3.75nS */
1871                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1872                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1873                 break;
1874         case 667: /* 3nS */
1875                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1876                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1877                 break;
1878         }
1879
1880         temp_drt |= reg32;
1881
1882         MCHBAR32(C0DRT3) = temp_drt;
1883         MCHBAR32(C1DRT3) = temp_drt;
1884 }
1885
1886 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1887 {
1888         u32 reg32;
1889
1890         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1891
1892         if (sdram_capabilities_interleave() &&
1893                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1894                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1895                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1896                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1897                 /* Both channels equipped with DIMMs of the same size */
1898                 sysinfo->interleaved = 1;
1899         } else {
1900                 sysinfo->interleaved = 0;
1901         }
1902
1903         reg32 = MCHBAR32(DCC);
1904         reg32 &= ~(7 << 0);
1905
1906         if(sysinfo->interleaved) {
1907                 /* Dual Channel Interleaved */
1908                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1909                 reg32 |= (1 << 1);
1910         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1911                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1912                 /* Channel 1 only */
1913                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1914                 reg32 |= (1 << 2);
1915         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1916                         SYSINFO_DIMM_NOT_POPULATED) {
1917                 /* Dual Channel Assymetric */
1918                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1919                 reg32 |= (1 << 0);
1920         } else {
1921                 /* All bits 0 means Single Channel 0 operation */
1922                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1923         }
1924
1925         /* Now disable channel XORing */
1926         reg32 |= (1 << 10);
1927
1928         MCHBAR32(DCC) = reg32;
1929
1930         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1931 }
1932
1933 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1934 {
1935         volatile u16 reg16;
1936
1937         MCHBAR32(PLLMON) = 0x80800000;
1938
1939         sysinfo->fsb_frequency = fsbclk();
1940         if (sysinfo->fsb_frequency == 0xffff)
1941                 die("Unsupported FSB speed");
1942
1943         /* Program CPCTL according to FSB speed */
1944         /* Only write the lower byte */
1945         switch (sysinfo->fsb_frequency) {
1946         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1947         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1948         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1949         }
1950
1951         MCHBAR16(CPCTL) &= ~(1 << 11);
1952
1953         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1954 }
1955
1956 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1957 {
1958         u8  reg8;
1959         u16 reg16;
1960         u8  freq, second_vco, voltage;
1961
1962 #define CRCLK_166MHz    0x00
1963 #define CRCLK_200MHz    0x01
1964 #define CRCLK_250MHz    0x03
1965 #define CRCLK_400MHz    0x05
1966
1967 #define CDCLK_200MHz    0x00
1968 #define CDCLK_320MHz    0x40
1969
1970 #define VOLTAGE_1_05    0x00
1971 #define VOLTAGE_1_50    0x01
1972
1973         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1974
1975         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1976
1977         voltage = VOLTAGE_1_05;
1978         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1979                 voltage = VOLTAGE_1_50;
1980         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1981
1982         /* Gate graphics hardware for frequency change */
1983         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1984         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1985         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1986
1987         /* Get graphics frequency capabilities */
1988         reg8 = sdram_capabilities_core_frequencies();
1989
1990         freq = CRCLK_250MHz;
1991         switch (reg8) {
1992         case GFX_FREQUENCY_CAP_ALL:
1993                 if (voltage == VOLTAGE_1_05)
1994                         freq = CRCLK_250MHz;
1995                 else
1996                         freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
1997                 break;
1998         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1999         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
2000         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
2001         }
2002
2003         if (freq != CRCLK_400MHz) {
2004                 /* What chipset are we? Force 166MHz for GMS */
2005                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
2006                 if (reg8==2)
2007                         freq = CRCLK_166MHz;
2008         }
2009
2010         printk(BIOS_DEBUG, "Render: ");
2011         switch (freq) {
2012         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2013         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2014         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2015         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2016         }
2017
2018         if (i945_silicon_revision() == 0) {
2019                 sysinfo->mvco4x = 1;
2020         } else {
2021                 sysinfo->mvco4x = 0;
2022         }
2023
2024         second_vco = 0;
2025
2026         if (voltage == VOLTAGE_1_50) {
2027                 second_vco = 1;
2028         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
2029                 u16 mem = sysinfo->memory_frequency;
2030                 u16 fsb = sysinfo->fsb_frequency;
2031
2032                 if ( (fsb == 667 && mem == 533) ||
2033                      (fsb == 533 && mem == 533) ||
2034                      (fsb == 533 && mem == 400)) {
2035                         second_vco = 1;
2036                 }
2037
2038                 if (fsb == 667 && mem == 533)
2039                         sysinfo->mvco4x = 1;
2040         }
2041
2042         if (second_vco) {
2043                 sysinfo->clkcfg_bit7=1;
2044         } else {
2045                 sysinfo->clkcfg_bit7=0;
2046         }
2047
2048         /* Graphics Core Render Clock */
2049         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2050         reg16 &= ~( (7 << 0) | (1 << 13) );
2051         reg16 |= freq;
2052         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2053
2054         /* Graphics Core Display Clock */
2055         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2056         reg8 &= ~( (1<<7) | (7<<4) );
2057
2058         if (voltage == VOLTAGE_1_05) {
2059                 reg8 |= CDCLK_200MHz;
2060                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2061         } else {
2062                 reg8 |= CDCLK_320MHz;
2063                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2064         }
2065         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2066
2067         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2068
2069         reg8 |= (1<<3) | (1<<1);
2070         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2071
2072         reg8 |= 0x0f;
2073         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2074
2075         /* Ungate core render and display clocks */
2076         reg8 &= 0xf0;
2077         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2078 }
2079
2080 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2081 {
2082         u32 clkcfg;
2083         u8 reg8;
2084
2085         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2086
2087         clkcfg = MCHBAR32(CLKCFG);
2088
2089         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2090
2091         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2092
2093         if (sysinfo->mvco4x) {
2094                 printk(BIOS_DEBUG, "MVCO 4x, ");
2095                 clkcfg &= ~(1 << 12);
2096         }
2097
2098         if (sysinfo->clkcfg_bit7) {
2099                 printk(BIOS_DEBUG, "second VCO, ");
2100
2101                 clkcfg |= (1 << 7);
2102         }
2103
2104         switch (sysinfo->memory_frequency) {
2105         case 400: clkcfg |= (2 << 4); break;
2106         case 533: clkcfg |= (3 << 4); break;
2107         case 667: clkcfg |= (4 << 4); break;
2108         default: die("Target Memory Frequency Error");
2109         }
2110
2111         if (MCHBAR32(CLKCFG) == clkcfg) {
2112                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2113                 return;
2114         }
2115
2116         MCHBAR32(CLKCFG) = clkcfg;
2117
2118         /* Make sure the following code is in the
2119          * cache before we execute it.
2120          */
2121         goto cache_code;
2122 vco_update:
2123         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2124         reg8 &= ~(1 << 7);
2125         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2126
2127         clkcfg &= ~(1 << 10);
2128         MCHBAR32(CLKCFG) = clkcfg;
2129         clkcfg |= (1 << 10);
2130         MCHBAR32(CLKCFG) = clkcfg;
2131
2132         asm volatile (
2133                 "       movl $0x100, %%ecx\n"
2134                 "delay_update:\n"
2135                 "       nop\n"
2136                 "       nop\n"
2137                 "       nop\n"
2138                 "       nop\n"
2139                 "       loop delay_update\n"
2140                 : /* No outputs */
2141                 : /* No inputs */
2142                 : "%ecx", "memory"
2143                 );
2144
2145         clkcfg &= ~(1 << 10);
2146         MCHBAR32(CLKCFG) = clkcfg;
2147
2148         goto out;
2149 cache_code:
2150         goto vco_update;
2151 out:
2152
2153         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2154         printk(BIOS_DEBUG, "ok\n");
2155 }
2156
2157 static void sdram_program_clock_crossing(void)
2158 {
2159         int idx = 0;
2160
2161         /**
2162          * We add the indices according to our clocks from CLKCFG.
2163          */
2164 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2165         static const u32 data_clock_crossing[] = {
2166                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2167                 0xffffffff, 0xffffffff, /*  nonexistant  */
2168                 0xffffffff, 0xffffffff, /*  nonexistant  */
2169
2170                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2171                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2172                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2173
2174                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2175                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2176                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2177
2178                 0xffffffff, 0xffffffff, /*  nonexistant  */
2179                 0xffffffff, 0xffffffff, /*  nonexistant  */
2180                 0xffffffff, 0xffffffff, /*  nonexistant  */
2181
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183                 0xffffffff, 0xffffffff, /*  nonexistant  */
2184                 0xffffffff, 0xffffffff, /*  nonexistant  */
2185         };
2186
2187         static const u32 command_clock_crossing[] = {
2188                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2189                 0xffffffff, 0xffffffff, /*  nonexistant  */
2190                 0xffffffff, 0xffffffff, /*  nonexistant  */
2191
2192                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2193                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2194                 0xffffffff, 0xffffffff, /*  nonexistant  */
2195
2196                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2197                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2198                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2199
2200                 0xffffffff, 0xffffffff, /*  nonexistant  */
2201                 0xffffffff, 0xffffffff, /*  nonexistant  */
2202                 0xffffffff, 0xffffffff, /*  nonexistant  */
2203
2204                 0xffffffff, 0xffffffff, /*  nonexistant  */
2205                 0xffffffff, 0xffffffff, /*  nonexistant  */
2206                 0xffffffff, 0xffffffff, /*  nonexistant  */
2207         };
2208
2209 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2210         /* i945 G/P */
2211         static const u32 data_clock_crossing[] = {
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214                 0xffffffff, 0xffffffff, /*  nonexistant  */
2215
2216                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2217                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2218                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2219
2220                 0xffffffff, 0xffffffff, /*  nonexistant  */
2221                 0xffffffff, 0xffffffff, /*  nonexistant  */
2222                 0xffffffff, 0xffffffff, /*  nonexistant  */
2223
2224                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2225                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2226                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2227
2228                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2229                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2230                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2231         };
2232
2233         static const u32 command_clock_crossing[] = {
2234                 0xffffffff, 0xffffffff, /*  nonexistant  */
2235                 0xffffffff, 0xffffffff, /*  nonexistant  */
2236                 0xffffffff, 0xffffffff, /*  nonexistant  */
2237
2238                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2239                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2240                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2241
2242                 0xffffffff, 0xffffffff, /*  nonexistant  */
2243                 0xffffffff, 0xffffffff, /*  nonexistant  */
2244                 0xffffffff, 0xffffffff, /*  nonexistant  */
2245
2246                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2247                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2248                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2249
2250                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2251                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2252                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2253         };
2254 #endif
2255
2256         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2257
2258         printk(BIOS_DEBUG, "MEM=");
2259         switch (memclk()) {
2260         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2261         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2262         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2263         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2264         }
2265
2266         printk(BIOS_DEBUG, " FSB=");
2267         switch (fsbclk()) {
2268         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2269         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2270         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2271         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2272         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2273         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2274         }
2275
2276         if (command_clock_crossing[idx]==0xffffffff) {
2277                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2278         }
2279
2280         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2281         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2282
2283         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2284         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2285         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2286         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2287
2288         printk(BIOS_DEBUG, "... ok\n");
2289 }
2290
2291 static void sdram_disable_fast_dispatch(void)
2292 {
2293         u32 reg32;
2294
2295         reg32 = MCHBAR32(FSBPMC3);
2296         reg32 |= (1 << 1);
2297         MCHBAR32(FSBPMC3) = reg32;
2298
2299         reg32 = MCHBAR32(SBTEST);
2300         reg32 |= (3 << 1);
2301         MCHBAR32(SBTEST) = reg32;
2302 }
2303
2304 static void sdram_pre_jedec_initialization(void)
2305 {
2306         u32 reg32;
2307
2308         reg32 = MCHBAR32(WCC);
2309         reg32 &= 0x113ff3ff;
2310         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2311         MCHBAR32(WCC) = reg32;
2312
2313         MCHBAR32(SMVREFC) |= (1 << 6);
2314
2315         MCHBAR32(MMARB0) &= ~(3 << 17);
2316         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2317
2318         MCHBAR32(MMARB1) &= ~(7 << 8);
2319         MCHBAR32(MMARB1) |= (3 << 8);
2320
2321         /* Adaptive Idle Timer Control */
2322         MCHBAR32(C0AIT) = 0x000006c4;
2323         MCHBAR32(C0AIT+4) = 0x871a066d;
2324
2325         MCHBAR32(C1AIT) = 0x000006c4;
2326         MCHBAR32(C1AIT+4) = 0x871a066d;
2327 }
2328
2329 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2330 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2331 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2332 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2333 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2334 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2335 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2336 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2337
2338 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2339 {
2340         u32 chan0 = 0, chan1 = 0;
2341         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2342
2343         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2344                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2345         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2346                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2347         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2348         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2349
2350         if (sdram_capabilities_enhanced_addressing_xor()) {
2351                 if (!sysinfo->interleaved) {
2352                         /* Single Channel & Dual Channel Assymetric */
2353                         if (chan0_populated) {
2354                                 if (chan0_dualsided) {
2355                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2356                                 } else {
2357                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2358                                 }
2359                         }
2360                         if (chan1_populated) {
2361                                 if (chan1_dualsided) {
2362                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2363                                 } else {
2364                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2365                                 }
2366                         }
2367                 } else {
2368                         /* Interleaved has always both channels populated */
2369                         if (chan0_dualsided) {
2370                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2371                         } else {
2372                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2373                         }
2374
2375                         if (chan1_dualsided) {
2376                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2377                         } else {
2378                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2379                         }
2380                 }
2381         } else {
2382                 if (!sysinfo->interleaved) {
2383                         /* Single Channel & Dual Channel Assymetric */
2384                         if (chan0_populated) {
2385                                 if (chan0_dualsided) {
2386                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2387                                 } else {
2388                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2389                                 }
2390                         }
2391                         if (chan1_populated) {
2392                                 if (chan1_dualsided) {
2393                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2394                                 } else {
2395                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2396                                 }
2397                         }
2398                 } else {
2399                         /* Interleaved has always both channels populated */
2400                         if (chan0_dualsided) {
2401                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2402                         } else {
2403                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2404                         }
2405
2406                         if (chan1_dualsided) {
2407                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2408                         } else {
2409                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2410                         }
2411                 }
2412         }
2413
2414         MCHBAR32(C0DRC1) &= 0x00ffffff;
2415         MCHBAR32(C0DRC1) |= chan0;
2416         MCHBAR32(C1DRC1) &= 0x00ffffff;
2417         MCHBAR32(C1DRC1) |= chan1;
2418 }
2419
2420 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2421 {
2422         u32 reg32;
2423
2424         /* Enable Channel XORing for Dual Channel Interleave */
2425         if (sysinfo->interleaved) {
2426
2427                 reg32 = MCHBAR32(DCC);
2428 #if CONFIG_CHANNEL_XOR_RANDOMIZATION
2429                 reg32 &= ~(1 << 10);
2430                 reg32 |= (1 << 9);
2431 #else
2432                 reg32 &= ~(1 << 9);
2433 #endif
2434                 MCHBAR32(DCC) = reg32;
2435         }
2436
2437         /* DRAM mode optimizations */
2438         sdram_enhanced_addressing_mode(sysinfo);
2439
2440         reg32 = MCHBAR32(FSBPMC3);
2441         reg32 &= ~(1 << 1);
2442         MCHBAR32(FSBPMC3) = reg32;
2443
2444         reg32 = MCHBAR32(SBTEST);
2445         reg32 &= ~(1 << 2);
2446         MCHBAR32(SBTEST) = reg32;
2447
2448         reg32 = MCHBAR32(SBOCC);
2449         reg32 &= 0xffbdb6ff;
2450         reg32 |= (0xbdb6 << 8) | (1 << 0);
2451         MCHBAR32(SBOCC) = reg32;
2452 }
2453
2454 static void sdram_power_management(struct sys_info *sysinfo)
2455 {
2456         u8 reg8;
2457         u16 reg16;
2458         u32 reg32;
2459         int integrated_graphics = 1;
2460         int i;
2461
2462         reg32 = MCHBAR32(C0DRT2);
2463         reg32 &= 0xffffff00;
2464         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2465         reg32 |= (1 << 5) | (1 << 4);
2466         MCHBAR32(C0DRT2) = reg32;
2467
2468         reg32 = MCHBAR32(C1DRT2);
2469         reg32 &= 0xffffff00;
2470         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2471         reg32 |= (1 << 5) | (1 << 4);
2472         MCHBAR32(C1DRT2) = reg32;
2473
2474         reg32 = MCHBAR32(C0DRC1);
2475
2476         reg32 |= (1 << 12) | (1 << 11);
2477         MCHBAR32(C0DRC1) = reg32;
2478
2479         reg32 = MCHBAR32(C1DRC1);
2480
2481         reg32 |= (1 << 12) | (1 << 11);
2482         MCHBAR32(C1DRC1) = reg32;
2483
2484         if (i945_silicon_revision()>1) {
2485                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2486                 u16 peg_bits = (1 << 5) | (1 << 0);
2487
2488                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2489         } else {
2490                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2491                 u16 peg_bits = (1 << 5) | (1 << 0);
2492
2493                 /* Rev 0 and 1 */
2494                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2495         }
2496
2497         reg16 = MCHBAR16(UPMC2);
2498         reg16 &= 0xfc00;
2499         reg16 |= 0x0100;
2500         MCHBAR16(UPMC2) = reg16;
2501
2502         MCHBAR32(UPMC3) = 0x000f06ff;
2503
2504         for (i=0; i<5; i++) {
2505                 MCHBAR32(UPMC3) &= ~(1 << 16);
2506                 MCHBAR32(UPMC3) |= (1 << 16);
2507         }
2508
2509         MCHBAR32(GIPMC1) = 0x8000000c;
2510
2511         reg16 = MCHBAR16(CPCTL);
2512         reg16 &= ~(7 << 11);
2513         if (i945_silicon_revision()>2) {
2514                 reg16 |= (6 << 11);
2515         } else {
2516                 reg16 |= (4 << 11);
2517         }
2518         MCHBAR16(CPCTL) = reg16;
2519
2520 #if 0
2521         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2522 #else
2523         if (i945_silicon_revision() != 0) {
2524 #endif
2525                 switch (sysinfo->fsb_frequency) {
2526                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2527                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2528                 }
2529         } else {
2530                 switch (sysinfo->fsb_frequency) {
2531                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2532                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2533                 }
2534         }
2535
2536         MCHBAR32(FSBPMC1) = 0x8000000c;
2537
2538         reg32 = MCHBAR32(C2C3TT);
2539         reg32 &= 0xffff0000;
2540         switch (sysinfo->fsb_frequency) {
2541         case 667: reg32 |= 0x0600; break;
2542         case 533: reg32 |= 0x0480; break;
2543         }
2544         MCHBAR32(C2C3TT) = reg32;
2545
2546         reg32 = MCHBAR32(C3C4TT);
2547         reg32 &= 0xffff0000;
2548         switch (sysinfo->fsb_frequency) {
2549         case 667: reg32 |= 0x0b80; break;
2550         case 533: reg32 |= 0x0980; break;
2551         }
2552         MCHBAR32(C3C4TT) = reg32;
2553
2554         if (i945_silicon_revision() == 0) {
2555                 MCHBAR32(ECO) &= ~(1 << 16);
2556         } else {
2557                 MCHBAR32(ECO) |= (1 << 16);
2558         }
2559
2560 #if 0
2561
2562         if (i945_silicon_revision() == 0) {
2563                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2564         } else {
2565                 MCHBAR32(FSBPMC3) |= (1 << 29);
2566         }
2567 #endif
2568         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2569
2570         MCHBAR32(FSBPMC3) |= (1 << 21);
2571
2572         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2573
2574         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2575
2576         reg32 = MCHBAR32(FSBPMC4);
2577         reg32 &= ~(3 << 24);
2578         reg32 |= ( 2 << 24);
2579         MCHBAR32(FSBPMC4) = reg32;
2580
2581         MCHBAR32(FSBPMC4) |= (1 << 21);
2582
2583         MCHBAR32(FSBPMC4) |= (1 << 5);
2584
2585         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2586                 /* stepping 0 and 1 or CPUID 6e8 */
2587                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2588         } else {
2589                 MCHBAR32(FSBPMC4) |= (1 << 4);
2590         }
2591
2592         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2593         reg8 |= (1 << 4);
2594         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2595
2596         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2597         reg8 |= (1 << 2);
2598         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2599
2600 #ifdef C2_SELF_REFRESH_DISABLE
2601
2602         if (integrated_graphics) {
2603                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2604                 MCHBAR16(MIPMC4) = 0x0468;
2605                 MCHBAR16(MIPMC5) = 0x046c;
2606                 MCHBAR16(MIPMC6) = 0x046c;
2607         } else {
2608                 MCHBAR16(MIPMC4) = 0x6468;
2609                 MCHBAR16(MIPMC5) = 0x646c;
2610                 MCHBAR16(MIPMC6) = 0x646c;
2611         }
2612 #else
2613         if (integrated_graphics) {
2614                 MCHBAR16(MIPMC4) = 0x04f8;
2615                 MCHBAR16(MIPMC5) = 0x04fc;
2616                 MCHBAR16(MIPMC6) = 0x04fc;
2617         } else {
2618                 MCHBAR16(MIPMC4) = 0x64f8;
2619                 MCHBAR16(MIPMC5) = 0x64fc;
2620                 MCHBAR16(MIPMC6) = 0x64fc;
2621         }
2622
2623 #endif
2624
2625         reg32 = MCHBAR32(PMCFG);
2626         reg32 &= ~(3 << 17);
2627         reg32 |= (2 << 17);
2628         MCHBAR32(PMCFG) = reg32;
2629
2630         MCHBAR32(PMCFG) |= (1 << 4);
2631
2632         reg32 = MCHBAR32(0xc30);
2633         reg32 &= 0xffffff00;
2634         reg32 |= 0x01;
2635         MCHBAR32(0xc30) = reg32;
2636
2637         MCHBAR32(0xb18) &= ~(1 << 21);
2638 }
2639
2640 static void sdram_thermal_management(void)
2641 {
2642
2643         MCHBAR8(TCO1) = 0x00;
2644         MCHBAR8(TCO0) = 0x00;
2645
2646         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2647          * 0x30/0x32.
2648          */
2649
2650         /* TODO This is not implemented yet. Volunteers? */
2651 }
2652
2653 static void sdram_save_receive_enable(void)
2654 {
2655         int i;
2656         u32 reg32;
2657         u8 values[4];
2658
2659         /* The following values are stored to an unused CMOS
2660          * area and restored instead of recalculated in case
2661          * of an S3 resume.
2662          *
2663          * C0WL0REOST [7:0]             -> 8 bit
2664          * C1WL0REOST [7:0]             -> 8 bit
2665          * RCVENMT    [11:8] [3:0]      -> 8 bit
2666          * C0DRT1     [27:24]           -> 4 bit
2667          * C1DRT1     [27:24]           -> 4 bit
2668          */
2669
2670         values[0] = MCHBAR8(C0WL0REOST);
2671         values[1] = MCHBAR8(C1WL0REOST);
2672
2673         reg32 = MCHBAR32(RCVENMT);
2674         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2675
2676         reg32 = MCHBAR32(C0DRT1);
2677         values[3] = (reg32 >> 24) & 0x0f;
2678         reg32 = MCHBAR32(C1DRT1);
2679         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2680
2681         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2682          * so we grab bytes 128 - 131 to save the receive enable values
2683          */
2684
2685         for (i=0; i<4; i++)
2686                 cmos_write(values[i], 128 + i);
2687 }
2688
2689 static void sdram_recover_receive_enable(void)
2690 {
2691         int i;
2692         u32 reg32;
2693         u8 values[4];
2694
2695         for (i=0; i<4; i++)
2696                 values[i] = cmos_read(128 + i);
2697
2698         MCHBAR8(C0WL0REOST) = values[0];
2699         MCHBAR8(C1WL0REOST) = values[1];
2700
2701         reg32 = MCHBAR32(RCVENMT);
2702         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2703         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2704         MCHBAR32(RCVENMT) = reg32;
2705
2706         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2707         reg32 |= (u32)(values[3] & 0x0f) << 24;
2708         MCHBAR32(C0DRT1) = reg32;
2709
2710         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2711         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2712         MCHBAR32(C1DRT1) = reg32;
2713 }
2714
2715 #include "rcven.c"
2716
2717 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2718 {
2719         MCHBAR32(REPC) |= (1 << 0);
2720
2721         /* enable upper CMOS */
2722         RCBA32(0x3400) = (1 << 2);
2723
2724         /* Program Receive Enable Timings */
2725         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2726                 sdram_recover_receive_enable();
2727         } else {
2728                 receive_enable_adjust(sysinfo);
2729                 sdram_save_receive_enable();
2730         }
2731
2732         MCHBAR32(C0DRC1) |= (1 << 6);
2733         MCHBAR32(C1DRC1) |= (1 << 6);
2734         MCHBAR32(C0DRC1) &= ~(1 << 6);
2735         MCHBAR32(C1DRC1) &= ~(1 << 6);
2736
2737         MCHBAR32(MIPMC3) |= (0x0f << 0);
2738 }
2739
2740 /**
2741  * @brief Enable On-Die Termination for DDR2.
2742  *
2743  */
2744
2745 static void sdram_on_die_termination(struct sys_info *sysinfo)
2746 {
2747         static const u32 odt[] = {
2748                 0x00024911, 0xe0010000,
2749                 0x00049211, 0xe0020000,
2750                 0x0006db11, 0xe0030000,
2751         };
2752
2753         u32 reg32;
2754         int cas;
2755
2756         reg32 = MCHBAR32(ODTC);
2757         reg32 &= ~(3 << 16);
2758         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2759         MCHBAR32(ODTC) = reg32;
2760
2761         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2762                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2763                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2764
2765                 reg32 = MCHBAR32(C0ODT);
2766                 reg32 &= ~(7 << 28);
2767                 MCHBAR32(C0ODT) = reg32;
2768                 reg32 = MCHBAR32(C1ODT);
2769                 reg32 &= ~(7 << 28);
2770                 MCHBAR32(C1ODT) = reg32;
2771         }
2772
2773         cas = sysinfo->cas;
2774
2775         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2776         reg32 |= odt[(cas-3) * 2];
2777         MCHBAR32(C0ODT) = reg32;
2778
2779         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2780         reg32 |= odt[(cas-3) * 2];
2781         MCHBAR32(C1ODT) = reg32;
2782
2783         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2784         reg32 |= odt[((cas-3) * 2) + 1];
2785         MCHBAR32(C0ODT + 4) = reg32;
2786
2787         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2788         reg32 |= odt[((cas-3) * 2) + 1];
2789         MCHBAR32(C1ODT + 4) = reg32;
2790 }
2791
2792 /**
2793  * @brief Enable clocks to populated sockets
2794  */
2795
2796 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2797 {
2798         u8 clocks[2] = { 0, 0 };
2799
2800 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2801 #define CLOCKS_WIDTH 2
2802 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2803 #define CLOCKS_WIDTH 3
2804 #endif
2805         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2806                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2807
2808         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2809                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2810
2811         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2812                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2813
2814         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2815                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2816
2817 #if CONFIG_OVERRIDE_CLOCK_DISABLE
2818         /* Usually system firmware turns off system memory clock signals
2819          * to unused SO-DIMM slots to reduce EMI and power consumption.
2820          * However, the Kontron 986LCD-M does not like unused clock
2821          * signals to be disabled.
2822          */
2823
2824         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2825         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2826 #endif
2827
2828         MCHBAR8(C0DCLKDIS) = clocks[0];
2829         MCHBAR8(C1DCLKDIS) = clocks[1];
2830 }
2831
2832 #define RTT_ODT_NONE    0
2833 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2834 #define RTT_ODT_75_OHM  (1 << 5)
2835 #define RTT_ODT_150_OHM (1 << 9)
2836
2837 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2838
2839 #define MRS_CAS_3       (3 << 7)
2840 #define MRS_CAS_4       (4 << 7)
2841 #define MRS_CAS_5       (5 << 7)
2842
2843 #define MRS_TWR_3       (2 << 12)
2844 #define MRS_TWR_4       (3 << 12)
2845 #define MRS_TWR_5       (4 << 12)
2846
2847 #define MRS_BT          (1 << 6)
2848
2849 #define MRS_BL4         (2 << 3)
2850 #define MRS_BL8         (3 << 3)
2851
2852 static void sdram_jedec_enable(struct sys_info *sysinfo)
2853 {
2854         int i, nonzero;
2855         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2856
2857         for (i = 0, nonzero = -1; i < 8; i++) {
2858                 if (sysinfo->banksize[i]  == 0) {
2859                         continue;
2860                 }
2861
2862                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2863                 switch (i) {
2864                 case 0:
2865                         /* Start at address 0 */
2866                         bankaddr = 0;
2867                         break;
2868                 case 4:
2869                         if (sysinfo->interleaved) {
2870                                 bankaddr = 0x40;
2871                                 break;
2872                         }
2873                 default:
2874                         if (nonzero != -1) {
2875                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2876                                 bankaddr += sysinfo->banksize[nonzero] <<
2877                                         (sysinfo->interleaved ? 26 : 25);
2878                                 break;
2879                         }
2880                         /* No populated bank hit before. Start at address 0 */
2881                         bankaddr = 0;
2882                 }
2883
2884                 /* We have a bank with a non-zero size.. Remember it
2885                  * for the next offset we have to calculate
2886                  */
2887                 nonzero = i;
2888
2889                 /* Get CAS latency set up */
2890                 switch (sysinfo->cas) {
2891                 case 5: mrsaddr = MRS_CAS_5; break;
2892                 case 4: mrsaddr = MRS_CAS_4; break;
2893                 case 3: mrsaddr = MRS_CAS_3; break;
2894                 default: die("Jedec Error (CAS).\n");
2895                 }
2896
2897                 /* Get tWR set */
2898                 switch (sysinfo->twr) {
2899                 case 5: mrsaddr |= MRS_TWR_5; break;
2900                 case 4: mrsaddr |= MRS_TWR_4; break;
2901                 case 3: mrsaddr |= MRS_TWR_3; break;
2902                 default: die("Jedec Error (tWR).\n");
2903                 }
2904
2905                 /* Set "Burst Type" */
2906                 mrsaddr |= MRS_BT;
2907
2908                 /* Interleaved */
2909                 if (sysinfo->interleaved) {
2910                         mrsaddr = mrsaddr << 1;
2911                 }
2912
2913                 /* Only burst length 8 supported */
2914                 mrsaddr |= MRS_BL8;
2915
2916                 /* Apply NOP */
2917                 PRINTK_DEBUG("Apply NOP\n");
2918                 do_ram_command(RAM_COMMAND_NOP);
2919                 ram_read32(bankaddr);
2920
2921                 /* Precharge all banks */
2922                 PRINTK_DEBUG("All Banks Precharge\n");
2923                 do_ram_command(RAM_COMMAND_PRECHARGE);
2924                 ram_read32(bankaddr);
2925
2926                 /* Extended Mode Register Set (2) */
2927                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2928                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2929                 ram_read32(bankaddr);
2930
2931                 /* Extended Mode Register Set (3) */
2932                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2933                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2934                 ram_read32(bankaddr);
2935
2936                 /* Extended Mode Register Set */
2937                 PRINTK_DEBUG("Extended Mode Register Set\n");
2938                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2939                 tmpaddr = bankaddr;
2940                 if (!sdram_capabilities_dual_channel()) {
2941                         tmpaddr |= RTT_ODT_75_OHM;
2942                 } else if (sysinfo->interleaved) {
2943                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2944                 } else {
2945                         tmpaddr |= RTT_ODT_150_OHM;
2946                 }
2947                 ram_read32(tmpaddr);
2948
2949                 /* Mode Register Set: Reset DLLs */
2950                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2951                 do_ram_command(RAM_COMMAND_MRS);
2952                 tmpaddr = bankaddr;
2953                 tmpaddr |= mrsaddr;
2954                 /* Set DLL reset bit */
2955                 if (sysinfo->interleaved)
2956                         tmpaddr |= (1 << 12);
2957                 else
2958                         tmpaddr |= (1 << 11);
2959                 ram_read32(tmpaddr);
2960
2961                 /* Precharge all banks */
2962                 PRINTK_DEBUG("All Banks Precharge\n");
2963                 do_ram_command(RAM_COMMAND_PRECHARGE);
2964                 ram_read32(bankaddr);
2965
2966                 /* CAS before RAS Refresh */
2967                 PRINTK_DEBUG("CAS before RAS\n");
2968                 do_ram_command(RAM_COMMAND_CBR);
2969
2970                 /* CBR wants two READs */
2971                 ram_read32(bankaddr);
2972                 ram_read32(bankaddr);
2973
2974                 /* Mode Register Set: Enable DLLs */
2975                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2976                 do_ram_command(RAM_COMMAND_MRS);
2977
2978                 tmpaddr = bankaddr;
2979                 tmpaddr |= mrsaddr;
2980                 ram_read32(tmpaddr);
2981
2982                 /* Extended Mode Register Set */
2983                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2984                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2985
2986                 tmpaddr = bankaddr;
2987                 if (!sdram_capabilities_dual_channel()) {
2988
2989                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2990                 } else if (sysinfo->interleaved) {
2991                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2992                 } else {
2993                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2994                 }
2995                 ram_read32(tmpaddr);
2996
2997                 /* Extended Mode Register Set */
2998                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2999                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
3000
3001                 tmpaddr = bankaddr;
3002                 if (!sdram_capabilities_dual_channel()) {
3003                         tmpaddr |= RTT_ODT_75_OHM;
3004                 } else if (sysinfo->interleaved) {
3005                         tmpaddr |= (RTT_ODT_150_OHM << 1);
3006                 } else {
3007                         tmpaddr |= RTT_ODT_150_OHM;
3008                 }
3009                 ram_read32(tmpaddr);
3010         }
3011 }
3012
3013 static void sdram_init_complete(void)
3014 {
3015         PRINTK_DEBUG("Normal Operation\n");
3016         do_ram_command(RAM_COMMAND_NORMAL);
3017 }
3018
3019 static void sdram_setup_processor_side(void)
3020 {
3021         if (i945_silicon_revision() == 0)
3022                 MCHBAR32(FSBPMC3) |= (1 << 2);
3023
3024         MCHBAR8(0xb00) |= 1;
3025
3026         if (i945_silicon_revision() == 0)
3027                 MCHBAR32(SLPCTL) |= (1 << 8);
3028 }
3029
3030 /**
3031  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3032  */
3033 void sdram_initialize(int boot_path)
3034 {
3035         struct sys_info sysinfo;
3036         u8 reg8, cas_mask;
3037
3038         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3039
3040         memset(&sysinfo, 0, sizeof(sysinfo));
3041
3042         sysinfo.boot_path = boot_path;
3043
3044         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3045         sdram_get_dram_configuration(&sysinfo);
3046
3047         /* If error, do cold boot */
3048         sdram_detect_errors(&sysinfo);
3049
3050         /* Check whether we have stacked DIMMs */
3051         sdram_verify_package_type(&sysinfo);
3052
3053         /* Determine common CAS */
3054         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3055
3056         /* Choose Common Frequency */
3057         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3058
3059         /* Determine smallest common tRAS */
3060         sdram_detect_smallest_tRAS(&sysinfo);
3061
3062         /* Determine tRP */
3063         sdram_detect_smallest_tRP(&sysinfo);
3064
3065         /* Determine tRCD */
3066         sdram_detect_smallest_tRCD(&sysinfo);
3067
3068         /* Determine smallest refresh period */
3069         sdram_detect_smallest_refresh(&sysinfo);
3070
3071         /* Verify all DIMMs support burst length 8 */
3072         sdram_verify_burst_length(&sysinfo);
3073
3074         /* determine tWR */
3075         sdram_detect_smallest_tWR(&sysinfo);
3076
3077         /* Determine DIMM size parameters (rows, columns banks) */
3078         sdram_detect_dimm_size(&sysinfo);
3079
3080         /* determine tRFC */
3081         sdram_detect_smallest_tRFC(&sysinfo);
3082
3083         /* Program PLL settings */
3084         sdram_program_pll_settings(&sysinfo);
3085
3086         /* Program Graphics Frequency */
3087         sdram_program_graphics_frequency(&sysinfo);
3088
3089         /* Program System Memory Frequency */
3090         sdram_program_memory_frequency(&sysinfo);
3091
3092         /* Determine Mode of Operation (Interleaved etc) */
3093         sdram_set_channel_mode(&sysinfo);
3094
3095         /* Program Clock Crossing values */
3096         sdram_program_clock_crossing();
3097
3098         /* Disable fast dispatch */
3099         sdram_disable_fast_dispatch();
3100
3101         /* Enable WIODLL Power Down in ACPI states */
3102         MCHBAR32(C0DMC) |= (1 << 24);
3103         MCHBAR32(C1DMC) |= (1 << 24);
3104
3105         /* Program DRAM Row Boundary/Attribute Registers */
3106
3107         /* program row size DRB and set TOLUD */
3108         sdram_program_row_boundaries(&sysinfo);
3109
3110         /* program page size DRA */
3111         sdram_set_row_attributes(&sysinfo);
3112
3113         /* Program CxBNKARC */
3114         sdram_set_bank_architecture(&sysinfo);
3115
3116         /* Program DRAM Timing and Control registers based on SPD */
3117         sdram_set_timing_and_control(&sysinfo);
3118
3119         /* On-Die Termination Adjustment */
3120         sdram_on_die_termination(&sysinfo);
3121
3122         /* Pre Jedec Initialization */
3123         sdram_pre_jedec_initialization();
3124
3125         /* Perform System Memory IO Initialization */
3126         sdram_initialize_system_memory_io(&sysinfo);
3127
3128         /* Perform System Memory IO Buffer Enable */
3129         sdram_enable_system_memory_io(&sysinfo);
3130
3131         /* Enable System Memory Clocks */
3132         sdram_enable_memory_clocks(&sysinfo);
3133
3134         if (boot_path == BOOT_PATH_NORMAL) {
3135                 /* Jedec Initialization sequence */
3136                 sdram_jedec_enable(&sysinfo);
3137         }
3138
3139         /* Program Power Management Registers */
3140         sdram_power_management(&sysinfo);
3141
3142         /* Post Jedec Init */
3143         sdram_post_jedec_initialization(&sysinfo);
3144
3145         /* Program DRAM Throttling */
3146         sdram_thermal_management();
3147
3148         /* Normal Operations */
3149         sdram_init_complete();
3150
3151         /* Program Receive Enable Timings */
3152         sdram_program_receive_enable(&sysinfo);
3153
3154         /* Enable Periodic RCOMP */
3155         sdram_enable_rcomp();
3156
3157         /* Tell ICH7 that we're done */
3158         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3159         reg8 &= ~(1 << 7);
3160         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3161
3162         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3163
3164         sdram_setup_processor_side();
3165 }
3166
3167 unsigned long get_top_of_ram(void)
3168 {
3169         /* This will not work if TSEG is in place! */
3170         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3171
3172         return (unsigned long) tom;
3173 }
3174