src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <pc80/mc146818rtc.h>
  24 #include <spd.h>
  25 #include <string.h>
  26 #include <arch/romcc_io.h>
  27 #include "raminit.h"
  28 #include "i945.h"
  29 #include <cbmem.h>
  30
  31 struct cbmem_entry *get_cbmem_toc(void) {
  32         return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
  33 }
  34
  35 /* Debugging macros. */
  36 #if CONFIG_DEBUG_RAM_SETUP
  37 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  38 #else
  39 #define PRINTK_DEBUG(x...)
  40 #endif
  41
  42 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  43
  44 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  45 #define RAM_COMMAND_NOP                 (0x1 << 16)
  46 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  47 #define RAM_COMMAND_MRS                 (0x3 << 16)
  48 #define RAM_COMMAND_EMRS                (0x4 << 16)
  49 #define RAM_COMMAND_CBR                 (0x6 << 16)
  50 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  51
  52 #define RAM_EMRS_1                      (0x0 << 21)
  53 #define RAM_EMRS_2                      (0x1 << 21)
  54 #define RAM_EMRS_3                      (0x2 << 21)
  55
  56 static inline int spd_read_byte(unsigned device, unsigned address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 static __attribute__((noinline)) void do_ram_command(u32 command)
  62 {
  63         u32 reg32;
  64
  65         reg32 = MCHBAR32(DCC);
  66         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  67         reg32 |= command;
  68
  69         /* Also set Init Complete */
  70         if (command == RAM_COMMAND_NORMAL)
  71                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  72
  73         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  74
  75         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  76
  77         PRINTK_DEBUG("...done\n");
  78
  79         udelay(1);
  80 }
  81
  82 static void ram_read32(u32 offset)
  83 {
  84         PRINTK_DEBUG("   ram read: %08x\n", offset);
  85
  86         read32(offset);
  87 }
  88
  89 #if CONFIG_DEBUG_RAM_SETUP
  90 static void sdram_dump_mchbar_registers(void)
  91 {
  92         int i;
  93         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  94
  95         for (i=0; i<0xfff; i+=4) {
  96                 if (MCHBAR32(i) == 0)
  97                         continue;
  98                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  99         }
 100 }
 101 #endif
 102
 103 static int memclk(void)
 104 {
 105         int offset = 0;
 106 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 107         offset++;
 108 #endif
 109         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
 110         case 1: return 400;
 111         case 2: return 533;
 112         case 3: return 667;
 113         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 114         }
 115         return -1;
 116 }
 117
 118 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 119 static u16 fsbclk(void)
 120 {
 121         switch (MCHBAR32(CLKCFG) & 7) {
 122         case 0: return 400;
 123         case 1: return 533;
 124         case 3: return 667;
 125         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 126         }
 127         return 0xffff;
 128 }
 129 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 130 static u16 fsbclk(void)
 131 {
 132         switch (MCHBAR32(CLKCFG) & 7) {
 133         case 0: return 1066;
 134         case 1: return 533;
 135         case 2: return 800;
 136         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 137         }
 138         return 0xffff;
 139 }
 140 #endif
 141
 142 static int sdram_capabilities_max_supported_memory_frequency(void)
 143 {
 144         u32 reg32;
 145
 146 #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
 147         return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 148 #endif
 149
 150         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 151         reg32 &= (7 << 0);
 152
 153         switch (reg32) {
 154         case 4: return 400;
 155         case 3: return 533;
 156         case 2: return 667;
 157         }
 158         /* Newer revisions of this chipset rather support faster memory clocks,
 159          * so if it's a reserved value, return the fastest memory clock that we
 160          * know of and can handle
 161          */
 162         return 667;
 163 }
 164
 165 /**
 166  * @brief determine whether chipset is capable of dual channel interleaved mode
 167  *
 168  * @return 1 if interleaving is supported, 0 otherwise
 169  */
 170 static int sdram_capabilities_interleave(void)
 171 {
 172         u32 reg32;
 173
 174         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 175         reg32 >>= 25;
 176         reg32 &= 1;
 177
 178         return (!reg32);
 179 }
 180
 181 /**
 182  * @brief determine whether chipset is capable of two memory channels
 183  *
 184  * @return 1 if dual channel operation is supported, 0 otherwise
 185  */
 186 static int sdram_capabilities_dual_channel(void)
 187 {
 188         u32 reg32;
 189
 190         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 191         reg32 >>= 24;
 192         reg32 &= 1;
 193
 194         return (!reg32);
 195 }
 196
 197 static int sdram_capabilities_enhanced_addressing_xor(void)
 198 {
 199         u8 reg8;
 200
 201         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 202         reg8 &= (1 << 7);
 203
 204         return (!reg8);
 205 }
 206
 207 static int sdram_capabilities_two_dimms_per_channel(void)
 208 {
 209         u8 reg8;
 210
 211         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 212         reg8 &= (1 << 0);
 213
 214         return (reg8 != 0);
 215 }
 216
 217 // TODO check if we ever need this function
 218 #if 0
 219 static int sdram_capabilities_MEM4G_disable(void)
 220 {
 221         u8 reg8;
 222
 223         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 224         reg8 &= (1 << 0);
 225
 226         return (reg8 != 0);
 227 }
 228 #endif
 229
 230 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 231 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 232 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 233 #define GFX_FREQUENCY_CAP_ALL           0x00
 234
 235 static int sdram_capabilities_core_frequencies(void)
 236 {
 237         u8 reg8;
 238
 239         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 240         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 241         reg8 >>= 1;
 242
 243         return (reg8);
 244 }
 245
 246 static void sdram_detect_errors(struct sys_info *sysinfo)
 247 {
 248         u8 reg8;
 249         u8 do_reset = 0;
 250
 251         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 252
 253         if (reg8 & ((1<<7)|(1<<2))) {
 254                 if (reg8 & (1<<2)) {
 255                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 256                         /* Write back clears bit 2 */
 257                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 258                         do_reset = 1;
 259
 260                 }
 261
 262                 if (reg8 & (1<<7)) {
 263                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 264                         reg8 &= ~(1<<7);
 265                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 266                         do_reset = 1;
 267                 }
 268
 269                 /* Set SLP_S3# Assertion Stretch Enable */
 270                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 271                 reg8 |= (1 << 3);
 272                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 273
 274                 if (do_reset) {
 275                         printk(BIOS_DEBUG, "Reset required.\n");
 276                         outb(0x00, 0xcf9);
 277                         outb(0x0e, 0xcf9);
 278                         for (;;) asm("hlt"); /* Wait for reset! */
 279                 }
 280         }
 281
 282         /* Set DRAM initialization bit in ICH7 */
 283         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 284         reg8 |= (1<<7);
 285         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 286
 287         /* clear self refresh if not wake-up from suspend */
 288         if (sysinfo->boot_path != 2) {
 289                 MCHBAR8(0xf14) |= 3;
 290         } else {
 291                 /* Validate self refresh config */
 292                 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
 293                      (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
 294                     !(MCHBAR8(0xf14) & (1<<0))) {
 295                         do_reset = 1;
 296                 }
 297                 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
 298                      (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
 299                     !(MCHBAR8(0xf14) & (1<<1))) {
 300                         do_reset = 1;
 301                 }
 302         }
 303
 304         if (do_reset) {
 305                 printk(BIOS_DEBUG, "Reset required.\n");
 306                 outb(0x00, 0xcf9);
 307                 outb(0x0e, 0xcf9);
 308                 for (;;) asm("hlt"); /* Wait for reset! */
 309         }
 310 }
 311
 312 /**
 313  * @brief Get generic DIMM parameters.
 314  * @param sysinfo Central memory controller information structure
 315  *
 316  * This function gathers several pieces of information for each system DIMM:
 317  *  o DIMM width (x8 / x16)
 318  *  o DIMM sides (single sided / dual sided)
 319  *
 320  *  Also, some non-supported scenarios are detected.
 321  */
 322
 323 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 324 {
 325         u32 dimm_mask = 0;
 326         int i;
 327
 328         /**
 329          * i945 supports two DIMMs, in two configurations:
 330          *
 331          * - single channel with two DIMMs
 332          * - dual channel with one DIMM per channel
 333          *
 334          * In practice dual channel mainboards have their SPD at 0x50/0x52
 335          * whereas single channel configurations have their SPD at 0x50/0x51.
 336          *
 337          * The capability register knows a lot about the channel configuration
 338          * but for now we stick with the information we gather via SPD.
 339          */
 340
 341         if (sdram_capabilities_dual_channel()) {
 342                 sysinfo->dual_channel = 1;
 343                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 344         } else {
 345                 sysinfo->dual_channel = 0;
 346                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 347         }
 348
 349         /**
 350          * Since we only support two DIMMs in total, there is a limited number
 351          * of combinations. This function returns the type of DIMMs.
 352          * return value:
 353          *   [0:7]  lower DIMM population
 354          *   [8-15] higher DIMM population
 355          *   [16]   dual channel?
 356          *
 357          * There are 5 different possible populations for a DIMM socket:
 358          * 1. x16 double sided (X16DS)
 359          * 2. x8 double sided  (X8DS)
 360          * 3. x16 single sided (X16SS)
 361          * 4. x8 double stacked (X8DDS)
 362          * 5. not populated (NC)
 363          *
 364          * For the return value we start counting at zero.
 365          *
 366          */
 367
 368         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 369                 u8 reg8, device = DIMM0 + i;
 370
 371                 /* Initialize the socket information with a sane value */
 372                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 373
 374                 /* Dual Channel not supported, but Channel 1? Bail out */
 375                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 376                         continue;
 377
 378                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 379                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 380                         continue;
 381
 382                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 383
 384                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 385                         printk(BIOS_DEBUG, "N/A\n");
 386                         continue;
 387                 }
 388
 389                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 390                 if (reg8 == ERROR_SCHEME_ECC)
 391                         die("Error: ECC memory not supported by this chipset\n");
 392
 393                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 394                 if (reg8 & MODULE_BUFFERED)
 395                         die("Error: Buffered memory not supported by this chipset\n");
 396                 if (reg8 & MODULE_REGISTERED)
 397                         die("Error: Registered memory not supported by this chipset\n");
 398
 399                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 400                 case 0x08:
 401                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 402                         case 1:
 403                                 printk(BIOS_DEBUG, "x8DDS\n");
 404                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 405                                 break;
 406                         case 0:
 407                                 printk(BIOS_DEBUG, "x8DS\n");
 408                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 409                                 break;
 410                         default:
 411                                 printk(BIOS_DEBUG, "Unsupported.\n");
 412                         }
 413                         break;
 414                 case 0x10:
 415                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 416                         case 1:
 417                                 printk(BIOS_DEBUG, "x16DS\n");
 418                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 419                                 break;
 420                         case 0:
 421                                 printk(BIOS_DEBUG, "x16SS\n");
 422                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 423                                 break;
 424                         default:
 425                                 printk(BIOS_DEBUG, "Unsupported.\n");
 426                         }
 427                         break;
 428                 default:
 429                         die("Unsupported DDR-II memory width.\n");
 430                 }
 431
 432                 dimm_mask |= (1 << i);
 433         }
 434
 435         if (!dimm_mask) {
 436                 die("No memory installed.\n");
 437         }
 438
 439         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 440                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 441         }
 442 }
 443
 444 /**
 445  * @brief determine if any DIMMs are stacked
 446  *
 447  * @param sysinfo central sysinfo data structure.
 448  */
 449 static void sdram_verify_package_type(struct sys_info * sysinfo)
 450 {
 451         int i;
 452
 453         /* Assume no stacked DIMMs are available until we find one */
 454         sysinfo->package = 0;
 455         for (i=0; i<2*DIMM_SOCKETS; i++) {
 456                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 457                         continue;
 458
 459                 /* Is the current DIMM a stacked DIMM? */
 460                 if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 461                         sysinfo->package = 1;
 462         }
 463 }
 464
 465 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 466 {
 467         int i;
 468         u8 cas_mask;
 469
 470         /* Setup CAS mask with all supported CAS Latencies */
 471         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 472                    SPD_CAS_LATENCY_DDR2_4 |
 473                    SPD_CAS_LATENCY_DDR2_5;
 474
 475         for (i=0; i<2*DIMM_SOCKETS; i++) {
 476                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 477                         cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 478         }
 479
 480         if(!cas_mask) {
 481                 die("No DDR-II modules with accepted CAS latencies found.\n");
 482         }
 483
 484         return cas_mask;
 485 }
 486
 487 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 488 {
 489         int i, j, idx;
 490         int lowest_common_cas = 0;
 491         int max_ram_speed = 0;
 492
 493         const u8 ddr2_speeds_table[] = {
 494                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 495                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 496                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 497         };
 498
 499         const u8 spd_lookup_table[] = {
 500                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 501                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 502                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 503         };
 504
 505         switch (sdram_capabilities_max_supported_memory_frequency()) {
 506         case 400: max_ram_speed = 0; break;
 507         case 533: max_ram_speed = 1; break;
 508         case 667: max_ram_speed = 2; break;
 509         }
 510
 511         if (fsbclk() == 533)
 512                 max_ram_speed = 1;
 513
 514         sysinfo->memory_frequency = 0;
 515         sysinfo->cas = 0;
 516
 517         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 518                 lowest_common_cas = 3;
 519         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 520                 lowest_common_cas = 4;
 521         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 522                 lowest_common_cas = 5;
 523         }
 524         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 525
 526         for (j = max_ram_speed; j>=0; j--) {
 527                 int freq_cas_mask = cas_mask;
 528
 529                 PRINTK_DEBUG("Probing Speed %d\n", j);
 530                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 531                         int current_cas_mask;
 532
 533                         PRINTK_DEBUG("  DIMM: %d\n", i);
 534                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 535                                 continue;
 536                         }
 537
 538                         current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 539
 540                         while (current_cas_mask) {
 541                                 int highest_supported_cas = 0, current_cas = 0;
 542                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 543                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 544                                         highest_supported_cas = 5;
 545                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 546                                         highest_supported_cas = 4;
 547                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 548                                         highest_supported_cas = 3;
 549                                 } else {
 550                                         die("Invalid max. CAS.\n");
 551                                 }
 552                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 553                                         current_cas = 3;
 554                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 555                                         current_cas = 4;
 556                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 557                                         current_cas = 5;
 558                                 } else {
 559                                         die("Invalid CAS.\n");
 560                                 }
 561
 562                                 idx = highest_supported_cas - current_cas;
 563                                 PRINTK_DEBUG("idx=%d, ", idx);
 564                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
 565                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
 566
 567                                 if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 568                                                 spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 569                                         PRINTK_DEBUG(":    OK\n");
 570                                         break;
 571                                 }
 572
 573                                 PRINTK_DEBUG(":    Not fast enough!\n");
 574
 575                                 current_cas_mask &= ~(1 << (current_cas));
 576                         }
 577
 578                         freq_cas_mask &= current_cas_mask;
 579                         if (!current_cas_mask) {
 580                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 581                                 break;
 582                         }
 583                 }
 584                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 585                 if (freq_cas_mask) {
 586                         switch (j) {
 587                         case 0: sysinfo->memory_frequency = 400; break;
 588                         case 1: sysinfo->memory_frequency = 533; break;
 589                         case 2: sysinfo->memory_frequency = 667; break;
 590                         }
 591                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 592                                 sysinfo->cas = 3;
 593                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 594                                 sysinfo->cas = 4;
 595                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 596                                 sysinfo->cas = 5;
 597                         }
 598                         break;
 599                 }
 600         }
 601
 602         if (sysinfo->memory_frequency && sysinfo->cas) {
 603                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 604                                 sysinfo->memory_frequency, sysinfo->cas);
 605         } else {
 606                 die("Could not find common memory frequency and CAS\n");
 607         }
 608 }
 609
 610 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 611 {
 612         int i;
 613         int tRAS_time;
 614         int tRAS_cycles;
 615         int freq_multiplier = 0;
 616
 617         switch (sysinfo->memory_frequency) {
 618         case 400: freq_multiplier = 0x14; break; /* 5ns */
 619         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 620         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 621         }
 622
 623         tRAS_cycles = 4; /* 4 clocks minimum */
 624         tRAS_time = tRAS_cycles * freq_multiplier;
 625
 626         for (i=0; i<2*DIMM_SOCKETS; i++) {
 627                 u8 reg8;
 628
 629                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 630                         continue;
 631
 632                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 633                 if (!reg8) {
 634                         die("Invalid tRAS value.\n");
 635                 }
 636
 637                 while ((tRAS_time >> 2) < reg8) {
 638                         tRAS_time += freq_multiplier;
 639                         tRAS_cycles++;
 640                 }
 641         }
 642         if(tRAS_cycles > 0x18) {
 643                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 644         }
 645
 646         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 647         sysinfo->tras = tRAS_cycles;
 648 }
 649
 650 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 651 {
 652         int i;
 653         int tRP_time;
 654         int tRP_cycles;
 655         int freq_multiplier = 0;
 656
 657         switch (sysinfo->memory_frequency) {
 658         case 400: freq_multiplier = 0x14; break; /* 5ns */
 659         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 660         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 661         }
 662
 663         tRP_cycles = 2; /* 2 clocks minimum */
 664         tRP_time = tRP_cycles * freq_multiplier;
 665
 666         for (i=0; i<2*DIMM_SOCKETS; i++) {
 667                 u8 reg8;
 668
 669                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 670                         continue;
 671
 672                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
 673                 if (!reg8) {
 674                         die("Invalid tRP value.\n");
 675                 }
 676
 677                 while (tRP_time < reg8) {
 678                         tRP_time += freq_multiplier;
 679                         tRP_cycles++;
 680                 }
 681         }
 682
 683         if(tRP_cycles > 6) {
 684                 die("DDR-II Module does not support this frequency (tRP error)\n");
 685         }
 686
 687         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 688         sysinfo->trp = tRP_cycles;
 689 }
 690
 691 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 692 {
 693         int i;
 694         int tRCD_time;
 695         int tRCD_cycles;
 696         int freq_multiplier = 0;
 697
 698         switch (sysinfo->memory_frequency) {
 699         case 400: freq_multiplier = 0x14; break; /* 5ns */
 700         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 701         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 702         }
 703
 704         tRCD_cycles = 2; /* 2 clocks minimum */
 705         tRCD_time = tRCD_cycles * freq_multiplier;
 706
 707         for (i=0; i<2*DIMM_SOCKETS; i++) {
 708                 u8 reg8;
 709
 710                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 711                         continue;
 712
 713                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
 714                 if (!reg8) {
 715                         die("Invalid tRCD value.\n");
 716                 }
 717
 718                 while (tRCD_time < reg8) {
 719                         tRCD_time += freq_multiplier;
 720                         tRCD_cycles++;
 721                 }
 722         }
 723         if(tRCD_cycles > 6) {
 724                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 725         }
 726
 727         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 728         sysinfo->trcd = tRCD_cycles;
 729 }
 730
 731 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 732 {
 733         int i;
 734         int tWR_time;
 735         int tWR_cycles;
 736         int freq_multiplier = 0;
 737
 738         switch (sysinfo->memory_frequency) {
 739         case 400: freq_multiplier = 0x14; break; /* 5ns */
 740         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 741         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 742         }
 743
 744         tWR_cycles = 2; /* 2 clocks minimum */
 745         tWR_time = tWR_cycles * freq_multiplier;
 746
 747         for (i=0; i<2*DIMM_SOCKETS; i++) {
 748                 u8 reg8;
 749
 750                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 751                         continue;
 752
 753                 reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
 754                 if (!reg8) {
 755                         die("Invalid tWR value.\n");
 756                 }
 757
 758                 while (tWR_time < reg8) {
 759                         tWR_time += freq_multiplier;
 760                         tWR_cycles++;
 761                 }
 762         }
 763         if(tWR_cycles > 5) {
 764                 die("DDR-II Module does not support this frequency (tWR error)\n");
 765         }
 766
 767         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 768         sysinfo->twr = tWR_cycles;
 769 }
 770
 771 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 772 {
 773         int i, index = 0;
 774
 775         const u8 tRFC_cycles[] = {
 776              /* 75 105 127.5 */
 777                 15, 21, 26,     /* DDR2-400 */
 778                 20, 28, 34,     /* DDR2-533 */
 779                 25, 35, 43      /* DDR2-667 */
 780         };
 781
 782         for (i=0; i<2*DIMM_SOCKETS; i++) {
 783                 u8 reg8;
 784
 785                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 786                         continue;
 787
 788                 reg8 = sysinfo->banksize[i*2];
 789                 switch (reg8) {
 790                 case 0x04: reg8 = 0; break;
 791                 case 0x08: reg8 = 1; break;
 792                 case 0x10: reg8 = 2; break;
 793                 case 0x20: reg8 = 3; break;
 794                 }
 795
 796                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 797                         reg8++;
 798
 799                 if (reg8 > 3) {
 800                         /* Can this happen? Go back to 127.5ns just to be sure
 801                          * we don't run out of the array. This may be wrong
 802                          */
 803                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 804                         reg8 = 3;
 805                 }
 806
 807                 if (reg8 > index)
 808                         index = reg8;
 809
 810         }
 811         index--;
 812         switch (sysinfo->memory_frequency) {
 813         case 667: index += 3; /* Fallthrough */
 814         case 533: index += 3; /* Fallthrough */
 815         case 400: break;
 816         }
 817
 818         sysinfo->trfc = tRFC_cycles[index];
 819         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 820 }
 821
 822 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 823 {
 824         int i;
 825
 826         sysinfo->refresh = 0;
 827
 828         for (i=0; i<2*DIMM_SOCKETS; i++) {
 829                 int refresh;
 830
 831                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 832                         continue;
 833
 834                 refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
 835
 836                 /* 15.6us */
 837                 if (!refresh)
 838                         continue;
 839
 840                 /* Refresh is slower than 15.6us, use 15.6us */
 841                 if (refresh > 2)
 842                         continue;
 843
 844                 if (refresh == 2) {
 845                         sysinfo->refresh = 1;
 846                         break;
 847                 }
 848
 849                 die("DDR-II module has unsupported refresh value\n");
 850         }
 851         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 852 }
 853
 854 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 855 {
 856         int i;
 857
 858         for (i=0; i<2*DIMM_SOCKETS; i++) {
 859                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 860                         continue;
 861
 862                 if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 863                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 864         }
 865 }
 866
 867 static void sdram_program_dram_width(struct sys_info * sysinfo)
 868 {
 869         u16 c0dramw=0, c1dramw=0;
 870         int idx;
 871
 872         if (sysinfo->dual_channel)
 873                 idx = 2;
 874         else
 875                 idx = 1;
 876
 877         switch (sysinfo->dimm[0]) {
 878         case 0: c0dramw = 0x0000; break; /* x16DS */
 879         case 1: c0dramw = 0x0001; break; /* x8DS */
 880         case 2: c0dramw = 0x0000; break; /* x16SS */
 881         case 3: c0dramw = 0x0005; break; /* x8DDS */
 882         case 4: c0dramw = 0x0000; break; /* NC */
 883         }
 884
 885         switch (sysinfo->dimm[idx]) {
 886         case 0: c1dramw = 0x0000; break; /* x16DS */
 887         case 1: c1dramw = 0x0010; break; /* x8DS */
 888         case 2: c1dramw = 0x0000; break; /* x16SS */
 889         case 3: c1dramw = 0x0050; break; /* x8DDS */
 890         case 4: c1dramw = 0x0000; break; /* NC */
 891         }
 892
 893         if ( !sdram_capabilities_dual_channel() ) {
 894                 /* Single Channel */
 895                 c0dramw |= c1dramw;
 896                 c1dramw = 0;
 897         }
 898
 899         MCHBAR16(C0DRAMW) = c0dramw;
 900         MCHBAR16(C1DRAMW) = c1dramw;
 901 }
 902
 903 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 904 {
 905         int i;
 906
 907         for (i=0; i<16; i++)
 908                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 909 }
 910
 911 static const u32 dq2030[] = {
 912         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 913         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 914         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 915         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 916 };
 917
 918 static const u32 dq2330[] = {
 919         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 920         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 921         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 922         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 923 };
 924
 925 static const u32 cmd2710[] = {
 926         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 927         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 928         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 929         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 930 };
 931
 932 static const u32 cmd3210[] = {
 933         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 934         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 935         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 936         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 937 };
 938
 939 static const u32 clk2030[] = {
 940         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 941         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 942         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 943         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 944 };
 945
 946 static const u32 ctl3215[] = {
 947         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 948         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 949         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 950         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 951 };
 952
 953 static const u32 ctl3220[] = {
 954         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 955         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 956         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 957         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 958 };
 959
 960 static const u32 nc[] = {
 961         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 962         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 963         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 964         0x00000000, 0x00000000, 0x00000000, 0x00000000
 965 };
 966
 967 enum {
 968         DQ2030,
 969         DQ2330,
 970         CMD2710,
 971         CMD3210,
 972         CLK2030,
 973         CTL3215,
 974         CTL3220,
 975         NC,
 976 };
 977
 978 static const u8 dual_channel_slew_group_lookup[] = {
 979         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 980         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 981         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 982         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 983         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 984
 985         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 986         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 987         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 988         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 989         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 990
 991         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 992         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 993         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 994         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 995         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 996
 997         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 998         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 999         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1000         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
1001         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1002
1003         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1004         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1005         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1006         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
1007 };
1008
1009 static const u8 single_channel_slew_group_lookup[] = {
1010         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1011         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1012         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1013         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1014         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1015
1016         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1017         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1018         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1019         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1020         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1021
1022         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1023         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1024         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1025         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1026         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1027
1028         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1029         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1030         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1031         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1032         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1033
1034         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1035         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1036         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1037         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
1038 };
1039
1040 static const u32 *slew_group_lookup(int dual_channel, int index)
1041 {
1042         const u8 *slew_group;
1043         /* Dual Channel needs different tables. */
1044         if (dual_channel)
1045                 slew_group   = dual_channel_slew_group_lookup;
1046         else
1047                 slew_group   = single_channel_slew_group_lookup;
1048
1049         switch (slew_group[index]) {
1050         case DQ2030:    return dq2030;
1051         case DQ2330:    return dq2330;
1052         case CMD2710:   return cmd2710;
1053         case CMD3210:   return cmd3210;
1054         case CLK2030:   return clk2030;
1055         case CTL3215:   return ctl3215;
1056         case CTL3220:   return ctl3220;
1057         case NC:        return nc;
1058         }
1059
1060         return nc;
1061 }
1062
1063 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
1064 /* Strength multiplier tables */
1065 static const u8 dual_channel_strength_multiplier[] = {
1066         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1067         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1068         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1069         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1070         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1071         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1072         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1073         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1074         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1075         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1076         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1077         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1078         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1079         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1080         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1081         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1082         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1083         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1084         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1085         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1086         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1087         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1088         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1089         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1090 };
1091
1092 static const u8 single_channel_strength_multiplier[] = {
1093         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1094         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1095         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1096         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1097         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1098         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1099         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1100         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1101         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1102         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1103         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1104         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1105         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1106         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1107         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1108         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1109         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1110         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1111         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1112         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1113         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1114         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1115         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1116         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1117 };
1118 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
1119 static const u8 dual_channel_strength_multiplier[] = {
1120         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1121         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1122         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1123         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1124         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1125         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1126         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1127         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1128         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1129         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1130         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1131         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1132         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1133         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1134         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1135         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1136         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1137         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1138         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1139         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1141         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1142         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1143         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1144 };
1145
1146 static const u8 single_channel_strength_multiplier[] = {
1147         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1148         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1149         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1151         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1152         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1153         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1154         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1155         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1156         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1157         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1158         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1159         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1160         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1161         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1162         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1163         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1164         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1165         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1166         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1167         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1168         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1169         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1170         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1171 };
1172 #endif
1173
1174 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1175 {
1176         const u8 * strength_multiplier;
1177         int idx, dual_channel;
1178
1179         /* Set Strength Multipliers */
1180
1181         /* Dual Channel needs different tables. */
1182         if (sdram_capabilities_dual_channel()) {
1183                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1184                 strength_multiplier = dual_channel_strength_multiplier;
1185                 dual_channel = 1;
1186                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1187         } else {
1188                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1189                 strength_multiplier = single_channel_strength_multiplier;
1190                 dual_channel = 0;
1191                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1192         }
1193
1194         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1195
1196         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1197         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1198         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1199         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1200         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1201         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1202         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1203         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1204
1205         /* Channel 0 */
1206         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1207         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1208         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1209
1210                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1211         } else {
1212                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1213         }
1214         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1215         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1216         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1217
1218         /* Channel 1 */
1219         if (sysinfo->dual_channel) {
1220                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1221                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1222         } else {
1223                 sdram_write_slew_rates(G7SRPUT, nc);
1224                 sdram_write_slew_rates(G8SRPUT, nc);
1225         }
1226 }
1227
1228 static void sdram_enable_rcomp(void)
1229 {
1230         u32 reg32;
1231         /* Enable Global Periodic RCOMP */
1232         udelay(300);
1233         reg32 = MCHBAR32(GBRCOMPCTL);
1234         reg32 &= ~(1 << 23);
1235         MCHBAR32(GBRCOMPCTL) = reg32;
1236 }
1237
1238 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1239 {
1240         u32 chan0dll = 0, chan1dll = 0;
1241         int i;
1242
1243         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1244
1245         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1246         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1247
1248         /* We drive both channels with the same speed */
1249         switch (sysinfo->memory_frequency) {
1250         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1251         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1252         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1253         }
1254
1255         for (i=0; i < 4; i++) {
1256                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1257                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1258                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1259                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1260         }
1261 }
1262
1263 static void sdram_force_rcomp(void)
1264 {
1265         u32 reg32;
1266         u8 reg8;
1267
1268         reg32 = MCHBAR32(ODTC);
1269         reg32 |= (1 << 28);
1270         MCHBAR32(ODTC) = reg32;
1271
1272         reg32 = MCHBAR32(SMSRCTL);
1273         reg32 |= (1 << 0);
1274         MCHBAR32(SMSRCTL) = reg32;
1275
1276         /* Start initial RCOMP */
1277         reg32 = MCHBAR32(GBRCOMPCTL);
1278         reg32 |= (1 << 8);
1279         MCHBAR32(GBRCOMPCTL) = reg32;
1280
1281         reg8 = i945_silicon_revision();
1282         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1283
1284                 reg32 = MCHBAR32(GBRCOMPCTL);
1285                 reg32 |= (3 << 5);
1286                 MCHBAR32(GBRCOMPCTL) = reg32;
1287         }
1288 }
1289
1290 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1291 {
1292         u8 reg8;
1293         u32 reg32;
1294
1295         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1296         /* Enable Data Half Clock Pushout */
1297         reg8 = MCHBAR8(C0HCTC);
1298         reg8 &= ~0x1f;
1299         reg8 |= ( 1 << 0);
1300         MCHBAR8(C0HCTC) = reg8;
1301
1302         reg8 = MCHBAR8(C1HCTC);
1303         reg8 &= ~0x1f;
1304         reg8 |= ( 1 << 0);
1305         MCHBAR8(C1HCTC) = reg8;
1306
1307         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1308         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1309
1310         MCHBAR8(C0WDLLCMC) = 0;
1311         MCHBAR8(C1WDLLCMC) = 0;
1312
1313         /* Program RCOMP Settings */
1314         sdram_program_dram_width(sysinfo);
1315
1316         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1317
1318         /* Indicate that RCOMP programming is done */
1319         reg32 = MCHBAR32(GBRCOMPCTL);
1320         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1321         reg32 |= (3 << 27) | (3 << 0);
1322         MCHBAR32(GBRCOMPCTL) = reg32;
1323
1324         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1325
1326         /* Program DLL Timings */
1327         sdram_program_dll_timings(sysinfo);
1328
1329         /* Force RCOMP cycle */
1330         sdram_force_rcomp();
1331 }
1332
1333 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1334 {
1335         u32 reg32;
1336
1337         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1338
1339         reg32 = MCHBAR32(RCVENMT);
1340         reg32 &= ~(0x3f << 6);
1341         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1342
1343         reg32 |= (1 << 11) | (1 << 9);
1344         MCHBAR32(RCVENMT) = reg32;
1345
1346         reg32 = MCHBAR32(DRTST);
1347         reg32 |= (1 << 3) | (1 << 2);
1348         MCHBAR32(DRTST) = reg32;
1349
1350         reg32 = MCHBAR32(DRTST);
1351         reg32 |= (1 << 6) | (1 << 4);
1352         MCHBAR32(DRTST) = reg32;
1353
1354         asm volatile ("nop; nop;" ::: "memory");
1355
1356         reg32 = MCHBAR32(DRTST);
1357
1358         /* Is channel 0 populated? */
1359         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1360                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1361                 reg32 |= (1 << 7) | (1 << 5);
1362         else
1363                 reg32 |= (1 << 31);
1364
1365         /* Is channel 1 populated? */
1366         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1367                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1368                 reg32 |= (1 << 9) | (1 << 8);
1369         else
1370                 reg32 |= (1 << 30);
1371
1372         MCHBAR32(DRTST) = reg32;
1373
1374         /* Activate DRAM Channel IO Buffers */
1375         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1376                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1377                 reg32 = MCHBAR32(C0DRC1);
1378                 reg32 |= (1 << 8);
1379                 MCHBAR32(C0DRC1) = reg32;
1380         }
1381         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1382                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1383                 reg32 = MCHBAR32(C1DRC1);
1384                 reg32 |= (1 << 8);
1385                 MCHBAR32(C1DRC1) = reg32;
1386         }
1387 }
1388
1389 struct dimm_size {
1390         unsigned long side1;
1391         unsigned long side2;
1392 };
1393
1394 static struct dimm_size sdram_get_dimm_size(u16 device)
1395 {
1396         /* Calculate the log base 2 size of a DIMM in bits */
1397         struct dimm_size sz;
1398         int value, low, rows, columns;
1399
1400         sz.side1 = 0;
1401         sz.side2 = 0;
1402
1403         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1404         if (rows < 0) goto hw_err;
1405         if ((rows & 0xf) == 0) goto val_err;
1406         sz.side1 += rows & 0xf;
1407
1408         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1409         if (columns < 0) goto hw_err;
1410         if ((columns & 0xf) == 0) goto val_err;
1411         sz.side1 += columns & 0xf;
1412
1413         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1414         if (value < 0) goto hw_err;
1415         if ((value & 0xff) == 0) goto val_err;
1416         sz.side1 += log2(value & 0xff);
1417
1418         /* Get the module data width and convert it to a power of two */
1419         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1420         if (value < 0) goto hw_err;
1421         value &= 0xff;
1422         value <<= 8;
1423
1424         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1425         if (low < 0) goto hw_err;
1426         value = value | (low & 0xff);
1427         if ((value != 72) && (value != 64)) goto val_err;
1428         sz.side1 += log2(value);
1429
1430         /* side 2 */
1431         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1432
1433         if (value < 0) goto hw_err;
1434         value &= 7;
1435         value++;
1436         if (value == 1) goto out;
1437         if (value != 2) goto val_err;
1438
1439         /* Start with the symmetrical case */
1440         sz.side2 = sz.side1;
1441
1442         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1443
1444         /* Don't die here, I have not come across any of these to test what
1445          * actually happens.
1446          */
1447         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1448
1449         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1450         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1451
1452         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1453         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1454
1455         goto out;
1456
1457  val_err:
1458         die("Bad SPD value\n");
1459  hw_err:
1460         /* If a hardware error occurs the spd rom probably does not exist.
1461          * In this case report that there is no memory
1462          */
1463         sz.side1 = 0;
1464         sz.side2 = 0;
1465  out:
1466         return sz;
1467 }
1468
1469 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1470 {
1471         int i;
1472
1473         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1474                 struct dimm_size sz;
1475
1476                 sysinfo->banksize[i * 2] = 0;
1477                 sysinfo->banksize[(i * 2) + 1] = 0;
1478
1479                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1480                         continue;
1481
1482                 sz = sdram_get_dimm_size(DIMM0 + i);
1483
1484                 sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1485
1486                 if (sz.side1 < 30)
1487                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1488
1489                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1490
1491                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1492
1493                 if (!sz.side2)
1494                         continue;
1495
1496                 /* If there is a second side, it has to have at least 128M, too */
1497                 if (sz.side2 < 30)
1498                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1499
1500                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1501
1502                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1503         }
1504 }
1505
1506 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1507 {
1508         int i;
1509         int cum0, cum1, tolud, tom;
1510
1511         printk(BIOS_DEBUG, "Setting RAM size... \n");
1512
1513         cum0 = 0;
1514         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1515                 cum0 += sysinfo->banksize[i];
1516                 MCHBAR8(C0DRB0+i) = cum0;
1517         }
1518
1519         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1520         cum1 = cum0;
1521
1522         /* Exception: Interleaved starts from the beginning */
1523         if (sysinfo->interleaved)
1524                 cum1 = 0;
1525
1526 #if 0
1527         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1528         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1529                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1530                 cum1 = 0;
1531 #endif
1532
1533         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1534                 cum1 += sysinfo->banksize[i + 4];
1535                 MCHBAR8(C1DRB0+i) = cum1;
1536         }
1537
1538         /* Set TOLUD Top Of Low Usable DRAM */
1539         if (sysinfo->interleaved)
1540                 tolud = (cum0 + cum1) << 1;
1541         else
1542                 tolud = (cum1 ? cum1 : cum0)  << 1;
1543
1544         /* The TOM register has a different format */
1545         tom = tolud >> 3;
1546
1547         /* Limit the value of TOLUD to leave some space for PCI memory. */
1548         if (tolud > 0xd0)
1549                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1550
1551         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1552
1553         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1554         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1555         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1556
1557         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1558
1559         return 0;
1560 }
1561
1562 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1563 {
1564         int i, value;
1565         u16 dra0=0, dra1=0, dra = 0;
1566
1567         printk(BIOS_DEBUG, "Setting row attributes... \n");
1568         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1569                 u16 device;
1570                 u8 columnsrows;
1571
1572                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1573                         continue;
1574                 }
1575
1576                 device = DIMM0 + i;
1577
1578                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1579                 columnsrows = (value & 0x0f);
1580
1581                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1582                 columnsrows |= (value & 0xf) << 4;
1583
1584                 switch (columnsrows) {
1585                 case 0x9d: dra = 2; break;
1586                 case 0xad: dra = 3; break;
1587                 case 0xbd: dra = 4; break;
1588                 case 0xae: dra = 3; break;
1589                 case 0xbe: dra = 4; break;
1590                 default: die("Unsupported Rows/Columns. (DRA)");
1591                 }
1592
1593                 /* Double Sided DIMMs? */
1594                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1595                         dra = (dra << 4) | dra;
1596                 }
1597
1598                 if (i < DIMM_SOCKETS)
1599                         dra0 |= (dra << (i*8));
1600                 else
1601                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1602         }
1603
1604         MCHBAR16(C0DRA0) = dra0;
1605         MCHBAR16(C1DRA0) = dra1;
1606
1607         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1608         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1609
1610         return 0;
1611 }
1612
1613 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1614 {
1615         u32 off32;
1616         int i;
1617
1618         MCHBAR16(C1BNKARC) &= 0xff00;
1619         MCHBAR16(C0BNKARC) &= 0xff00;
1620
1621         off32 = C0BNKARC;
1622         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1623                 /* Switch to second channel */
1624                 if (i == DIMM_SOCKETS)
1625                         off32 = C1BNKARC;
1626
1627                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1628                         continue;
1629
1630                 if (sysinfo->banks[i] != 8)
1631                         continue;
1632
1633                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1634
1635                 if (i & 1)
1636                         MCHBAR16(off32) |= 0x50;
1637                 else
1638                         MCHBAR16(off32) |= 0x05;
1639         }
1640 }
1641
1642 #define REFRESH_7_8US   1
1643 #define REFRESH_15_6US  0
1644 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1645 {
1646         u32 reg32;
1647
1648         if (sysinfo->refresh == REFRESH_7_8US) {
1649                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1650         } else {
1651                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1652         }
1653
1654         MCHBAR32(C0DRC0) &= ~(7 << 8);
1655         MCHBAR32(C0DRC0) |= reg32;
1656
1657         MCHBAR32(C1DRC0) &= ~(7 << 8);
1658         MCHBAR32(C1DRC0) |= reg32;
1659 }
1660
1661 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1662 {
1663         u32 reg32;
1664         int i;
1665
1666         reg32 = MCHBAR32(C0DRC1);
1667
1668         for (i=0; i < 4; i++) {
1669                 if (sysinfo->banksize[i] == 0) {
1670                         reg32 |= (1 << (16 + i));
1671                 }
1672         }
1673
1674         reg32 |= (1 << 12);
1675
1676         reg32 |= (1 << 11);
1677         MCHBAR32(C0DRC1) = reg32;
1678
1679         /* Do we have to do this if we're in Single Channel Mode?  */
1680         reg32 = MCHBAR32(C1DRC1);
1681
1682         for (i=4; i < 8; i++) {
1683                 if (sysinfo->banksize[i] == 0) {
1684                         reg32 |= (1 << (12 + i));
1685                 }
1686         }
1687
1688         reg32 |= (1 << 12);
1689
1690         reg32 |= (1 << 11);
1691         MCHBAR32(C1DRC1) = reg32;
1692 }
1693
1694 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1695 {
1696         u32 reg32;
1697         int i;
1698
1699         reg32 = MCHBAR32(C0DRC2);
1700
1701         for (i=0; i < 4; i++) {
1702                 if (sysinfo->banksize[i] == 0) {
1703                         reg32 |= (1 << (24 + i));
1704                 }
1705         }
1706         MCHBAR32(C0DRC2) = reg32;
1707
1708         reg32 = MCHBAR32(C1DRC2);
1709
1710         for (i=4; i < 8; i++) {
1711                 if (sysinfo->banksize[i] == 0) {
1712                         reg32 |= (1 << (20 + i));
1713                 }
1714         }
1715         MCHBAR32(C1DRC2) = reg32;
1716 }
1717
1718 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1719 {
1720         u32 reg32, off32;
1721         u32 tWTR;
1722         u32 temp_drt;
1723         int i, page_size;
1724
1725         static const u8 const drt0_table[] = {
1726           /* CL 3, 4, 5 */
1727                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1728                 4, 5, 6,        /* FSB667, DDR533/400 */
1729                 4, 5, 6,        /* FSB667, DDR667 */
1730         };
1731
1732         static const u8 const cas_table[] = {
1733                 2, 1, 0, 3
1734         };
1735
1736         reg32 = MCHBAR32(C0DRC0);
1737         reg32 |= (1 << 2);      /* Burst Length 8 */
1738         reg32 &= ~( (1 << 13) | (1 << 12) );
1739         MCHBAR32(C0DRC0) = reg32;
1740
1741         reg32 = MCHBAR32(C1DRC0);
1742         reg32 |= (1 << 2);      /* Burst Length 8 */
1743         reg32 &= ~( (1 << 13) | (1 << 12) );
1744         MCHBAR32(C1DRC0) = reg32;
1745
1746         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1747                         SYSINFO_DIMM_NOT_POPULATED) {
1748                 reg32 = MCHBAR32(C0DRC0);
1749                 reg32 |= (1 << 15);
1750                 MCHBAR32(C0DRC0) = reg32;
1751         }
1752
1753         sdram_program_refresh_rate(sysinfo);
1754
1755         sdram_program_cke_tristate(sysinfo);
1756
1757         sdram_program_odt_tristate(sysinfo);
1758
1759         /* Calculate DRT0 */
1760
1761         temp_drt = 0;
1762
1763         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1764         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1765         temp_drt |= (reg32 << 28);
1766
1767         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1768         reg32 += sysinfo->trp;
1769         temp_drt |= (reg32 << 4);
1770
1771         if (sysinfo->memory_frequency == 667) {
1772                 tWTR = 3; /* 667MHz */
1773         } else {
1774                 tWTR = 2; /* 400 and 533 */
1775         }
1776
1777         /* B2B Write to Read Command Spacing */
1778         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1779         temp_drt |= (reg32 << 24);
1780
1781         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1782         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1783
1784         /* Program Write Auto Precharge to Activate */
1785         off32 = 0;
1786         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1787                 off32 += 3;
1788         }
1789         if (sysinfo->memory_frequency == 667) {
1790                 off32 += 3;
1791         }
1792         off32 += sysinfo->cas - 3;
1793         reg32 = drt0_table[off32];
1794         temp_drt |= (reg32 << 11);
1795
1796         /* Read Auto Precharge to Activate */
1797
1798         temp_drt |= (8 << 0);
1799
1800         MCHBAR32(C0DRT0) = temp_drt;
1801         MCHBAR32(C1DRT0) = temp_drt;
1802
1803         /* Calculate DRT1 */
1804
1805         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1806
1807         /* DRAM RASB Precharge */
1808         temp_drt |= (sysinfo->trp - 2) << 0;
1809
1810         /* DRAM RASB to CASB Delay */
1811         temp_drt |= (sysinfo->trcd - 2) << 4;
1812
1813         /* CASB Latency */
1814         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1815
1816         /* Refresh Cycle Time */
1817         temp_drt |= (sysinfo->trfc) << 10;
1818
1819         /* Pre-All to Activate Delay */
1820         temp_drt |= (0 << 16);
1821
1822         /* Precharge to Precharge Delay stays at 1 clock */
1823         temp_drt |= (0 << 18);
1824
1825         /* Activate to Precharge Delay */
1826         temp_drt |= (sysinfo->tras << 19);
1827
1828         /* Read to Precharge (tRTP) */
1829         if (sysinfo->memory_frequency == 667) {
1830                 temp_drt |= (1 << 28);
1831         } else {
1832                 temp_drt |= (0 << 28);
1833         }
1834
1835         /* Determine page size */
1836         reg32 = 0;
1837         page_size = 1; /* Default: 1k pagesize */
1838         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1839                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1840                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1841                         page_size = 2; /* 2k pagesize */
1842         }
1843
1844         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1845                 reg32 = 1;
1846         }
1847         if (sysinfo->memory_frequency == 667) {
1848                 reg32 = page_size;
1849         }
1850
1851         temp_drt |= (reg32 << 30);
1852
1853         MCHBAR32(C0DRT1) = temp_drt;
1854         MCHBAR32(C1DRT1) = temp_drt;
1855
1856         /* Program DRT2 */
1857         reg32 = MCHBAR32(C0DRT2);
1858         reg32 &= ~(1 << 8);
1859         MCHBAR32(C0DRT2) = reg32;
1860
1861         reg32 = MCHBAR32(C1DRT2);
1862         reg32 &= ~(1 << 8);
1863         MCHBAR32(C1DRT2) = reg32;
1864
1865         /* Calculate DRT3 */
1866         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1867
1868         /* Get old tRFC value */
1869         reg32 = MCHBAR32(C0DRT1) >> 10;
1870         reg32 &= 0x3f;
1871
1872         /* 788nS - tRFC */
1873         switch (sysinfo->memory_frequency) {
1874         case 400: /* 5nS */
1875                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1876                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1877                 break;
1878         case 533: /* 3.75nS */
1879                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1880                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1881                 break;
1882         case 667: /* 3nS */
1883                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1884                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1885                 break;
1886         }
1887
1888         temp_drt |= reg32;
1889
1890         MCHBAR32(C0DRT3) = temp_drt;
1891         MCHBAR32(C1DRT3) = temp_drt;
1892 }
1893
1894 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1895 {
1896         u32 reg32;
1897
1898         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1899
1900         if (sdram_capabilities_interleave() &&
1901                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1902                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1903                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1904                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1905                 /* Both channels equipped with DIMMs of the same size */
1906                 sysinfo->interleaved = 1;
1907         } else {
1908                 sysinfo->interleaved = 0;
1909         }
1910
1911         reg32 = MCHBAR32(DCC);
1912         reg32 &= ~(7 << 0);
1913
1914         if(sysinfo->interleaved) {
1915                 /* Dual Channel Interleaved */
1916                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1917                 reg32 |= (1 << 1);
1918         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1919                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1920                 /* Channel 1 only */
1921                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1922                 reg32 |= (1 << 2);
1923         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1924                         SYSINFO_DIMM_NOT_POPULATED) {
1925                 /* Dual Channel Assymetric */
1926                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1927                 reg32 |= (1 << 0);
1928         } else {
1929                 /* All bits 0 means Single Channel 0 operation */
1930                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1931         }
1932
1933         /* Now disable channel XORing */
1934         reg32 |= (1 << 10);
1935
1936         MCHBAR32(DCC) = reg32;
1937
1938         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1939 }
1940
1941 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1942 {
1943         volatile u16 reg16;
1944
1945         MCHBAR32(PLLMON) = 0x80800000;
1946
1947         sysinfo->fsb_frequency = fsbclk();
1948         if (sysinfo->fsb_frequency == 0xffff)
1949                 die("Unsupported FSB speed");
1950
1951         /* Program CPCTL according to FSB speed */
1952         /* Only write the lower byte */
1953         switch (sysinfo->fsb_frequency) {
1954         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1955         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1956         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1957         }
1958
1959         MCHBAR16(CPCTL) &= ~(1 << 11);
1960
1961         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1962 }
1963
1964 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1965 {
1966         u8  reg8;
1967         u16 reg16;
1968         u8  freq, second_vco, voltage;
1969
1970 #define CRCLK_166MHz    0x00
1971 #define CRCLK_200MHz    0x01
1972 #define CRCLK_250MHz    0x03
1973 #define CRCLK_400MHz    0x05
1974
1975 #define CDCLK_200MHz    0x00
1976 #define CDCLK_320MHz    0x40
1977
1978 #define VOLTAGE_1_05    0x00
1979 #define VOLTAGE_1_50    0x01
1980
1981         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1982
1983         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1984
1985         voltage = VOLTAGE_1_05;
1986         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1987                 voltage = VOLTAGE_1_50;
1988         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1989
1990         /* Gate graphics hardware for frequency change */
1991         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1992         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1993         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1994
1995         /* Get graphics frequency capabilities */
1996         reg8 = sdram_capabilities_core_frequencies();
1997
1998         freq = CRCLK_250MHz;
1999         switch (reg8) {
2000         case GFX_FREQUENCY_CAP_ALL:
2001                 if (voltage == VOLTAGE_1_05)
2002                         freq = CRCLK_250MHz;
2003                 else
2004                         freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
2005                 break;
2006         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
2007         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
2008         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
2009         }
2010
2011         if (freq != CRCLK_400MHz) {
2012                 /* What chipset are we? Force 166MHz for GMS */
2013                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
2014                 if (reg8==2)
2015                         freq = CRCLK_166MHz;
2016         }
2017
2018         printk(BIOS_DEBUG, "Render: ");
2019         switch (freq) {
2020         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2021         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2022         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2023         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2024         }
2025
2026         if (i945_silicon_revision() == 0) {
2027                 sysinfo->mvco4x = 1;
2028         } else {
2029                 sysinfo->mvco4x = 0;
2030         }
2031
2032         second_vco = 0;
2033
2034         if (voltage == VOLTAGE_1_50) {
2035                 second_vco = 1;
2036         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
2037                 u16 mem = sysinfo->memory_frequency;
2038                 u16 fsb = sysinfo->fsb_frequency;
2039
2040                 if ( (fsb == 667 && mem == 533) ||
2041                      (fsb == 533 && mem == 533) ||
2042                      (fsb == 533 && mem == 400)) {
2043                         second_vco = 1;
2044                 }
2045
2046                 if (fsb == 667 && mem == 533)
2047                         sysinfo->mvco4x = 1;
2048         }
2049
2050         if (second_vco) {
2051                 sysinfo->clkcfg_bit7=1;
2052         } else {
2053                 sysinfo->clkcfg_bit7=0;
2054         }
2055
2056         /* Graphics Core Render Clock */
2057         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2058         reg16 &= ~( (7 << 0) | (1 << 13) );
2059         reg16 |= freq;
2060         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2061
2062         /* Graphics Core Display Clock */
2063         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2064         reg8 &= ~( (1<<7) | (7<<4) );
2065
2066         if (voltage == VOLTAGE_1_05) {
2067                 reg8 |= CDCLK_200MHz;
2068                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2069         } else {
2070                 reg8 |= CDCLK_320MHz;
2071                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2072         }
2073         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2074
2075         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2076
2077         reg8 |= (1<<3) | (1<<1);
2078         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2079
2080         reg8 |= 0x0f;
2081         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2082
2083         /* Ungate core render and display clocks */
2084         reg8 &= 0xf0;
2085         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2086 }
2087
2088 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2089 {
2090         u32 clkcfg;
2091         u8 reg8;
2092
2093         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2094
2095         clkcfg = MCHBAR32(CLKCFG);
2096
2097         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2098
2099         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2100
2101         if (sysinfo->mvco4x) {
2102                 printk(BIOS_DEBUG, "MVCO 4x, ");
2103                 clkcfg &= ~(1 << 12);
2104         }
2105
2106         if (sysinfo->clkcfg_bit7) {
2107                 printk(BIOS_DEBUG, "second VCO, ");
2108
2109                 clkcfg |= (1 << 7);
2110         }
2111
2112         switch (sysinfo->memory_frequency) {
2113         case 400: clkcfg |= (2 << 4); break;
2114         case 533: clkcfg |= (3 << 4); break;
2115         case 667: clkcfg |= (4 << 4); break;
2116         default: die("Target Memory Frequency Error");
2117         }
2118
2119         if (MCHBAR32(CLKCFG) == clkcfg) {
2120                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2121                 return;
2122         }
2123
2124         MCHBAR32(CLKCFG) = clkcfg;
2125
2126         /* Make sure the following code is in the
2127          * cache before we execute it.
2128          */
2129         goto cache_code;
2130 vco_update:
2131         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2132         reg8 &= ~(1 << 7);
2133         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2134
2135         clkcfg &= ~(1 << 10);
2136         MCHBAR32(CLKCFG) = clkcfg;
2137         clkcfg |= (1 << 10);
2138         MCHBAR32(CLKCFG) = clkcfg;
2139
2140         asm volatile (
2141                 "       movl $0x100, %%ecx\n"
2142                 "delay_update:\n"
2143                 "       nop\n"
2144                 "       nop\n"
2145                 "       nop\n"
2146                 "       nop\n"
2147                 "       loop delay_update\n"
2148                 : /* No outputs */
2149                 : /* No inputs */
2150                 : "%ecx", "memory"
2151                 );
2152
2153         clkcfg &= ~(1 << 10);
2154         MCHBAR32(CLKCFG) = clkcfg;
2155
2156         goto out;
2157 cache_code:
2158         goto vco_update;
2159 out:
2160
2161         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2162         printk(BIOS_DEBUG, "ok\n");
2163 }
2164
2165 static void sdram_program_clock_crossing(void)
2166 {
2167         int idx = 0;
2168
2169         /**
2170          * We add the indices according to our clocks from CLKCFG.
2171          */
2172 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2173         static const u32 data_clock_crossing[] = {
2174                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2175                 0xffffffff, 0xffffffff, /*  nonexistant  */
2176                 0xffffffff, 0xffffffff, /*  nonexistant  */
2177
2178                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2179                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2180                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2181
2182                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2183                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2184                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2185
2186                 0xffffffff, 0xffffffff, /*  nonexistant  */
2187                 0xffffffff, 0xffffffff, /*  nonexistant  */
2188                 0xffffffff, 0xffffffff, /*  nonexistant  */
2189
2190                 0xffffffff, 0xffffffff, /*  nonexistant  */
2191                 0xffffffff, 0xffffffff, /*  nonexistant  */
2192                 0xffffffff, 0xffffffff, /*  nonexistant  */
2193         };
2194
2195         static const u32 command_clock_crossing[] = {
2196                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2197                 0xffffffff, 0xffffffff, /*  nonexistant  */
2198                 0xffffffff, 0xffffffff, /*  nonexistant  */
2199
2200                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2201                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2202                 0xffffffff, 0xffffffff, /*  nonexistant  */
2203
2204                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2205                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2206                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2207
2208                 0xffffffff, 0xffffffff, /*  nonexistant  */
2209                 0xffffffff, 0xffffffff, /*  nonexistant  */
2210                 0xffffffff, 0xffffffff, /*  nonexistant  */
2211
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214                 0xffffffff, 0xffffffff, /*  nonexistant  */
2215         };
2216
2217 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2218         /* i945 G/P */
2219         static const u32 data_clock_crossing[] = {
2220                 0xffffffff, 0xffffffff, /*  nonexistant  */
2221                 0xffffffff, 0xffffffff, /*  nonexistant  */
2222                 0xffffffff, 0xffffffff, /*  nonexistant  */
2223
2224                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2225                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2226                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2227
2228                 0xffffffff, 0xffffffff, /*  nonexistant  */
2229                 0xffffffff, 0xffffffff, /*  nonexistant  */
2230                 0xffffffff, 0xffffffff, /*  nonexistant  */
2231
2232                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2233                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2234                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2235
2236                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2237                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2238                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2239         };
2240
2241         static const u32 command_clock_crossing[] = {
2242                 0xffffffff, 0xffffffff, /*  nonexistant  */
2243                 0xffffffff, 0xffffffff, /*  nonexistant  */
2244                 0xffffffff, 0xffffffff, /*  nonexistant  */
2245
2246                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2247                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2248                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2249
2250                 0xffffffff, 0xffffffff, /*  nonexistant  */
2251                 0xffffffff, 0xffffffff, /*  nonexistant  */
2252                 0xffffffff, 0xffffffff, /*  nonexistant  */
2253
2254                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2255                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2256                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2257
2258                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2259                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2260                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2261         };
2262 #endif
2263
2264         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2265
2266         printk(BIOS_DEBUG, "MEM=");
2267         switch (memclk()) {
2268         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2269         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2270         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2271         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2272         }
2273
2274         printk(BIOS_DEBUG, " FSB=");
2275         switch (fsbclk()) {
2276         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2277         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2278         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2279         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2280         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2281         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2282         }
2283
2284         if (command_clock_crossing[idx]==0xffffffff) {
2285                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2286         }
2287
2288         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2289         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2290
2291         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2292         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2293         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2294         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2295
2296         printk(BIOS_DEBUG, "... ok\n");
2297 }
2298
2299 static void sdram_disable_fast_dispatch(void)
2300 {
2301         u32 reg32;
2302
2303         reg32 = MCHBAR32(FSBPMC3);
2304         reg32 |= (1 << 1);
2305         MCHBAR32(FSBPMC3) = reg32;
2306
2307         reg32 = MCHBAR32(SBTEST);
2308         reg32 |= (3 << 1);
2309         MCHBAR32(SBTEST) = reg32;
2310 }
2311
2312 static void sdram_pre_jedec_initialization(void)
2313 {
2314         u32 reg32;
2315
2316         reg32 = MCHBAR32(WCC);
2317         reg32 &= 0x113ff3ff;
2318         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2319         MCHBAR32(WCC) = reg32;
2320
2321         MCHBAR32(SMVREFC) |= (1 << 6);
2322
2323         MCHBAR32(MMARB0) &= ~(3 << 17);
2324         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2325
2326         MCHBAR32(MMARB1) &= ~(7 << 8);
2327         MCHBAR32(MMARB1) |= (3 << 8);
2328
2329         /* Adaptive Idle Timer Control */
2330         MCHBAR32(C0AIT) = 0x000006c4;
2331         MCHBAR32(C0AIT+4) = 0x871a066d;
2332
2333         MCHBAR32(C1AIT) = 0x000006c4;
2334         MCHBAR32(C1AIT+4) = 0x871a066d;
2335 }
2336
2337 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2338 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2339 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2340 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2341 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2342 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2343 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2344 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2345
2346 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2347 {
2348         u32 chan0 = 0, chan1 = 0;
2349         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2350
2351         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2352                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2353         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2354                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2355         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2356         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2357
2358         if (sdram_capabilities_enhanced_addressing_xor()) {
2359                 if (!sysinfo->interleaved) {
2360                         /* Single Channel & Dual Channel Assymetric */
2361                         if (chan0_populated) {
2362                                 if (chan0_dualsided) {
2363                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2364                                 } else {
2365                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2366                                 }
2367                         }
2368                         if (chan1_populated) {
2369                                 if (chan1_dualsided) {
2370                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2371                                 } else {
2372                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2373                                 }
2374                         }
2375                 } else {
2376                         /* Interleaved has always both channels populated */
2377                         if (chan0_dualsided) {
2378                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2379                         } else {
2380                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2381                         }
2382
2383                         if (chan1_dualsided) {
2384                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2385                         } else {
2386                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2387                         }
2388                 }
2389         } else {
2390                 if (!sysinfo->interleaved) {
2391                         /* Single Channel & Dual Channel Assymetric */
2392                         if (chan0_populated) {
2393                                 if (chan0_dualsided) {
2394                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2395                                 } else {
2396                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2397                                 }
2398                         }
2399                         if (chan1_populated) {
2400                                 if (chan1_dualsided) {
2401                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2402                                 } else {
2403                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2404                                 }
2405                         }
2406                 } else {
2407                         /* Interleaved has always both channels populated */
2408                         if (chan0_dualsided) {
2409                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2410                         } else {
2411                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2412                         }
2413
2414                         if (chan1_dualsided) {
2415                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2416                         } else {
2417                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2418                         }
2419                 }
2420         }
2421
2422         MCHBAR32(C0DRC1) &= 0x00ffffff;
2423         MCHBAR32(C0DRC1) |= chan0;
2424         MCHBAR32(C1DRC1) &= 0x00ffffff;
2425         MCHBAR32(C1DRC1) |= chan1;
2426 }
2427
2428 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2429 {
2430         u32 reg32;
2431
2432         /* Enable Channel XORing for Dual Channel Interleave */
2433         if (sysinfo->interleaved) {
2434
2435                 reg32 = MCHBAR32(DCC);
2436 #if CONFIG_CHANNEL_XOR_RANDOMIZATION
2437                 reg32 &= ~(1 << 10);
2438                 reg32 |= (1 << 9);
2439 #else
2440                 reg32 &= ~(1 << 9);
2441 #endif
2442                 MCHBAR32(DCC) = reg32;
2443         }
2444
2445         /* DRAM mode optimizations */
2446         sdram_enhanced_addressing_mode(sysinfo);
2447
2448         reg32 = MCHBAR32(FSBPMC3);
2449         reg32 &= ~(1 << 1);
2450         MCHBAR32(FSBPMC3) = reg32;
2451
2452         reg32 = MCHBAR32(SBTEST);
2453         reg32 &= ~(1 << 2);
2454         MCHBAR32(SBTEST) = reg32;
2455
2456         reg32 = MCHBAR32(SBOCC);
2457         reg32 &= 0xffbdb6ff;
2458         reg32 |= (0xbdb6 << 8) | (1 << 0);
2459         MCHBAR32(SBOCC) = reg32;
2460 }
2461
2462 static void sdram_power_management(struct sys_info *sysinfo)
2463 {
2464         u8 reg8;
2465         u16 reg16;
2466         u32 reg32;
2467         int integrated_graphics = 1;
2468         int i;
2469
2470         reg32 = MCHBAR32(C0DRT2);
2471         reg32 &= 0xffffff00;
2472         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2473         reg32 |= (1 << 5) | (1 << 4);
2474         MCHBAR32(C0DRT2) = reg32;
2475
2476         reg32 = MCHBAR32(C1DRT2);
2477         reg32 &= 0xffffff00;
2478         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2479         reg32 |= (1 << 5) | (1 << 4);
2480         MCHBAR32(C1DRT2) = reg32;
2481
2482         reg32 = MCHBAR32(C0DRC1);
2483
2484         reg32 |= (1 << 12) | (1 << 11);
2485         MCHBAR32(C0DRC1) = reg32;
2486
2487         reg32 = MCHBAR32(C1DRC1);
2488
2489         reg32 |= (1 << 12) | (1 << 11);
2490         MCHBAR32(C1DRC1) = reg32;
2491
2492         if (i945_silicon_revision()>1) {
2493                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2494                 u16 peg_bits = (1 << 5) | (1 << 0);
2495
2496                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2497         } else {
2498                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2499                 u16 peg_bits = (1 << 5) | (1 << 0);
2500
2501                 /* Rev 0 and 1 */
2502                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2503         }
2504
2505         reg16 = MCHBAR16(UPMC2);
2506         reg16 &= 0xfc00;
2507         reg16 |= 0x0100;
2508         MCHBAR16(UPMC2) = reg16;
2509
2510         MCHBAR32(UPMC3) = 0x000f06ff;
2511
2512         for (i=0; i<5; i++) {
2513                 MCHBAR32(UPMC3) &= ~(1 << 16);
2514                 MCHBAR32(UPMC3) |= (1 << 16);
2515         }
2516
2517         MCHBAR32(GIPMC1) = 0x8000000c;
2518
2519         reg16 = MCHBAR16(CPCTL);
2520         reg16 &= ~(7 << 11);
2521         if (i945_silicon_revision()>2) {
2522                 reg16 |= (6 << 11);
2523         } else {
2524                 reg16 |= (4 << 11);
2525         }
2526         MCHBAR16(CPCTL) = reg16;
2527
2528 #if 0
2529         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2530 #else
2531         if (i945_silicon_revision() != 0) {
2532 #endif
2533                 switch (sysinfo->fsb_frequency) {
2534                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2535                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2536                 }
2537         } else {
2538                 switch (sysinfo->fsb_frequency) {
2539                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2540                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2541                 }
2542         }
2543
2544         MCHBAR32(FSBPMC1) = 0x8000000c;
2545
2546         reg32 = MCHBAR32(C2C3TT);
2547         reg32 &= 0xffff0000;
2548         switch (sysinfo->fsb_frequency) {
2549         case 667: reg32 |= 0x0600; break;
2550         case 533: reg32 |= 0x0480; break;
2551         }
2552         MCHBAR32(C2C3TT) = reg32;
2553
2554         reg32 = MCHBAR32(C3C4TT);
2555         reg32 &= 0xffff0000;
2556         switch (sysinfo->fsb_frequency) {
2557         case 667: reg32 |= 0x0b80; break;
2558         case 533: reg32 |= 0x0980; break;
2559         }
2560         MCHBAR32(C3C4TT) = reg32;
2561
2562         if (i945_silicon_revision() == 0) {
2563                 MCHBAR32(ECO) &= ~(1 << 16);
2564         } else {
2565                 MCHBAR32(ECO) |= (1 << 16);
2566         }
2567
2568 #if 0
2569
2570         if (i945_silicon_revision() == 0) {
2571                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2572         } else {
2573                 MCHBAR32(FSBPMC3) |= (1 << 29);
2574         }
2575 #endif
2576         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2577
2578         MCHBAR32(FSBPMC3) |= (1 << 21);
2579
2580         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2581
2582         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2583
2584         reg32 = MCHBAR32(FSBPMC4);
2585         reg32 &= ~(3 << 24);
2586         reg32 |= ( 2 << 24);
2587         MCHBAR32(FSBPMC4) = reg32;
2588
2589         MCHBAR32(FSBPMC4) |= (1 << 21);
2590
2591         MCHBAR32(FSBPMC4) |= (1 << 5);
2592
2593         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2594                 /* stepping 0 and 1 or CPUID 6e8 */
2595                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2596         } else {
2597                 MCHBAR32(FSBPMC4) |= (1 << 4);
2598         }
2599
2600         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2601         reg8 |= (1 << 4);
2602         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2603
2604         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2605         reg8 |= (1 << 2);
2606         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2607
2608 #ifdef C2_SELF_REFRESH_DISABLE
2609
2610         if (integrated_graphics) {
2611                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2612                 MCHBAR16(MIPMC4) = 0x0468;
2613                 MCHBAR16(MIPMC5) = 0x046c;
2614                 MCHBAR16(MIPMC6) = 0x046c;
2615         } else {
2616                 MCHBAR16(MIPMC4) = 0x6468;
2617                 MCHBAR16(MIPMC5) = 0x646c;
2618                 MCHBAR16(MIPMC6) = 0x646c;
2619         }
2620 #else
2621         if (integrated_graphics) {
2622                 MCHBAR16(MIPMC4) = 0x04f8;
2623                 MCHBAR16(MIPMC5) = 0x04fc;
2624                 MCHBAR16(MIPMC6) = 0x04fc;
2625         } else {
2626                 MCHBAR16(MIPMC4) = 0x64f8;
2627                 MCHBAR16(MIPMC5) = 0x64fc;
2628                 MCHBAR16(MIPMC6) = 0x64fc;
2629         }
2630
2631 #endif
2632
2633         reg32 = MCHBAR32(PMCFG);
2634         reg32 &= ~(3 << 17);
2635         reg32 |= (2 << 17);
2636         MCHBAR32(PMCFG) = reg32;
2637
2638         MCHBAR32(PMCFG) |= (1 << 4);
2639
2640         reg32 = MCHBAR32(0xc30);
2641         reg32 &= 0xffffff00;
2642         reg32 |= 0x01;
2643         MCHBAR32(0xc30) = reg32;
2644
2645         MCHBAR32(0xb18) &= ~(1 << 21);
2646 }
2647
2648 static void sdram_thermal_management(void)
2649 {
2650
2651         MCHBAR8(TCO1) = 0x00;
2652         MCHBAR8(TCO0) = 0x00;
2653
2654         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2655          * 0x30/0x32.
2656          */
2657
2658         /* TODO This is not implemented yet. Volunteers? */
2659 }
2660
2661 static void sdram_save_receive_enable(void)
2662 {
2663         int i;
2664         u32 reg32;
2665         u8 values[4];
2666
2667         /* The following values are stored to an unused CMOS
2668          * area and restored instead of recalculated in case
2669          * of an S3 resume.
2670          *
2671          * C0WL0REOST [7:0]             -> 8 bit
2672          * C1WL0REOST [7:0]             -> 8 bit
2673          * RCVENMT    [11:8] [3:0]      -> 8 bit
2674          * C0DRT1     [27:24]           -> 4 bit
2675          * C1DRT1     [27:24]           -> 4 bit
2676          */
2677
2678         values[0] = MCHBAR8(C0WL0REOST);
2679         values[1] = MCHBAR8(C1WL0REOST);
2680
2681         reg32 = MCHBAR32(RCVENMT);
2682         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2683
2684         reg32 = MCHBAR32(C0DRT1);
2685         values[3] = (reg32 >> 24) & 0x0f;
2686         reg32 = MCHBAR32(C1DRT1);
2687         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2688
2689         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2690          * so we grab bytes 128 - 131 to save the receive enable values
2691          */
2692
2693         for (i=0; i<4; i++)
2694                 cmos_write(values[i], 128 + i);
2695 }
2696
2697 static void sdram_recover_receive_enable(void)
2698 {
2699         int i;
2700         u32 reg32;
2701         u8 values[4];
2702
2703         for (i=0; i<4; i++)
2704                 values[i] = cmos_read(128 + i);
2705
2706         MCHBAR8(C0WL0REOST) = values[0];
2707         MCHBAR8(C1WL0REOST) = values[1];
2708
2709         reg32 = MCHBAR32(RCVENMT);
2710         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2711         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2712         MCHBAR32(RCVENMT) = reg32;
2713
2714         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2715         reg32 |= (u32)(values[3] & 0x0f) << 24;
2716         MCHBAR32(C0DRT1) = reg32;
2717
2718         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2719         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2720         MCHBAR32(C1DRT1) = reg32;
2721 }
2722
2723 #include "rcven.c"
2724
2725 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2726 {
2727         MCHBAR32(REPC) |= (1 << 0);
2728
2729         /* enable upper CMOS */
2730         RCBA32(0x3400) = (1 << 2);
2731
2732         /* Program Receive Enable Timings */
2733         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2734                 sdram_recover_receive_enable();
2735         } else {
2736                 receive_enable_adjust(sysinfo);
2737                 sdram_save_receive_enable();
2738         }
2739
2740         MCHBAR32(C0DRC1) |= (1 << 6);
2741         MCHBAR32(C1DRC1) |= (1 << 6);
2742         MCHBAR32(C0DRC1) &= ~(1 << 6);
2743         MCHBAR32(C1DRC1) &= ~(1 << 6);
2744
2745         MCHBAR32(MIPMC3) |= (0x0f << 0);
2746 }
2747
2748 /**
2749  * @brief Enable On-Die Termination for DDR2.
2750  *
2751  */
2752
2753 static void sdram_on_die_termination(struct sys_info *sysinfo)
2754 {
2755         static const u32 odt[] = {
2756                 0x00024911, 0xe0010000,
2757                 0x00049211, 0xe0020000,
2758                 0x0006db11, 0xe0030000,
2759         };
2760
2761         u32 reg32;
2762         int cas;
2763
2764         reg32 = MCHBAR32(ODTC);
2765         reg32 &= ~(3 << 16);
2766         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2767         MCHBAR32(ODTC) = reg32;
2768
2769         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2770                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2771                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2772
2773                 reg32 = MCHBAR32(C0ODT);
2774                 reg32 &= ~(7 << 28);
2775                 MCHBAR32(C0ODT) = reg32;
2776                 reg32 = MCHBAR32(C1ODT);
2777                 reg32 &= ~(7 << 28);
2778                 MCHBAR32(C1ODT) = reg32;
2779         }
2780
2781         cas = sysinfo->cas;
2782
2783         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2784         reg32 |= odt[(cas-3) * 2];
2785         MCHBAR32(C0ODT) = reg32;
2786
2787         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2788         reg32 |= odt[(cas-3) * 2];
2789         MCHBAR32(C1ODT) = reg32;
2790
2791         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2792         reg32 |= odt[((cas-3) * 2) + 1];
2793         MCHBAR32(C0ODT + 4) = reg32;
2794
2795         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2796         reg32 |= odt[((cas-3) * 2) + 1];
2797         MCHBAR32(C1ODT + 4) = reg32;
2798 }
2799
2800 /**
2801  * @brief Enable clocks to populated sockets
2802  */
2803
2804 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2805 {
2806         u8 clocks[2] = { 0, 0 };
2807
2808 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2809 #define CLOCKS_WIDTH 2
2810 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2811 #define CLOCKS_WIDTH 3
2812 #endif
2813         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2814                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2815
2816         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2817                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2818
2819         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2820                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2821
2822         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2823                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2824
2825 #if CONFIG_OVERRIDE_CLOCK_DISABLE
2826         /* Usually system firmware turns off system memory clock signals
2827          * to unused SO-DIMM slots to reduce EMI and power consumption.
2828          * However, the Kontron 986LCD-M does not like unused clock
2829          * signals to be disabled.
2830          */
2831
2832         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2833         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2834 #endif
2835
2836         MCHBAR8(C0DCLKDIS) = clocks[0];
2837         MCHBAR8(C1DCLKDIS) = clocks[1];
2838 }
2839
2840 #define RTT_ODT_NONE    0
2841 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2842 #define RTT_ODT_75_OHM  (1 << 5)
2843 #define RTT_ODT_150_OHM (1 << 9)
2844
2845 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2846
2847 #define MRS_CAS_3       (3 << 7)
2848 #define MRS_CAS_4       (4 << 7)
2849 #define MRS_CAS_5       (5 << 7)
2850
2851 #define MRS_TWR_3       (2 << 12)
2852 #define MRS_TWR_4       (3 << 12)
2853 #define MRS_TWR_5       (4 << 12)
2854
2855 #define MRS_BT          (1 << 6)
2856
2857 #define MRS_BL4         (2 << 3)
2858 #define MRS_BL8         (3 << 3)
2859
2860 static void sdram_jedec_enable(struct sys_info *sysinfo)
2861 {
2862         int i, nonzero;
2863         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2864
2865         for (i = 0, nonzero = -1; i < 8; i++) {
2866                 if (sysinfo->banksize[i]  == 0) {
2867                         continue;
2868                 }
2869
2870                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2871                 switch (i) {
2872                 case 0:
2873                         /* Start at address 0 */
2874                         bankaddr = 0;
2875                         break;
2876                 case 4:
2877                         if (sysinfo->interleaved) {
2878                                 bankaddr = 0x40;
2879                                 break;
2880                         }
2881                 default:
2882                         if (nonzero != -1) {
2883                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2884                                 bankaddr += sysinfo->banksize[nonzero] <<
2885                                         (sysinfo->interleaved ? 26 : 25);
2886                                 break;
2887                         }
2888                         /* No populated bank hit before. Start at address 0 */
2889                         bankaddr = 0;
2890                 }
2891
2892                 /* We have a bank with a non-zero size.. Remember it
2893                  * for the next offset we have to calculate
2894                  */
2895                 nonzero = i;
2896
2897                 /* Get CAS latency set up */
2898                 switch (sysinfo->cas) {
2899                 case 5: mrsaddr = MRS_CAS_5; break;
2900                 case 4: mrsaddr = MRS_CAS_4; break;
2901                 case 3: mrsaddr = MRS_CAS_3; break;
2902                 default: die("Jedec Error (CAS).\n");
2903                 }
2904
2905                 /* Get tWR set */
2906                 switch (sysinfo->twr) {
2907                 case 5: mrsaddr |= MRS_TWR_5; break;
2908                 case 4: mrsaddr |= MRS_TWR_4; break;
2909                 case 3: mrsaddr |= MRS_TWR_3; break;
2910                 default: die("Jedec Error (tWR).\n");
2911                 }
2912
2913                 /* Set "Burst Type" */
2914                 mrsaddr |= MRS_BT;
2915
2916                 /* Interleaved */
2917                 if (sysinfo->interleaved) {
2918                         mrsaddr = mrsaddr << 1;
2919                 }
2920
2921                 /* Only burst length 8 supported */
2922                 mrsaddr |= MRS_BL8;
2923
2924                 /* Apply NOP */
2925                 PRINTK_DEBUG("Apply NOP\n");
2926                 do_ram_command(RAM_COMMAND_NOP);
2927                 ram_read32(bankaddr);
2928
2929                 /* Precharge all banks */
2930                 PRINTK_DEBUG("All Banks Precharge\n");
2931                 do_ram_command(RAM_COMMAND_PRECHARGE);
2932                 ram_read32(bankaddr);
2933
2934                 /* Extended Mode Register Set (2) */
2935                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2936                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2937                 ram_read32(bankaddr);
2938
2939                 /* Extended Mode Register Set (3) */
2940                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2941                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2942                 ram_read32(bankaddr);
2943
2944                 /* Extended Mode Register Set */
2945                 PRINTK_DEBUG("Extended Mode Register Set\n");
2946                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2947                 tmpaddr = bankaddr;
2948                 if (!sdram_capabilities_dual_channel()) {
2949                         tmpaddr |= RTT_ODT_75_OHM;
2950                 } else if (sysinfo->interleaved) {
2951                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2952                 } else {
2953                         tmpaddr |= RTT_ODT_150_OHM;
2954                 }
2955                 ram_read32(tmpaddr);
2956
2957                 /* Mode Register Set: Reset DLLs */
2958                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2959                 do_ram_command(RAM_COMMAND_MRS);
2960                 tmpaddr = bankaddr;
2961                 tmpaddr |= mrsaddr;
2962                 /* Set DLL reset bit */
2963                 if (sysinfo->interleaved)
2964                         tmpaddr |= (1 << 12);
2965                 else
2966                         tmpaddr |= (1 << 11);
2967                 ram_read32(tmpaddr);
2968
2969                 /* Precharge all banks */
2970                 PRINTK_DEBUG("All Banks Precharge\n");
2971                 do_ram_command(RAM_COMMAND_PRECHARGE);
2972                 ram_read32(bankaddr);
2973
2974                 /* CAS before RAS Refresh */
2975                 PRINTK_DEBUG("CAS before RAS\n");
2976                 do_ram_command(RAM_COMMAND_CBR);
2977
2978                 /* CBR wants two READs */
2979                 ram_read32(bankaddr);
2980                 ram_read32(bankaddr);
2981
2982                 /* Mode Register Set: Enable DLLs */
2983                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2984                 do_ram_command(RAM_COMMAND_MRS);
2985
2986                 tmpaddr = bankaddr;
2987                 tmpaddr |= mrsaddr;
2988                 ram_read32(tmpaddr);
2989
2990                 /* Extended Mode Register Set */
2991                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2992                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2993
2994                 tmpaddr = bankaddr;
2995                 if (!sdram_capabilities_dual_channel()) {
2996
2997                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2998                 } else if (sysinfo->interleaved) {
2999                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
3000                 } else {
3001                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
3002                 }
3003                 ram_read32(tmpaddr);
3004
3005                 /* Extended Mode Register Set */
3006                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
3007                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
3008
3009                 tmpaddr = bankaddr;
3010                 if (!sdram_capabilities_dual_channel()) {
3011                         tmpaddr |= RTT_ODT_75_OHM;
3012                 } else if (sysinfo->interleaved) {
3013                         tmpaddr |= (RTT_ODT_150_OHM << 1);
3014                 } else {
3015                         tmpaddr |= RTT_ODT_150_OHM;
3016                 }
3017                 ram_read32(tmpaddr);
3018         }
3019 }
3020
3021 static void sdram_init_complete(void)
3022 {
3023         PRINTK_DEBUG("Normal Operation\n");
3024         do_ram_command(RAM_COMMAND_NORMAL);
3025 }
3026
3027 static void sdram_setup_processor_side(void)
3028 {
3029         if (i945_silicon_revision() == 0)
3030                 MCHBAR32(FSBPMC3) |= (1 << 2);
3031
3032         MCHBAR8(0xb00) |= 1;
3033
3034         if (i945_silicon_revision() == 0)
3035                 MCHBAR32(SLPCTL) |= (1 << 8);
3036 }
3037
3038 /**
3039  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3040  */
3041 void sdram_initialize(int boot_path)
3042 {
3043         struct sys_info sysinfo;
3044         u8 reg8, cas_mask;
3045
3046         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3047
3048         memset(&sysinfo, 0, sizeof(sysinfo));
3049
3050         sysinfo.boot_path = boot_path;
3051
3052         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3053         sdram_get_dram_configuration(&sysinfo);
3054
3055         /* If error, do cold boot */
3056         sdram_detect_errors(&sysinfo);
3057
3058         /* Check whether we have stacked DIMMs */
3059         sdram_verify_package_type(&sysinfo);
3060
3061         /* Determine common CAS */
3062         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3063
3064         /* Choose Common Frequency */
3065         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3066
3067         /* Determine smallest common tRAS */
3068         sdram_detect_smallest_tRAS(&sysinfo);
3069
3070         /* Determine tRP */
3071         sdram_detect_smallest_tRP(&sysinfo);
3072
3073         /* Determine tRCD */
3074         sdram_detect_smallest_tRCD(&sysinfo);
3075
3076         /* Determine smallest refresh period */
3077         sdram_detect_smallest_refresh(&sysinfo);
3078
3079         /* Verify all DIMMs support burst length 8 */
3080         sdram_verify_burst_length(&sysinfo);
3081
3082         /* determine tWR */
3083         sdram_detect_smallest_tWR(&sysinfo);
3084
3085         /* Determine DIMM size parameters (rows, columns banks) */
3086         sdram_detect_dimm_size(&sysinfo);
3087
3088         /* determine tRFC */
3089         sdram_detect_smallest_tRFC(&sysinfo);
3090
3091         /* Program PLL settings */
3092         sdram_program_pll_settings(&sysinfo);
3093
3094         /* Program Graphics Frequency */
3095         sdram_program_graphics_frequency(&sysinfo);
3096
3097         /* Program System Memory Frequency */
3098         sdram_program_memory_frequency(&sysinfo);
3099
3100         /* Determine Mode of Operation (Interleaved etc) */
3101         sdram_set_channel_mode(&sysinfo);
3102
3103         /* Program Clock Crossing values */
3104         sdram_program_clock_crossing();
3105
3106         /* Disable fast dispatch */
3107         sdram_disable_fast_dispatch();
3108
3109         /* Enable WIODLL Power Down in ACPI states */
3110         MCHBAR32(C0DMC) |= (1 << 24);
3111         MCHBAR32(C1DMC) |= (1 << 24);
3112
3113         /* Program DRAM Row Boundary/Attribute Registers */
3114
3115         /* program row size DRB and set TOLUD */
3116         sdram_program_row_boundaries(&sysinfo);
3117
3118         /* program page size DRA */
3119         sdram_set_row_attributes(&sysinfo);
3120
3121         /* Program CxBNKARC */
3122         sdram_set_bank_architecture(&sysinfo);
3123
3124         /* Program DRAM Timing and Control registers based on SPD */
3125         sdram_set_timing_and_control(&sysinfo);
3126
3127         /* On-Die Termination Adjustment */
3128         sdram_on_die_termination(&sysinfo);
3129
3130         /* Pre Jedec Initialization */
3131         sdram_pre_jedec_initialization();
3132
3133         /* Perform System Memory IO Initialization */
3134         sdram_initialize_system_memory_io(&sysinfo);
3135
3136         /* Perform System Memory IO Buffer Enable */
3137         sdram_enable_system_memory_io(&sysinfo);
3138
3139         /* Enable System Memory Clocks */
3140         sdram_enable_memory_clocks(&sysinfo);
3141
3142         if (boot_path == BOOT_PATH_NORMAL) {
3143                 /* Jedec Initialization sequence */
3144                 sdram_jedec_enable(&sysinfo);
3145         }
3146
3147         /* Program Power Management Registers */
3148         sdram_power_management(&sysinfo);
3149
3150         /* Post Jedec Init */
3151         sdram_post_jedec_initialization(&sysinfo);
3152
3153         /* Program DRAM Throttling */
3154         sdram_thermal_management();
3155
3156         /* Normal Operations */
3157         sdram_init_complete();
3158
3159         /* Program Receive Enable Timings */
3160         sdram_program_receive_enable(&sysinfo);
3161
3162         /* Enable Periodic RCOMP */
3163         sdram_enable_rcomp();
3164
3165         /* Tell ICH7 that we're done */
3166         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3167         reg8 &= ~(1 << 7);
3168         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3169
3170         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3171
3172         sdram_setup_processor_side();
3173 }
3174
3175 unsigned long get_top_of_ram(void)
3176 {
3177         /* This will not work if TSEG is in place! */
3178         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3179
3180         return (unsigned long) tom;
3181 }
3182