src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <pc80/mc146818rtc.h>
  24 #include <spd.h>
  25 #include <string.h>
  26 #include <arch/romcc_io.h>
  27 #include "raminit.h"
  28 #include "i945.h"
  29
  30 /* Debugging macros. */
  31 #if CONFIG_DEBUG_RAM_SETUP
  32 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  33 #else
  34 #define PRINTK_DEBUG(x...)
  35 #endif
  36
  37 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  38
  39 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  40 #define RAM_COMMAND_NOP                 (0x1 << 16)
  41 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  42 #define RAM_COMMAND_MRS                 (0x3 << 16)
  43 #define RAM_COMMAND_EMRS                (0x4 << 16)
  44 #define RAM_COMMAND_CBR                 (0x6 << 16)
  45 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  46
  47 #define RAM_EMRS_1                      (0x0 << 21)
  48 #define RAM_EMRS_2                      (0x1 << 21)
  49 #define RAM_EMRS_3                      (0x2 << 21)
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 static __attribute__((noinline)) void do_ram_command(u32 command)
  57 {
  58         u32 reg32;
  59
  60         reg32 = MCHBAR32(DCC);
  61         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  62         reg32 |= command;
  63
  64         /* Also set Init Complete */
  65         if (command == RAM_COMMAND_NORMAL)
  66                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  67
  68         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  69
  70         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  71
  72         PRINTK_DEBUG("...done\n");
  73
  74         udelay(1);
  75 }
  76
  77 static void ram_read32(u32 offset)
  78 {
  79         PRINTK_DEBUG("   ram read: %08x\n", offset);
  80
  81         read32(offset);
  82 }
  83
  84 #if CONFIG_DEBUG_RAM_SETUP
  85 static void sdram_dump_mchbar_registers(void)
  86 {
  87         int i;
  88         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  89
  90         for (i=0; i<0xfff; i+=4) {
  91                 if (MCHBAR32(i) == 0)
  92                         continue;
  93                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  94         }
  95 }
  96 #endif
  97
  98 static int memclk(void)
  99 {
 100         int offset = 0;
 101 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 102         offset++;
 103 #endif
 104         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
 105         case 1: return 400;
 106         case 2: return 533;
 107         case 3: return 667;
 108         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 109         }
 110         return -1;
 111 }
 112
 113 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 114 static u16 fsbclk(void)
 115 {
 116         switch (MCHBAR32(CLKCFG) & 7) {
 117         case 0: return 400;
 118         case 1: return 533;
 119         case 3: return 667;
 120         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 121         }
 122         return 0xffff;
 123 }
 124 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 125 static u16 fsbclk(void)
 126 {
 127         switch (MCHBAR32(CLKCFG) & 7) {
 128         case 0: return 1066;
 129         case 1: return 533;
 130         case 2: return 800;
 131         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 132         }
 133         return 0xffff;
 134 }
 135 #endif
 136
 137 static int sdram_capabilities_max_supported_memory_frequency(void)
 138 {
 139         u32 reg32;
 140
 141 #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
 142         return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 143 #endif
 144
 145         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 146         reg32 &= (7 << 0);
 147
 148         switch (reg32) {
 149         case 4: return 400;
 150         case 3: return 533;
 151         case 2: return 667;
 152         }
 153         /* Newer revisions of this chipset rather support faster memory clocks,
 154          * so if it's a reserved value, return the fastest memory clock that we
 155          * know of and can handle
 156          */
 157         return 667;
 158 }
 159
 160 /**
 161  * @brief determine whether chipset is capable of dual channel interleaved mode
 162  *
 163  * @return 1 if interleaving is supported, 0 otherwise
 164  */
 165 static int sdram_capabilities_interleave(void)
 166 {
 167         u32 reg32;
 168
 169         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 170         reg32 >>= 25;
 171         reg32 &= 1;
 172
 173         return (!reg32);
 174 }
 175
 176 /**
 177  * @brief determine whether chipset is capable of two memory channels
 178  *
 179  * @return 1 if dual channel operation is supported, 0 otherwise
 180  */
 181 static int sdram_capabilities_dual_channel(void)
 182 {
 183         u32 reg32;
 184
 185         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 186         reg32 >>= 24;
 187         reg32 &= 1;
 188
 189         return (!reg32);
 190 }
 191
 192 static int sdram_capabilities_enhanced_addressing_xor(void)
 193 {
 194         u8 reg8;
 195
 196         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 197         reg8 &= (1 << 7);
 198
 199         return (!reg8);
 200 }
 201
 202 static int sdram_capabilities_two_dimms_per_channel(void)
 203 {
 204         u8 reg8;
 205
 206         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 207         reg8 &= (1 << 0);
 208
 209         return (reg8 != 0);
 210 }
 211
 212 // TODO check if we ever need this function
 213 #if 0
 214 static int sdram_capabilities_MEM4G_disable(void)
 215 {
 216         u8 reg8;
 217
 218         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 219         reg8 &= (1 << 0);
 220
 221         return (reg8 != 0);
 222 }
 223 #endif
 224
 225 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 226 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 227 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 228 #define GFX_FREQUENCY_CAP_ALL           0x00
 229
 230 static int sdram_capabilities_core_frequencies(void)
 231 {
 232         u8 reg8;
 233
 234         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 235         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 236         reg8 >>= 1;
 237
 238         return (reg8);
 239 }
 240
 241 static void sdram_detect_errors(struct sys_info *sysinfo)
 242 {
 243         u8 reg8;
 244         u8 do_reset = 0;
 245
 246         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 247
 248         if (reg8 & ((1<<7)|(1<<2))) {
 249                 if (reg8 & (1<<2)) {
 250                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 251                         /* Write back clears bit 2 */
 252                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 253                         do_reset = 1;
 254
 255                 }
 256
 257                 if (reg8 & (1<<7)) {
 258                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 259                         reg8 &= ~(1<<7);
 260                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 261                         do_reset = 1;
 262                 }
 263
 264                 /* Set SLP_S3# Assertion Stretch Enable */
 265                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 266                 reg8 |= (1 << 3);
 267                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 268
 269                 if (do_reset) {
 270                         printk(BIOS_DEBUG, "Reset required.\n");
 271                         outb(0x00, 0xcf9);
 272                         outb(0x0e, 0xcf9);
 273                         for (;;) asm("hlt"); /* Wait for reset! */
 274                 }
 275         }
 276
 277         /* Set DRAM initialization bit in ICH7 */
 278         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 279         reg8 |= (1<<7);
 280         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 281
 282         /* clear self refresh if not wake-up from suspend */
 283         if (sysinfo->boot_path != 2) {
 284                 MCHBAR8(0xf14) |= 3;
 285         } else {
 286                 /* Validate self refresh config */
 287                 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
 288                      (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
 289                     !(MCHBAR8(0xf14) & (1<<0))) {
 290                         do_reset = 1;
 291                 }
 292                 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
 293                      (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
 294                     !(MCHBAR8(0xf14) & (1<<1))) {
 295                         do_reset = 1;
 296                 }
 297         }
 298
 299         if (do_reset) {
 300                 printk(BIOS_DEBUG, "Reset required.\n");
 301                 outb(0x00, 0xcf9);
 302                 outb(0x0e, 0xcf9);
 303                 for (;;) asm("hlt"); /* Wait for reset! */
 304         }
 305 }
 306
 307 /**
 308  * @brief Get generic DIMM parameters.
 309  * @param sysinfo Central memory controller information structure
 310  *
 311  * This function gathers several pieces of information for each system DIMM:
 312  *  o DIMM width (x8 / x16)
 313  *  o DIMM sides (single sided / dual sided)
 314  *
 315  *  Also, some non-supported scenarios are detected.
 316  */
 317
 318 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 319 {
 320         u32 dimm_mask = 0;
 321         int i;
 322
 323         /**
 324          * i945 supports two DIMMs, in two configurations:
 325          *
 326          * - single channel with two DIMMs
 327          * - dual channel with one DIMM per channel
 328          *
 329          * In practice dual channel mainboards have their SPD at 0x50/0x52
 330          * whereas single channel configurations have their SPD at 0x50/0x51.
 331          *
 332          * The capability register knows a lot about the channel configuration
 333          * but for now we stick with the information we gather via SPD.
 334          */
 335
 336         if (sdram_capabilities_dual_channel()) {
 337                 sysinfo->dual_channel = 1;
 338                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 339         } else {
 340                 sysinfo->dual_channel = 0;
 341                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 342         }
 343
 344         /**
 345          * Since we only support two DIMMs in total, there is a limited number
 346          * of combinations. This function returns the type of DIMMs.
 347          * return value:
 348          *   [0:7]  lower DIMM population
 349          *   [8-15] higher DIMM population
 350          *   [16]   dual channel?
 351          *
 352          * There are 5 different possible populations for a DIMM socket:
 353          * 1. x16 double sided (X16DS)
 354          * 2. x8 double sided  (X8DS)
 355          * 3. x16 single sided (X16SS)
 356          * 4. x8 double stacked (X8DDS)
 357          * 5. not populated (NC)
 358          *
 359          * For the return value we start counting at zero.
 360          *
 361          */
 362
 363         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 364                 u8 reg8, device = DIMM0 + i;
 365
 366                 /* Initialize the socket information with a sane value */
 367                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 368
 369                 /* Dual Channel not supported, but Channel 1? Bail out */
 370                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 371                         continue;
 372
 373                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 374                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 375                         continue;
 376
 377                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 378
 379                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 380                         printk(BIOS_DEBUG, "N/A\n");
 381                         continue;
 382                 }
 383
 384                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 385                 if (reg8 == ERROR_SCHEME_ECC)
 386                         die("Error: ECC memory not supported by this chipset\n");
 387
 388                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 389                 if (reg8 & MODULE_BUFFERED)
 390                         die("Error: Buffered memory not supported by this chipset\n");
 391                 if (reg8 & MODULE_REGISTERED)
 392                         die("Error: Registered memory not supported by this chipset\n");
 393
 394                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 395                 case 0x08:
 396                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 397                         case 1:
 398                                 printk(BIOS_DEBUG, "x8DDS\n");
 399                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 400                                 break;
 401                         case 0:
 402                                 printk(BIOS_DEBUG, "x8DS\n");
 403                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 404                                 break;
 405                         default:
 406                                 printk(BIOS_DEBUG, "Unsupported.\n");
 407                         }
 408                         break;
 409                 case 0x10:
 410                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 411                         case 1:
 412                                 printk(BIOS_DEBUG, "x16DS\n");
 413                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 414                                 break;
 415                         case 0:
 416                                 printk(BIOS_DEBUG, "x16SS\n");
 417                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 418                                 break;
 419                         default:
 420                                 printk(BIOS_DEBUG, "Unsupported.\n");
 421                         }
 422                         break;
 423                 default:
 424                         die("Unsupported DDR-II memory width.\n");
 425                 }
 426
 427                 dimm_mask |= (1 << i);
 428         }
 429
 430         if (!dimm_mask) {
 431                 die("No memory installed.\n");
 432         }
 433
 434         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 435                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 436         }
 437 }
 438
 439 /**
 440  * @brief determine if any DIMMs are stacked
 441  *
 442  * @param sysinfo central sysinfo data structure.
 443  */
 444 static void sdram_verify_package_type(struct sys_info * sysinfo)
 445 {
 446         int i;
 447
 448         /* Assume no stacked DIMMs are available until we find one */
 449         sysinfo->package = 0;
 450         for (i=0; i<2*DIMM_SOCKETS; i++) {
 451                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 452                         continue;
 453
 454                 /* Is the current DIMM a stacked DIMM? */
 455                 if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 456                         sysinfo->package = 1;
 457         }
 458 }
 459
 460 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 461 {
 462         int i;
 463         u8 cas_mask;
 464
 465         /* Setup CAS mask with all supported CAS Latencies */
 466         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 467                    SPD_CAS_LATENCY_DDR2_4 |
 468                    SPD_CAS_LATENCY_DDR2_5;
 469
 470         for (i=0; i<2*DIMM_SOCKETS; i++) {
 471                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 472                         cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 473         }
 474
 475         if(!cas_mask) {
 476                 die("No DDR-II modules with accepted CAS latencies found.\n");
 477         }
 478
 479         return cas_mask;
 480 }
 481
 482 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 483 {
 484         int i, j, idx;
 485         int lowest_common_cas = 0;
 486         int max_ram_speed = 0;
 487
 488         const u8 ddr2_speeds_table[] = {
 489                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 490                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 491                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 492         };
 493
 494         const u8 spd_lookup_table[] = {
 495                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 496                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 497                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 498         };
 499
 500         switch (sdram_capabilities_max_supported_memory_frequency()) {
 501         case 400: max_ram_speed = 0; break;
 502         case 533: max_ram_speed = 1; break;
 503         case 667: max_ram_speed = 2; break;
 504         }
 505
 506         if (fsbclk() == 533)
 507                 max_ram_speed = 1;
 508
 509         sysinfo->memory_frequency = 0;
 510         sysinfo->cas = 0;
 511
 512         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 513                 lowest_common_cas = 3;
 514         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 515                 lowest_common_cas = 4;
 516         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 517                 lowest_common_cas = 5;
 518         }
 519         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 520
 521         for (j = max_ram_speed; j>=0; j--) {
 522                 int freq_cas_mask = cas_mask;
 523
 524                 PRINTK_DEBUG("Probing Speed %d\n", j);
 525                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 526                         int current_cas_mask;
 527
 528                         PRINTK_DEBUG("  DIMM: %d\n", i);
 529                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 530                                 continue;
 531                         }
 532
 533                         current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 534
 535                         while (current_cas_mask) {
 536                                 int highest_supported_cas = 0, current_cas = 0;
 537                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 538                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 539                                         highest_supported_cas = 5;
 540                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 541                                         highest_supported_cas = 4;
 542                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 543                                         highest_supported_cas = 3;
 544                                 }
 545                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 546                                         current_cas = 3;
 547                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 548                                         current_cas = 4;
 549                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 550                                         current_cas = 5;
 551                                 }
 552
 553                                 idx = highest_supported_cas - current_cas;
 554                                 PRINTK_DEBUG("idx=%d, ", idx);
 555                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
 556                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
 557
 558                                 if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 559                                                 spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 560                                         PRINTK_DEBUG(":    OK\n");
 561                                         break;
 562                                 }
 563
 564                                 PRINTK_DEBUG(":    Not fast enough!\n");
 565
 566                                 current_cas_mask &= ~(1 << (current_cas));
 567                         }
 568
 569                         freq_cas_mask &= current_cas_mask;
 570                         if (!current_cas_mask) {
 571                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 572                                 break;
 573                         }
 574                 }
 575                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 576                 if (freq_cas_mask) {
 577                         switch (j) {
 578                         case 0: sysinfo->memory_frequency = 400; break;
 579                         case 1: sysinfo->memory_frequency = 533; break;
 580                         case 2: sysinfo->memory_frequency = 667; break;
 581                         }
 582                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 583                                 sysinfo->cas = 3;
 584                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 585                                 sysinfo->cas = 4;
 586                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 587                                 sysinfo->cas = 5;
 588                         }
 589                         break;
 590                 }
 591         }
 592
 593         if (sysinfo->memory_frequency && sysinfo->cas) {
 594                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 595                                 sysinfo->memory_frequency, sysinfo->cas);
 596         } else {
 597                 die("Could not find common memory frequency and CAS\n");
 598         }
 599 }
 600
 601 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 602 {
 603         int i;
 604         int tRAS_time;
 605         int tRAS_cycles;
 606         int freq_multiplier = 0;
 607
 608         switch (sysinfo->memory_frequency) {
 609         case 400: freq_multiplier = 0x14; break; /* 5ns */
 610         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 611         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 612         }
 613
 614         tRAS_cycles = 4; /* 4 clocks minimum */
 615         tRAS_time = tRAS_cycles * freq_multiplier;
 616
 617         for (i=0; i<2*DIMM_SOCKETS; i++) {
 618                 u8 reg8;
 619
 620                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 621                         continue;
 622
 623                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 624                 if (!reg8) {
 625                         die("Invalid tRAS value.\n");
 626                 }
 627
 628                 while ((tRAS_time >> 2) < reg8) {
 629                         tRAS_time += freq_multiplier;
 630                         tRAS_cycles++;
 631                 }
 632         }
 633         if(tRAS_cycles > 0x18) {
 634                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 635         }
 636
 637         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 638         sysinfo->tras = tRAS_cycles;
 639 }
 640
 641 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 642 {
 643         int i;
 644         int tRP_time;
 645         int tRP_cycles;
 646         int freq_multiplier = 0;
 647
 648         switch (sysinfo->memory_frequency) {
 649         case 400: freq_multiplier = 0x14; break; /* 5ns */
 650         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 651         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 652         }
 653
 654         tRP_cycles = 2; /* 2 clocks minimum */
 655         tRP_time = tRP_cycles * freq_multiplier;
 656
 657         for (i=0; i<2*DIMM_SOCKETS; i++) {
 658                 u8 reg8;
 659
 660                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 661                         continue;
 662
 663                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
 664                 if (!reg8) {
 665                         die("Invalid tRP value.\n");
 666                 }
 667
 668                 while (tRP_time < reg8) {
 669                         tRP_time += freq_multiplier;
 670                         tRP_cycles++;
 671                 }
 672         }
 673
 674         if(tRP_cycles > 6) {
 675                 die("DDR-II Module does not support this frequency (tRP error)\n");
 676         }
 677
 678         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 679         sysinfo->trp = tRP_cycles;
 680 }
 681
 682 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 683 {
 684         int i;
 685         int tRCD_time;
 686         int tRCD_cycles;
 687         int freq_multiplier = 0;
 688
 689         switch (sysinfo->memory_frequency) {
 690         case 400: freq_multiplier = 0x14; break; /* 5ns */
 691         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 692         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 693         }
 694
 695         tRCD_cycles = 2; /* 2 clocks minimum */
 696         tRCD_time = tRCD_cycles * freq_multiplier;
 697
 698         for (i=0; i<2*DIMM_SOCKETS; i++) {
 699                 u8 reg8;
 700
 701                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 702                         continue;
 703
 704                 reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
 705                 if (!reg8) {
 706                         die("Invalid tRCD value.\n");
 707                 }
 708
 709                 while (tRCD_time < reg8) {
 710                         tRCD_time += freq_multiplier;
 711                         tRCD_cycles++;
 712                 }
 713         }
 714         if(tRCD_cycles > 6) {
 715                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 716         }
 717
 718         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 719         sysinfo->trcd = tRCD_cycles;
 720 }
 721
 722 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 723 {
 724         int i;
 725         int tWR_time;
 726         int tWR_cycles;
 727         int freq_multiplier = 0;
 728
 729         switch (sysinfo->memory_frequency) {
 730         case 400: freq_multiplier = 0x14; break; /* 5ns */
 731         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 732         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 733         }
 734
 735         tWR_cycles = 2; /* 2 clocks minimum */
 736         tWR_time = tWR_cycles * freq_multiplier;
 737
 738         for (i=0; i<2*DIMM_SOCKETS; i++) {
 739                 u8 reg8;
 740
 741                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 742                         continue;
 743
 744                 reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
 745                 if (!reg8) {
 746                         die("Invalid tWR value.\n");
 747                 }
 748
 749                 while (tWR_time < reg8) {
 750                         tWR_time += freq_multiplier;
 751                         tWR_cycles++;
 752                 }
 753         }
 754         if(tWR_cycles > 5) {
 755                 die("DDR-II Module does not support this frequency (tWR error)\n");
 756         }
 757
 758         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 759         sysinfo->twr = tWR_cycles;
 760 }
 761
 762 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 763 {
 764         int i, index = 0;
 765
 766         const u8 tRFC_cycles[] = {
 767              /* 75 105 127.5 */
 768                 15, 21, 26,     /* DDR2-400 */
 769                 20, 28, 34,     /* DDR2-533 */
 770                 25, 35, 43      /* DDR2-667 */
 771         };
 772
 773         for (i=0; i<2*DIMM_SOCKETS; i++) {
 774                 u8 reg8;
 775
 776                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 777                         continue;
 778
 779                 reg8 = sysinfo->banksize[i*2];
 780                 switch (reg8) {
 781                 case 0x04: reg8 = 0; break;
 782                 case 0x08: reg8 = 1; break;
 783                 case 0x10: reg8 = 2; break;
 784                 case 0x20: reg8 = 3; break;
 785                 }
 786
 787                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 788                         reg8++;
 789
 790                 if (reg8 > 3) {
 791                         /* Can this happen? Go back to 127.5ns just to be sure
 792                          * we don't run out of the array. This may be wrong
 793                          */
 794                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 795                         reg8 = 3;
 796                 }
 797
 798                 if (reg8 > index)
 799                         index = reg8;
 800
 801         }
 802         index--;
 803         switch (sysinfo->memory_frequency) {
 804         case 667: index += 3; /* Fallthrough */
 805         case 533: index += 3; /* Fallthrough */
 806         case 400: break;
 807         }
 808
 809         sysinfo->trfc = tRFC_cycles[index];
 810         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 811 }
 812
 813 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 814 {
 815         int i;
 816
 817         sysinfo->refresh = 0;
 818
 819         for (i=0; i<2*DIMM_SOCKETS; i++) {
 820                 int refresh;
 821
 822                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 823                         continue;
 824
 825                 refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
 826
 827                 /* 15.6us */
 828                 if (!refresh)
 829                         continue;
 830
 831                 /* Refresh is slower than 15.6us, use 15.6us */
 832                 if (refresh > 2)
 833                         continue;
 834
 835                 if (refresh == 2) {
 836                         sysinfo->refresh = 1;
 837                         break;
 838                 }
 839
 840                 die("DDR-II module has unsupported refresh value\n");
 841         }
 842         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 843 }
 844
 845 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 846 {
 847         int i;
 848
 849         for (i=0; i<2*DIMM_SOCKETS; i++) {
 850                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 851                         continue;
 852
 853                 if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 854                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 855         }
 856 }
 857
 858 static void sdram_program_dram_width(struct sys_info * sysinfo)
 859 {
 860         u16 c0dramw=0, c1dramw=0;
 861         int idx;
 862
 863         if (sysinfo->dual_channel)
 864                 idx = 2;
 865         else
 866                 idx = 1;
 867
 868         switch (sysinfo->dimm[0]) {
 869         case 0: c0dramw = 0x0000; break; /* x16DS */
 870         case 1: c0dramw = 0x0001; break; /* x8DS */
 871         case 2: c0dramw = 0x0000; break; /* x16SS */
 872         case 3: c0dramw = 0x0005; break; /* x8DDS */
 873         case 4: c0dramw = 0x0000; break; /* NC */
 874         }
 875
 876         switch (sysinfo->dimm[idx]) {
 877         case 0: c1dramw = 0x0000; break; /* x16DS */
 878         case 1: c1dramw = 0x0010; break; /* x8DS */
 879         case 2: c1dramw = 0x0000; break; /* x16SS */
 880         case 3: c1dramw = 0x0050; break; /* x8DDS */
 881         case 4: c1dramw = 0x0000; break; /* NC */
 882         }
 883
 884         if ( !sdram_capabilities_dual_channel() ) {
 885                 /* Single Channel */
 886                 c0dramw |= c1dramw;
 887                 c1dramw = 0;
 888         }
 889
 890         MCHBAR16(C0DRAMW) = c0dramw;
 891         MCHBAR16(C1DRAMW) = c1dramw;
 892 }
 893
 894 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 895 {
 896         int i;
 897
 898         for (i=0; i<16; i++)
 899                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 900 }
 901
 902 static const u32 dq2030[] = {
 903         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 904         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 905         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 906         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 907 };
 908
 909 static const u32 dq2330[] = {
 910         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 911         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 912         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 913         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 914 };
 915
 916 static const u32 cmd2710[] = {
 917         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 918         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 919         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 920         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 921 };
 922
 923 static const u32 cmd3210[] = {
 924         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 925         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 926         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 927         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 928 };
 929
 930 static const u32 clk2030[] = {
 931         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 932         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 933         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 934         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 935 };
 936
 937 static const u32 ctl3215[] = {
 938         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 939         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 940         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 941         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 942 };
 943
 944 static const u32 ctl3220[] = {
 945         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 946         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 947         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 948         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 949 };
 950
 951 static const u32 nc[] = {
 952         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 953         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 954         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 955         0x00000000, 0x00000000, 0x00000000, 0x00000000
 956 };
 957
 958 enum {
 959         DQ2030,
 960         DQ2330,
 961         CMD2710,
 962         CMD3210,
 963         CLK2030,
 964         CTL3215,
 965         CTL3220,
 966         NC,
 967 };
 968
 969 static const u8 dual_channel_slew_group_lookup[] = {
 970         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 971         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 972         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 973         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 974         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 975
 976         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 977         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 978         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 979         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 980         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 981
 982         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 983         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 984         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 985         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 986         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 987
 988         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 989         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 990         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 991         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 992         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 993
 994         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 995         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 996         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 997         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 998 };
 999
1000 static const u8 single_channel_slew_group_lookup[] = {
1001         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1002         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1003         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1004         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1005         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1006
1007         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1008         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1009         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1010         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1011         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1012
1013         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1014         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1015         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1016         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1017         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1018
1019         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1020         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1021         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1022         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1023         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1024
1025         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1026         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1027         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1028         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
1029 };
1030
1031 static const u32 *slew_group_lookup(int dual_channel, int index)
1032 {
1033         const u8 *slew_group;
1034         /* Dual Channel needs different tables. */
1035         if (dual_channel)
1036                 slew_group   = dual_channel_slew_group_lookup;
1037         else
1038                 slew_group   = single_channel_slew_group_lookup;
1039
1040         switch (slew_group[index]) {
1041         case DQ2030:    return dq2030;
1042         case DQ2330:    return dq2330;
1043         case CMD2710:   return cmd2710;
1044         case CMD3210:   return cmd3210;
1045         case CLK2030:   return clk2030;
1046         case CTL3215:   return ctl3215;
1047         case CTL3220:   return ctl3220;
1048         case NC:        return nc;
1049         }
1050
1051         return nc;
1052 }
1053
1054 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
1055 /* Strength multiplier tables */
1056 static const u8 dual_channel_strength_multiplier[] = {
1057         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1058         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1059         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1060         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1061         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1062         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1063         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1064         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1065         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1066         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1067         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1068         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1069         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1070         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1071         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1072         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1073         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1074         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1075         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1076         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1077         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1078         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1079         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1080         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1081 };
1082
1083 static const u8 single_channel_strength_multiplier[] = {
1084         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1085         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1086         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1087         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1088         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1089         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1090         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1091         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1092         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1093         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1094         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1095         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1096         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1097         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1098         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1099         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1100         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1101         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1102         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1103         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1104         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1105         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1106         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1107         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1108 };
1109 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
1110 static const u8 dual_channel_strength_multiplier[] = {
1111         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1112         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1113         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1114         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1115         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1116         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1117         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1118         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1119         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1120         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1121         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1122         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1123         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1124         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1125         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1126         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1127         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1128         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1129         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1130         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1131         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1132         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1133         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1134         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1135 };
1136
1137 static const u8 single_channel_strength_multiplier[] = {
1138         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1139         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1141         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1142         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1143         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1144         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1145         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1146         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1147         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1148         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1149         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1151         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1152         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1153         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1154         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1155         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1156         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1157         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1158         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1159         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1160         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1161         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1162 };
1163 #endif
1164
1165 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1166 {
1167         const u8 * strength_multiplier;
1168         int idx, dual_channel;
1169
1170         /* Set Strength Multipliers */
1171
1172         /* Dual Channel needs different tables. */
1173         if (sdram_capabilities_dual_channel()) {
1174                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1175                 strength_multiplier = dual_channel_strength_multiplier;
1176                 dual_channel = 1;
1177                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1178         } else {
1179                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1180                 strength_multiplier = single_channel_strength_multiplier;
1181                 dual_channel = 0;
1182                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1183         }
1184
1185         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1186
1187         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1188         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1189         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1190         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1191         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1192         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1193         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1194         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1195
1196         /* Channel 0 */
1197         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1198         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1199         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1200
1201                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1202         } else {
1203                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1204         }
1205         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1206         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1207         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1208
1209         /* Channel 1 */
1210         if (sysinfo->dual_channel) {
1211                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1212                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1213         } else {
1214                 sdram_write_slew_rates(G7SRPUT, nc);
1215                 sdram_write_slew_rates(G8SRPUT, nc);
1216         }
1217 }
1218
1219 static void sdram_enable_rcomp(void)
1220 {
1221         u32 reg32;
1222         /* Enable Global Periodic RCOMP */
1223         udelay(300);
1224         reg32 = MCHBAR32(GBRCOMPCTL);
1225         reg32 &= ~(1 << 23);
1226         MCHBAR32(GBRCOMPCTL) = reg32;
1227 }
1228
1229 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1230 {
1231         u32 chan0dll = 0, chan1dll = 0;
1232         int i;
1233
1234         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1235
1236         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1237         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1238
1239         /* We drive both channels with the same speed */
1240         switch (sysinfo->memory_frequency) {
1241         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1242         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1243         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1244         }
1245
1246         for (i=0; i < 4; i++) {
1247                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1248                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1249                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1250                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1251         }
1252 }
1253
1254 static void sdram_force_rcomp(void)
1255 {
1256         u32 reg32;
1257         u8 reg8;
1258
1259         reg32 = MCHBAR32(ODTC);
1260         reg32 |= (1 << 28);
1261         MCHBAR32(ODTC) = reg32;
1262
1263         reg32 = MCHBAR32(SMSRCTL);
1264         reg32 |= (1 << 0);
1265         MCHBAR32(SMSRCTL) = reg32;
1266
1267         /* Start initial RCOMP */
1268         reg32 = MCHBAR32(GBRCOMPCTL);
1269         reg32 |= (1 << 8);
1270         MCHBAR32(GBRCOMPCTL) = reg32;
1271
1272         reg8 = i945_silicon_revision();
1273         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1274
1275                 reg32 = MCHBAR32(GBRCOMPCTL);
1276                 reg32 |= (3 << 5);
1277                 MCHBAR32(GBRCOMPCTL) = reg32;
1278         }
1279 }
1280
1281 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1282 {
1283         u8 reg8;
1284         u32 reg32;
1285
1286         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1287         /* Enable Data Half Clock Pushout */
1288         reg8 = MCHBAR8(C0HCTC);
1289         reg8 &= ~0x1f;
1290         reg8 |= ( 1 << 0);
1291         MCHBAR8(C0HCTC) = reg8;
1292
1293         reg8 = MCHBAR8(C1HCTC);
1294         reg8 &= ~0x1f;
1295         reg8 |= ( 1 << 0);
1296         MCHBAR8(C1HCTC) = reg8;
1297
1298         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1299         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1300
1301         MCHBAR8(C0WDLLCMC) = 0;
1302         MCHBAR8(C1WDLLCMC) = 0;
1303
1304         /* Program RCOMP Settings */
1305         sdram_program_dram_width(sysinfo);
1306
1307         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1308
1309         /* Indicate that RCOMP programming is done */
1310         reg32 = MCHBAR32(GBRCOMPCTL);
1311         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1312         reg32 |= (3 << 27) | (3 << 0);
1313         MCHBAR32(GBRCOMPCTL) = reg32;
1314
1315         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1316
1317         /* Program DLL Timings */
1318         sdram_program_dll_timings(sysinfo);
1319
1320         /* Force RCOMP cycle */
1321         sdram_force_rcomp();
1322 }
1323
1324 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1325 {
1326         u32 reg32;
1327
1328         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1329
1330         reg32 = MCHBAR32(RCVENMT);
1331         reg32 &= ~(0x3f << 6);
1332         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1333
1334         reg32 |= (1 << 11) | (1 << 9);
1335         MCHBAR32(RCVENMT) = reg32;
1336
1337         reg32 = MCHBAR32(DRTST);
1338         reg32 |= (1 << 3) | (1 << 2);
1339         MCHBAR32(DRTST) = reg32;
1340
1341         reg32 = MCHBAR32(DRTST);
1342         reg32 |= (1 << 6) | (1 << 4);
1343         MCHBAR32(DRTST) = reg32;
1344
1345         asm volatile ("nop; nop;" ::: "memory");
1346
1347         reg32 = MCHBAR32(DRTST);
1348
1349         /* Is channel 0 populated? */
1350         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1351                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1352                 reg32 |= (1 << 7) | (1 << 5);
1353         else
1354                 reg32 |= (1 << 31);
1355
1356         /* Is channel 1 populated? */
1357         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1358                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1359                 reg32 |= (1 << 9) | (1 << 8);
1360         else
1361                 reg32 |= (1 << 30);
1362
1363         MCHBAR32(DRTST) = reg32;
1364
1365         /* Activate DRAM Channel IO Buffers */
1366         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1367                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1368                 reg32 = MCHBAR32(C0DRC1);
1369                 reg32 |= (1 << 8);
1370                 MCHBAR32(C0DRC1) = reg32;
1371         }
1372         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1373                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1374                 reg32 = MCHBAR32(C1DRC1);
1375                 reg32 |= (1 << 8);
1376                 MCHBAR32(C1DRC1) = reg32;
1377         }
1378 }
1379
1380 struct dimm_size {
1381         unsigned long side1;
1382         unsigned long side2;
1383 };
1384
1385 static struct dimm_size sdram_get_dimm_size(u16 device)
1386 {
1387         /* Calculate the log base 2 size of a DIMM in bits */
1388         struct dimm_size sz;
1389         int value, low, rows, columns;
1390
1391         sz.side1 = 0;
1392         sz.side2 = 0;
1393
1394         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1395         if (rows < 0) goto hw_err;
1396         if ((rows & 0xf) == 0) goto val_err;
1397         sz.side1 += rows & 0xf;
1398
1399         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1400         if (columns < 0) goto hw_err;
1401         if ((columns & 0xf) == 0) goto val_err;
1402         sz.side1 += columns & 0xf;
1403
1404         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1405         if (value < 0) goto hw_err;
1406         if ((value & 0xff) == 0) goto val_err;
1407         sz.side1 += log2(value & 0xff);
1408
1409         /* Get the module data width and convert it to a power of two */
1410         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1411         if (value < 0) goto hw_err;
1412         value &= 0xff;
1413         value <<= 8;
1414
1415         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1416         if (low < 0) goto hw_err;
1417         value = value | (low & 0xff);
1418         if ((value != 72) && (value != 64)) goto val_err;
1419         sz.side1 += log2(value);
1420
1421         /* side 2 */
1422         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1423
1424         if (value < 0) goto hw_err;
1425         value &= 7;
1426         value++;
1427         if (value == 1) goto out;
1428         if (value != 2) goto val_err;
1429
1430         /* Start with the symmetrical case */
1431         sz.side2 = sz.side1;
1432
1433         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1434
1435         /* Don't die here, I have not come across any of these to test what
1436          * actually happens.
1437          */
1438         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1439
1440         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1441         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1442
1443         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1444         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1445
1446         goto out;
1447
1448  val_err:
1449         die("Bad SPD value\n");
1450  hw_err:
1451         /* If a hardware error occurs the spd rom probably does not exist.
1452          * In this case report that there is no memory
1453          */
1454         sz.side1 = 0;
1455         sz.side2 = 0;
1456  out:
1457         return sz;
1458 }
1459
1460 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1461 {
1462         int i;
1463
1464         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1465                 struct dimm_size sz;
1466
1467                 sysinfo->banksize[i * 2] = 0;
1468                 sysinfo->banksize[(i * 2) + 1] = 0;
1469
1470                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1471                         continue;
1472
1473                 sz = sdram_get_dimm_size(DIMM0 + i);
1474
1475                 sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1476
1477                 if (sz.side1 < 30)
1478                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1479
1480                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1481
1482                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1483
1484                 if (!sz.side2)
1485                         continue;
1486
1487                 /* If there is a second side, it has to have at least 128M, too */
1488                 if (sz.side2 < 30)
1489                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1490
1491                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1492
1493                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1494         }
1495 }
1496
1497 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1498 {
1499         int i;
1500         int cum0, cum1, tolud, tom;
1501
1502         printk(BIOS_DEBUG, "Setting RAM size... \n");
1503
1504         cum0 = 0;
1505         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1506                 cum0 += sysinfo->banksize[i];
1507                 MCHBAR8(C0DRB0+i) = cum0;
1508         }
1509
1510         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1511         cum1 = cum0;
1512
1513         /* Exception: Interleaved starts from the beginning */
1514         if (sysinfo->interleaved)
1515                 cum1 = 0;
1516
1517 #if 0
1518         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1519         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1520                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1521                 cum1 = 0;
1522 #endif
1523
1524         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1525                 cum1 += sysinfo->banksize[i + 4];
1526                 MCHBAR8(C1DRB0+i) = cum1;
1527         }
1528
1529         /* Set TOLUD Top Of Low Usable DRAM */
1530         if (sysinfo->interleaved)
1531                 tolud = (cum0 + cum1) << 1;
1532         else
1533                 tolud = (cum1 ? cum1 : cum0)  << 1;
1534
1535         /* The TOM register has a different format */
1536         tom = tolud >> 3;
1537
1538         /* Limit the value of TOLUD to leave some space for PCI memory. */
1539         if (tolud > 0xd0)
1540                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1541
1542         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1543
1544         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1545         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1546         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1547
1548         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1549
1550         return 0;
1551 }
1552
1553 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1554 {
1555         int i, value;
1556         u16 dra0=0, dra1=0, dra = 0;
1557
1558         printk(BIOS_DEBUG, "Setting row attributes... \n");
1559         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1560                 u16 device;
1561                 u8 columnsrows;
1562
1563                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1564                         continue;
1565                 }
1566
1567                 device = DIMM0 + i;
1568
1569                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1570                 columnsrows = (value & 0x0f);
1571
1572                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1573                 columnsrows |= (value & 0xf) << 4;
1574
1575                 switch (columnsrows) {
1576                 case 0x9d: dra = 2; break;
1577                 case 0xad: dra = 3; break;
1578                 case 0xbd: dra = 4; break;
1579                 case 0xae: dra = 3; break;
1580                 case 0xbe: dra = 4; break;
1581                 default: die("Unsupported Rows/Columns. (DRA)");
1582                 }
1583
1584                 /* Double Sided DIMMs? */
1585                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1586                         dra = (dra << 4) | dra;
1587                 }
1588
1589                 if (i < DIMM_SOCKETS)
1590                         dra0 |= (dra << (i*8));
1591                 else
1592                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1593         }
1594
1595         MCHBAR16(C0DRA0) = dra0;
1596         MCHBAR16(C1DRA0) = dra1;
1597
1598         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1599         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1600
1601         return 0;
1602 }
1603
1604 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1605 {
1606         u32 off32;
1607         int i;
1608
1609         MCHBAR16(C1BNKARC) &= 0xff00;
1610         MCHBAR16(C0BNKARC) &= 0xff00;
1611
1612         off32 = C0BNKARC;
1613         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1614                 /* Switch to second channel */
1615                 if (i == DIMM_SOCKETS)
1616                         off32 = C1BNKARC;
1617
1618                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1619                         continue;
1620
1621                 if (sysinfo->banks[i] != 8)
1622                         continue;
1623
1624                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1625
1626                 if (i & 1)
1627                         MCHBAR16(off32) |= 0x50;
1628                 else
1629                         MCHBAR16(off32) |= 0x05;
1630         }
1631 }
1632
1633 #define REFRESH_7_8US   1
1634 #define REFRESH_15_6US  0
1635 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1636 {
1637         u32 reg32;
1638
1639         if (sysinfo->refresh == REFRESH_7_8US) {
1640                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1641         } else {
1642                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1643         }
1644
1645         MCHBAR32(C0DRC0) &= ~(7 << 8);
1646         MCHBAR32(C0DRC0) |= reg32;
1647
1648         MCHBAR32(C1DRC0) &= ~(7 << 8);
1649         MCHBAR32(C1DRC0) |= reg32;
1650 }
1651
1652 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1653 {
1654         u32 reg32;
1655         int i;
1656
1657         reg32 = MCHBAR32(C0DRC1);
1658
1659         for (i=0; i < 4; i++) {
1660                 if (sysinfo->banksize[i] == 0) {
1661                         reg32 |= (1 << (16 + i));
1662                 }
1663         }
1664
1665         reg32 |= (1 << 12);
1666
1667         reg32 |= (1 << 11);
1668         MCHBAR32(C0DRC1) = reg32;
1669
1670         /* Do we have to do this if we're in Single Channel Mode?  */
1671         reg32 = MCHBAR32(C1DRC1);
1672
1673         for (i=4; i < 8; i++) {
1674                 if (sysinfo->banksize[i] == 0) {
1675                         reg32 |= (1 << (12 + i));
1676                 }
1677         }
1678
1679         reg32 |= (1 << 12);
1680
1681         reg32 |= (1 << 11);
1682         MCHBAR32(C1DRC1) = reg32;
1683 }
1684
1685 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1686 {
1687         u32 reg32;
1688         int i;
1689
1690         reg32 = MCHBAR32(C0DRC2);
1691
1692         for (i=0; i < 4; i++) {
1693                 if (sysinfo->banksize[i] == 0) {
1694                         reg32 |= (1 << (24 + i));
1695                 }
1696         }
1697         MCHBAR32(C0DRC2) = reg32;
1698
1699         reg32 = MCHBAR32(C1DRC2);
1700
1701         for (i=4; i < 8; i++) {
1702                 if (sysinfo->banksize[i] == 0) {
1703                         reg32 |= (1 << (20 + i));
1704                 }
1705         }
1706         MCHBAR32(C1DRC2) = reg32;
1707 }
1708
1709 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1710 {
1711         u32 reg32, off32;
1712         u32 tWTR;
1713         u32 temp_drt;
1714         int i, page_size;
1715
1716         static const u8 const drt0_table[] = {
1717           /* CL 3, 4, 5 */
1718                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1719                 4, 5, 6,        /* FSB667, DDR533/400 */
1720                 4, 5, 6,        /* FSB667, DDR667 */
1721         };
1722
1723         static const u8 const cas_table[] = {
1724                 2, 1, 0, 3
1725         };
1726
1727         reg32 = MCHBAR32(C0DRC0);
1728         reg32 |= (1 << 2);      /* Burst Length 8 */
1729         reg32 &= ~( (1 << 13) | (1 << 12) );
1730         MCHBAR32(C0DRC0) = reg32;
1731
1732         reg32 = MCHBAR32(C1DRC0);
1733         reg32 |= (1 << 2);      /* Burst Length 8 */
1734         reg32 &= ~( (1 << 13) | (1 << 12) );
1735         MCHBAR32(C1DRC0) = reg32;
1736
1737         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1738                         SYSINFO_DIMM_NOT_POPULATED) {
1739                 reg32 = MCHBAR32(C0DRC0);
1740                 reg32 |= (1 << 15);
1741                 MCHBAR32(C0DRC0) = reg32;
1742         }
1743
1744         sdram_program_refresh_rate(sysinfo);
1745
1746         sdram_program_cke_tristate(sysinfo);
1747
1748         sdram_program_odt_tristate(sysinfo);
1749
1750         /* Calculate DRT0 */
1751
1752         temp_drt = 0;
1753
1754         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1755         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1756         temp_drt |= (reg32 << 28);
1757
1758         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1759         reg32 += sysinfo->trp;
1760         temp_drt |= (reg32 << 4);
1761
1762         if (sysinfo->memory_frequency == 667) {
1763                 tWTR = 3; /* 667MHz */
1764         } else {
1765                 tWTR = 2; /* 400 and 533 */
1766         }
1767
1768         /* B2B Write to Read Command Spacing */
1769         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1770         temp_drt |= (reg32 << 24);
1771
1772         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1773         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1774
1775         /* Program Write Auto Precharge to Activate */
1776         off32 = 0;
1777         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1778                 off32 += 3;
1779         }
1780         if (sysinfo->memory_frequency == 667) {
1781                 off32 += 3;
1782         }
1783         off32 += sysinfo->cas - 3;
1784         reg32 = drt0_table[off32];
1785         temp_drt |= (reg32 << 11);
1786
1787         /* Read Auto Precharge to Activate */
1788
1789         temp_drt |= (8 << 0);
1790
1791         MCHBAR32(C0DRT0) = temp_drt;
1792         MCHBAR32(C1DRT0) = temp_drt;
1793
1794         /* Calculate DRT1 */
1795
1796         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1797
1798         /* DRAM RASB Precharge */
1799         temp_drt |= (sysinfo->trp - 2) << 0;
1800
1801         /* DRAM RASB to CASB Delay */
1802         temp_drt |= (sysinfo->trcd - 2) << 4;
1803
1804         /* CASB Latency */
1805         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1806
1807         /* Refresh Cycle Time */
1808         temp_drt |= (sysinfo->trfc) << 10;
1809
1810         /* Pre-All to Activate Delay */
1811         temp_drt |= (0 << 16);
1812
1813         /* Precharge to Precharge Delay stays at 1 clock */
1814         temp_drt |= (0 << 18);
1815
1816         /* Activate to Precharge Delay */
1817         temp_drt |= (sysinfo->tras << 19);
1818
1819         /* Read to Precharge (tRTP) */
1820         if (sysinfo->memory_frequency == 667) {
1821                 temp_drt |= (1 << 28);
1822         } else {
1823                 temp_drt |= (0 << 28);
1824         }
1825
1826         /* Determine page size */
1827         reg32 = 0;
1828         page_size = 1; /* Default: 1k pagesize */
1829         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1830                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1831                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1832                         page_size = 2; /* 2k pagesize */
1833         }
1834
1835         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1836                 reg32 = 1;
1837         }
1838         if (sysinfo->memory_frequency == 667) {
1839                 reg32 = page_size;
1840         }
1841
1842         temp_drt |= (reg32 << 30);
1843
1844         MCHBAR32(C0DRT1) = temp_drt;
1845         MCHBAR32(C1DRT1) = temp_drt;
1846
1847         /* Program DRT2 */
1848         reg32 = MCHBAR32(C0DRT2);
1849         reg32 &= ~(1 << 8);
1850         MCHBAR32(C0DRT2) = reg32;
1851
1852         reg32 = MCHBAR32(C1DRT2);
1853         reg32 &= ~(1 << 8);
1854         MCHBAR32(C1DRT2) = reg32;
1855
1856         /* Calculate DRT3 */
1857         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1858
1859         /* Get old tRFC value */
1860         reg32 = MCHBAR32(C0DRT1) >> 10;
1861         reg32 &= 0x3f;
1862
1863         /* 788nS - tRFC */
1864         switch (sysinfo->memory_frequency) {
1865         case 400: /* 5nS */
1866                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1867                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1868                 break;
1869         case 533: /* 3.75nS */
1870                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1871                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1872                 break;
1873         case 667: /* 3nS */
1874                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1875                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1876                 break;
1877         }
1878
1879         temp_drt |= reg32;
1880
1881         MCHBAR32(C0DRT3) = temp_drt;
1882         MCHBAR32(C1DRT3) = temp_drt;
1883 }
1884
1885 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1886 {
1887         u32 reg32;
1888
1889         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1890
1891         if (sdram_capabilities_interleave() &&
1892                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1893                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1894                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1895                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1896                 /* Both channels equipped with DIMMs of the same size */
1897                 sysinfo->interleaved = 1;
1898         } else {
1899                 sysinfo->interleaved = 0;
1900         }
1901
1902         reg32 = MCHBAR32(DCC);
1903         reg32 &= ~(7 << 0);
1904
1905         if(sysinfo->interleaved) {
1906                 /* Dual Channel Interleaved */
1907                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1908                 reg32 |= (1 << 1);
1909         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1910                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1911                 /* Channel 1 only */
1912                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1913                 reg32 |= (1 << 2);
1914         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1915                         SYSINFO_DIMM_NOT_POPULATED) {
1916                 /* Dual Channel Assymetric */
1917                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1918                 reg32 |= (1 << 0);
1919         } else {
1920                 /* All bits 0 means Single Channel 0 operation */
1921                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1922         }
1923
1924         /* Now disable channel XORing */
1925         reg32 |= (1 << 10);
1926
1927         MCHBAR32(DCC) = reg32;
1928
1929         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1930 }
1931
1932 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1933 {
1934         volatile u16 reg16;
1935
1936         MCHBAR32(PLLMON) = 0x80800000;
1937
1938         sysinfo->fsb_frequency = fsbclk();
1939         if (sysinfo->fsb_frequency == 0xffff)
1940                 die("Unsupported FSB speed");
1941
1942         /* Program CPCTL according to FSB speed */
1943         /* Only write the lower byte */
1944         switch (sysinfo->fsb_frequency) {
1945         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1946         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1947         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1948         }
1949
1950         MCHBAR16(CPCTL) &= ~(1 << 11);
1951
1952         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1953 }
1954
1955 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1956 {
1957         u8  reg8;
1958         u16 reg16;
1959         u8  freq, second_vco, voltage;
1960
1961 #define CRCLK_166MHz    0x00
1962 #define CRCLK_200MHz    0x01
1963 #define CRCLK_250MHz    0x03
1964 #define CRCLK_400MHz    0x05
1965
1966 #define CDCLK_200MHz    0x00
1967 #define CDCLK_320MHz    0x40
1968
1969 #define VOLTAGE_1_05    0x00
1970 #define VOLTAGE_1_50    0x01
1971
1972         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1973
1974         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1975
1976         voltage = VOLTAGE_1_05;
1977         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1978                 voltage = VOLTAGE_1_50;
1979         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1980
1981         /* Gate graphics hardware for frequency change */
1982         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1983         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1984         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1985
1986         /* Get graphics frequency capabilities */
1987         reg8 = sdram_capabilities_core_frequencies();
1988
1989         freq = CRCLK_250MHz;
1990         switch (reg8) {
1991         case GFX_FREQUENCY_CAP_ALL:
1992                 if (voltage == VOLTAGE_1_05)
1993                         freq = CRCLK_250MHz;
1994                 else
1995                         freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
1996                 break;
1997         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1998         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1999         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
2000         }
2001
2002         if (freq != CRCLK_400MHz) {
2003                 /* What chipset are we? Force 166MHz for GMS */
2004                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
2005                 if (reg8==2)
2006                         freq = CRCLK_166MHz;
2007         }
2008
2009         printk(BIOS_DEBUG, "Render: ");
2010         switch (freq) {
2011         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2012         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2013         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2014         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2015         }
2016
2017         if (i945_silicon_revision() == 0) {
2018                 sysinfo->mvco4x = 1;
2019         } else {
2020                 sysinfo->mvco4x = 0;
2021         }
2022
2023         second_vco = 0;
2024
2025         if (voltage == VOLTAGE_1_50) {
2026                 second_vco = 1;
2027         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
2028                 u16 mem = sysinfo->memory_frequency;
2029                 u16 fsb = sysinfo->fsb_frequency;
2030
2031                 if ( (fsb == 667 && mem == 533) ||
2032                      (fsb == 533 && mem == 533) ||
2033                      (fsb == 533 && mem == 400)) {
2034                         second_vco = 1;
2035                 }
2036
2037                 if (fsb == 667 && mem == 533)
2038                         sysinfo->mvco4x = 1;
2039         }
2040
2041         if (second_vco) {
2042                 sysinfo->clkcfg_bit7=1;
2043         } else {
2044                 sysinfo->clkcfg_bit7=0;
2045         }
2046
2047         /* Graphics Core Render Clock */
2048         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2049         reg16 &= ~( (7 << 0) | (1 << 13) );
2050         reg16 |= freq;
2051         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2052
2053         /* Graphics Core Display Clock */
2054         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2055         reg8 &= ~( (1<<7) | (7<<4) );
2056
2057         if (voltage == VOLTAGE_1_05) {
2058                 reg8 |= CDCLK_200MHz;
2059                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2060         } else {
2061                 reg8 |= CDCLK_320MHz;
2062                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2063         }
2064         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2065
2066         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2067
2068         reg8 |= (1<<3) | (1<<1);
2069         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2070
2071         reg8 |= 0x0f;
2072         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2073
2074         /* Ungate core render and display clocks */
2075         reg8 &= 0xf0;
2076         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2077 }
2078
2079 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2080 {
2081         u32 clkcfg;
2082         u8 reg8;
2083
2084         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2085
2086         clkcfg = MCHBAR32(CLKCFG);
2087
2088         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2089
2090         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2091
2092         if (sysinfo->mvco4x) {
2093                 printk(BIOS_DEBUG, "MVCO 4x, ");
2094                 clkcfg &= ~(1 << 12);
2095         }
2096
2097         if (sysinfo->clkcfg_bit7) {
2098                 printk(BIOS_DEBUG, "second VCO, ");
2099
2100                 clkcfg |= (1 << 7);
2101         }
2102
2103         switch (sysinfo->memory_frequency) {
2104         case 400: clkcfg |= (2 << 4); break;
2105         case 533: clkcfg |= (3 << 4); break;
2106         case 667: clkcfg |= (4 << 4); break;
2107         default: die("Target Memory Frequency Error");
2108         }
2109
2110         if (MCHBAR32(CLKCFG) == clkcfg) {
2111                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2112                 return;
2113         }
2114
2115         MCHBAR32(CLKCFG) = clkcfg;
2116
2117         /* Make sure the following code is in the
2118          * cache before we execute it.
2119          */
2120         goto cache_code;
2121 vco_update:
2122         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2123         reg8 &= ~(1 << 7);
2124         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2125
2126         clkcfg &= ~(1 << 10);
2127         MCHBAR32(CLKCFG) = clkcfg;
2128         clkcfg |= (1 << 10);
2129         MCHBAR32(CLKCFG) = clkcfg;
2130
2131         asm volatile (
2132                 "       movl $0x100, %%ecx\n"
2133                 "delay_update:\n"
2134                 "       nop\n"
2135                 "       nop\n"
2136                 "       nop\n"
2137                 "       nop\n"
2138                 "       loop delay_update\n"
2139                 : /* No outputs */
2140                 : /* No inputs */
2141                 : "%ecx", "memory"
2142                 );
2143
2144         clkcfg &= ~(1 << 10);
2145         MCHBAR32(CLKCFG) = clkcfg;
2146
2147         goto out;
2148 cache_code:
2149         goto vco_update;
2150 out:
2151
2152         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2153         printk(BIOS_DEBUG, "ok\n");
2154 }
2155
2156 static void sdram_program_clock_crossing(void)
2157 {
2158         int idx = 0;
2159
2160         /**
2161          * We add the indices according to our clocks from CLKCFG.
2162          */
2163 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2164         static const u32 data_clock_crossing[] = {
2165                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2166                 0xffffffff, 0xffffffff, /*  nonexistant  */
2167                 0xffffffff, 0xffffffff, /*  nonexistant  */
2168
2169                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2170                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2171                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2172
2173                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2174                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2175                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2176
2177                 0xffffffff, 0xffffffff, /*  nonexistant  */
2178                 0xffffffff, 0xffffffff, /*  nonexistant  */
2179                 0xffffffff, 0xffffffff, /*  nonexistant  */
2180
2181                 0xffffffff, 0xffffffff, /*  nonexistant  */
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183                 0xffffffff, 0xffffffff, /*  nonexistant  */
2184         };
2185
2186         static const u32 command_clock_crossing[] = {
2187                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2188                 0xffffffff, 0xffffffff, /*  nonexistant  */
2189                 0xffffffff, 0xffffffff, /*  nonexistant  */
2190
2191                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2192                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2193                 0xffffffff, 0xffffffff, /*  nonexistant  */
2194
2195                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2196                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2197                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2198
2199                 0xffffffff, 0xffffffff, /*  nonexistant  */
2200                 0xffffffff, 0xffffffff, /*  nonexistant  */
2201                 0xffffffff, 0xffffffff, /*  nonexistant  */
2202
2203                 0xffffffff, 0xffffffff, /*  nonexistant  */
2204                 0xffffffff, 0xffffffff, /*  nonexistant  */
2205                 0xffffffff, 0xffffffff, /*  nonexistant  */
2206         };
2207
2208 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2209         /* i945 G/P */
2210         static const u32 data_clock_crossing[] = {
2211                 0xffffffff, 0xffffffff, /*  nonexistant  */
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214
2215                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2216                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2217                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2218
2219                 0xffffffff, 0xffffffff, /*  nonexistant  */
2220                 0xffffffff, 0xffffffff, /*  nonexistant  */
2221                 0xffffffff, 0xffffffff, /*  nonexistant  */
2222
2223                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2224                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2225                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2226
2227                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2228                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2229                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2230         };
2231
2232         static const u32 command_clock_crossing[] = {
2233                 0xffffffff, 0xffffffff, /*  nonexistant  */
2234                 0xffffffff, 0xffffffff, /*  nonexistant  */
2235                 0xffffffff, 0xffffffff, /*  nonexistant  */
2236
2237                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2238                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2239                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2240
2241                 0xffffffff, 0xffffffff, /*  nonexistant  */
2242                 0xffffffff, 0xffffffff, /*  nonexistant  */
2243                 0xffffffff, 0xffffffff, /*  nonexistant  */
2244
2245                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2246                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2247                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2248
2249                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2250                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2251                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2252         };
2253 #endif
2254
2255         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2256
2257         printk(BIOS_DEBUG, "MEM=");
2258         switch (memclk()) {
2259         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2260         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2261         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2262         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2263         }
2264
2265         printk(BIOS_DEBUG, " FSB=");
2266         switch (fsbclk()) {
2267         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2268         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2269         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2270         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2271         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2272         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2273         }
2274
2275         if (command_clock_crossing[idx]==0xffffffff) {
2276                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2277         }
2278
2279         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2280         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2281
2282         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2283         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2284         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2285         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2286
2287         printk(BIOS_DEBUG, "... ok\n");
2288 }
2289
2290 static void sdram_disable_fast_dispatch(void)
2291 {
2292         u32 reg32;
2293
2294         reg32 = MCHBAR32(FSBPMC3);
2295         reg32 |= (1 << 1);
2296         MCHBAR32(FSBPMC3) = reg32;
2297
2298         reg32 = MCHBAR32(SBTEST);
2299         reg32 |= (3 << 1);
2300         MCHBAR32(SBTEST) = reg32;
2301 }
2302
2303 static void sdram_pre_jedec_initialization(void)
2304 {
2305         u32 reg32;
2306
2307         reg32 = MCHBAR32(WCC);
2308         reg32 &= 0x113ff3ff;
2309         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2310         MCHBAR32(WCC) = reg32;
2311
2312         MCHBAR32(SMVREFC) |= (1 << 6);
2313
2314         MCHBAR32(MMARB0) &= ~(3 << 17);
2315         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2316
2317         MCHBAR32(MMARB1) &= ~(7 << 8);
2318         MCHBAR32(MMARB1) |= (3 << 8);
2319
2320         /* Adaptive Idle Timer Control */
2321         MCHBAR32(C0AIT) = 0x000006c4;
2322         MCHBAR32(C0AIT+4) = 0x871a066d;
2323
2324         MCHBAR32(C1AIT) = 0x000006c4;
2325         MCHBAR32(C1AIT+4) = 0x871a066d;
2326 }
2327
2328 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2329 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2330 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2331 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2332 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2333 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2334 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2335 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2336
2337 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2338 {
2339         u32 chan0 = 0, chan1 = 0;
2340         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2341
2342         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2343                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2344         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2345                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2346         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2347         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2348
2349         if (sdram_capabilities_enhanced_addressing_xor()) {
2350                 if (!sysinfo->interleaved) {
2351                         /* Single Channel & Dual Channel Assymetric */
2352                         if (chan0_populated) {
2353                                 if (chan0_dualsided) {
2354                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2355                                 } else {
2356                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2357                                 }
2358                         }
2359                         if (chan1_populated) {
2360                                 if (chan1_dualsided) {
2361                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2362                                 } else {
2363                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2364                                 }
2365                         }
2366                 } else {
2367                         /* Interleaved has always both channels populated */
2368                         if (chan0_dualsided) {
2369                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2370                         } else {
2371                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2372                         }
2373
2374                         if (chan1_dualsided) {
2375                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2376                         } else {
2377                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2378                         }
2379                 }
2380         } else {
2381                 if (!sysinfo->interleaved) {
2382                         /* Single Channel & Dual Channel Assymetric */
2383                         if (chan0_populated) {
2384                                 if (chan0_dualsided) {
2385                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2386                                 } else {
2387                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2388                                 }
2389                         }
2390                         if (chan1_populated) {
2391                                 if (chan1_dualsided) {
2392                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2393                                 } else {
2394                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2395                                 }
2396                         }
2397                 } else {
2398                         /* Interleaved has always both channels populated */
2399                         if (chan0_dualsided) {
2400                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2401                         } else {
2402                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2403                         }
2404
2405                         if (chan1_dualsided) {
2406                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2407                         } else {
2408                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2409                         }
2410                 }
2411         }
2412
2413         MCHBAR32(C0DRC1) &= 0x00ffffff;
2414         MCHBAR32(C0DRC1) |= chan0;
2415         MCHBAR32(C1DRC1) &= 0x00ffffff;
2416         MCHBAR32(C1DRC1) |= chan1;
2417 }
2418
2419 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2420 {
2421         u32 reg32;
2422
2423         /* Enable Channel XORing for Dual Channel Interleave */
2424         if (sysinfo->interleaved) {
2425
2426                 reg32 = MCHBAR32(DCC);
2427 #if CONFIG_CHANNEL_XOR_RANDOMIZATION
2428                 reg32 &= ~(1 << 10);
2429                 reg32 |= (1 << 9);
2430 #else
2431                 reg32 &= ~(1 << 9);
2432 #endif
2433                 MCHBAR32(DCC) = reg32;
2434         }
2435
2436         /* DRAM mode optimizations */
2437         sdram_enhanced_addressing_mode(sysinfo);
2438
2439         reg32 = MCHBAR32(FSBPMC3);
2440         reg32 &= ~(1 << 1);
2441         MCHBAR32(FSBPMC3) = reg32;
2442
2443         reg32 = MCHBAR32(SBTEST);
2444         reg32 &= ~(1 << 2);
2445         MCHBAR32(SBTEST) = reg32;
2446
2447         reg32 = MCHBAR32(SBOCC);
2448         reg32 &= 0xffbdb6ff;
2449         reg32 |= (0xbdb6 << 8) | (1 << 0);
2450         MCHBAR32(SBOCC) = reg32;
2451 }
2452
2453 static void sdram_power_management(struct sys_info *sysinfo)
2454 {
2455         u8 reg8;
2456         u16 reg16;
2457         u32 reg32;
2458         int integrated_graphics = 1;
2459         int i;
2460
2461         reg32 = MCHBAR32(C0DRT2);
2462         reg32 &= 0xffffff00;
2463         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2464         reg32 |= (1 << 5) | (1 << 4);
2465         MCHBAR32(C0DRT2) = reg32;
2466
2467         reg32 = MCHBAR32(C1DRT2);
2468         reg32 &= 0xffffff00;
2469         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2470         reg32 |= (1 << 5) | (1 << 4);
2471         MCHBAR32(C1DRT2) = reg32;
2472
2473         reg32 = MCHBAR32(C0DRC1);
2474
2475         reg32 |= (1 << 12) | (1 << 11);
2476         MCHBAR32(C0DRC1) = reg32;
2477
2478         reg32 = MCHBAR32(C1DRC1);
2479
2480         reg32 |= (1 << 12) | (1 << 11);
2481         MCHBAR32(C1DRC1) = reg32;
2482
2483         if (i945_silicon_revision()>1) {
2484                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2485                 u16 peg_bits = (1 << 5) | (1 << 0);
2486
2487                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2488         } else {
2489                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2490                 u16 peg_bits = (1 << 5) | (1 << 0);
2491
2492                 /* Rev 0 and 1 */
2493                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2494         }
2495
2496         reg16 = MCHBAR16(UPMC2);
2497         reg16 &= 0xfc00;
2498         reg16 |= 0x0100;
2499         MCHBAR16(UPMC2) = reg16;
2500
2501         MCHBAR32(UPMC3) = 0x000f06ff;
2502
2503         for (i=0; i<5; i++) {
2504                 MCHBAR32(UPMC3) &= ~(1 << 16);
2505                 MCHBAR32(UPMC3) |= (1 << 16);
2506         }
2507
2508         MCHBAR32(GIPMC1) = 0x8000000c;
2509
2510         reg16 = MCHBAR16(CPCTL);
2511         reg16 &= ~(7 << 11);
2512         if (i945_silicon_revision()>2) {
2513                 reg16 |= (6 << 11);
2514         } else {
2515                 reg16 |= (4 << 11);
2516         }
2517         MCHBAR16(CPCTL) = reg16;
2518
2519 #if 0
2520         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2521 #else
2522         if (i945_silicon_revision() != 0) {
2523 #endif
2524                 switch (sysinfo->fsb_frequency) {
2525                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2526                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2527                 }
2528         } else {
2529                 switch (sysinfo->fsb_frequency) {
2530                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2531                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2532                 }
2533         }
2534
2535         MCHBAR32(FSBPMC1) = 0x8000000c;
2536
2537         reg32 = MCHBAR32(C2C3TT);
2538         reg32 &= 0xffff0000;
2539         switch (sysinfo->fsb_frequency) {
2540         case 667: reg32 |= 0x0600; break;
2541         case 533: reg32 |= 0x0480; break;
2542         }
2543         MCHBAR32(C2C3TT) = reg32;
2544
2545         reg32 = MCHBAR32(C3C4TT);
2546         reg32 &= 0xffff0000;
2547         switch (sysinfo->fsb_frequency) {
2548         case 667: reg32 |= 0x0b80; break;
2549         case 533: reg32 |= 0x0980; break;
2550         }
2551         MCHBAR32(C3C4TT) = reg32;
2552
2553         if (i945_silicon_revision() == 0) {
2554                 MCHBAR32(ECO) &= ~(1 << 16);
2555         } else {
2556                 MCHBAR32(ECO) |= (1 << 16);
2557         }
2558
2559 #if 0
2560
2561         if (i945_silicon_revision() == 0) {
2562                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2563         } else {
2564                 MCHBAR32(FSBPMC3) |= (1 << 29);
2565         }
2566 #endif
2567         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2568
2569         MCHBAR32(FSBPMC3) |= (1 << 21);
2570
2571         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2572
2573         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2574
2575         reg32 = MCHBAR32(FSBPMC4);
2576         reg32 &= ~(3 << 24);
2577         reg32 |= ( 2 << 24);
2578         MCHBAR32(FSBPMC4) = reg32;
2579
2580         MCHBAR32(FSBPMC4) |= (1 << 21);
2581
2582         MCHBAR32(FSBPMC4) |= (1 << 5);
2583
2584         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2585                 /* stepping 0 and 1 or CPUID 6e8 */
2586                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2587         } else {
2588                 MCHBAR32(FSBPMC4) |= (1 << 4);
2589         }
2590
2591         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2592         reg8 |= (1 << 4);
2593         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2594
2595         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2596         reg8 |= (1 << 2);
2597         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2598
2599 #ifdef C2_SELF_REFRESH_DISABLE
2600
2601         if (integrated_graphics) {
2602                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2603                 MCHBAR16(MIPMC4) = 0x0468;
2604                 MCHBAR16(MIPMC5) = 0x046c;
2605                 MCHBAR16(MIPMC6) = 0x046c;
2606         } else {
2607                 MCHBAR16(MIPMC4) = 0x6468;
2608                 MCHBAR16(MIPMC5) = 0x646c;
2609                 MCHBAR16(MIPMC6) = 0x646c;
2610         }
2611 #else
2612         if (integrated_graphics) {
2613                 MCHBAR16(MIPMC4) = 0x04f8;
2614                 MCHBAR16(MIPMC5) = 0x04fc;
2615                 MCHBAR16(MIPMC6) = 0x04fc;
2616         } else {
2617                 MCHBAR16(MIPMC4) = 0x64f8;
2618                 MCHBAR16(MIPMC5) = 0x64fc;
2619                 MCHBAR16(MIPMC6) = 0x64fc;
2620         }
2621
2622 #endif
2623
2624         reg32 = MCHBAR32(PMCFG);
2625         reg32 &= ~(3 << 17);
2626         reg32 |= (2 << 17);
2627         MCHBAR32(PMCFG) = reg32;
2628
2629         MCHBAR32(PMCFG) |= (1 << 4);
2630
2631         reg32 = MCHBAR32(0xc30);
2632         reg32 &= 0xffffff00;
2633         reg32 |= 0x01;
2634         MCHBAR32(0xc30) = reg32;
2635
2636         MCHBAR32(0xb18) &= ~(1 << 21);
2637 }
2638
2639 static void sdram_thermal_management(void)
2640 {
2641
2642         MCHBAR8(TCO1) = 0x00;
2643         MCHBAR8(TCO0) = 0x00;
2644
2645         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2646          * 0x30/0x32.
2647          */
2648
2649         /* TODO This is not implemented yet. Volunteers? */
2650 }
2651
2652 static void sdram_save_receive_enable(void)
2653 {
2654         int i;
2655         u32 reg32;
2656         u8 values[4];
2657
2658         /* The following values are stored to an unused CMOS
2659          * area and restored instead of recalculated in case
2660          * of an S3 resume.
2661          *
2662          * C0WL0REOST [7:0]             -> 8 bit
2663          * C1WL0REOST [7:0]             -> 8 bit
2664          * RCVENMT    [11:8] [3:0]      -> 8 bit
2665          * C0DRT1     [27:24]           -> 4 bit
2666          * C1DRT1     [27:24]           -> 4 bit
2667          */
2668
2669         values[0] = MCHBAR8(C0WL0REOST);
2670         values[1] = MCHBAR8(C1WL0REOST);
2671
2672         reg32 = MCHBAR32(RCVENMT);
2673         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2674
2675         reg32 = MCHBAR32(C0DRT1);
2676         values[3] = (reg32 >> 24) & 0x0f;
2677         reg32 = MCHBAR32(C1DRT1);
2678         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2679
2680         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2681          * so we grab bytes 128 - 131 to save the receive enable values
2682          */
2683
2684         for (i=0; i<4; i++)
2685                 cmos_write(values[i], 128 + i);
2686 }
2687
2688 static void sdram_recover_receive_enable(void)
2689 {
2690         int i;
2691         u32 reg32;
2692         u8 values[4];
2693
2694         for (i=0; i<4; i++)
2695                 values[i] = cmos_read(128 + i);
2696
2697         MCHBAR8(C0WL0REOST) = values[0];
2698         MCHBAR8(C1WL0REOST) = values[1];
2699
2700         reg32 = MCHBAR32(RCVENMT);
2701         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2702         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2703         MCHBAR32(RCVENMT) = reg32;
2704
2705         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2706         reg32 |= (u32)(values[3] & 0x0f) << 24;
2707         MCHBAR32(C0DRT1) = reg32;
2708
2709         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2710         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2711         MCHBAR32(C1DRT1) = reg32;
2712 }
2713
2714 #include "rcven.c"
2715
2716 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2717 {
2718         MCHBAR32(REPC) |= (1 << 0);
2719
2720         /* enable upper CMOS */
2721         RCBA32(0x3400) = (1 << 2);
2722
2723         /* Program Receive Enable Timings */
2724         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2725                 sdram_recover_receive_enable();
2726         } else {
2727                 receive_enable_adjust(sysinfo);
2728                 sdram_save_receive_enable();
2729         }
2730
2731         MCHBAR32(C0DRC1) |= (1 << 6);
2732         MCHBAR32(C1DRC1) |= (1 << 6);
2733         MCHBAR32(C0DRC1) &= ~(1 << 6);
2734         MCHBAR32(C1DRC1) &= ~(1 << 6);
2735
2736         MCHBAR32(MIPMC3) |= (0x0f << 0);
2737 }
2738
2739 /**
2740  * @brief Enable On-Die Termination for DDR2.
2741  *
2742  */
2743
2744 static void sdram_on_die_termination(struct sys_info *sysinfo)
2745 {
2746         static const u32 odt[] = {
2747                 0x00024911, 0xe0010000,
2748                 0x00049211, 0xe0020000,
2749                 0x0006db11, 0xe0030000,
2750         };
2751
2752         u32 reg32;
2753         int cas;
2754
2755         reg32 = MCHBAR32(ODTC);
2756         reg32 &= ~(3 << 16);
2757         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2758         MCHBAR32(ODTC) = reg32;
2759
2760         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2761                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2762                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2763
2764                 reg32 = MCHBAR32(C0ODT);
2765                 reg32 &= ~(7 << 28);
2766                 MCHBAR32(C0ODT) = reg32;
2767                 reg32 = MCHBAR32(C1ODT);
2768                 reg32 &= ~(7 << 28);
2769                 MCHBAR32(C1ODT) = reg32;
2770         }
2771
2772         cas = sysinfo->cas;
2773
2774         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2775         reg32 |= odt[(cas-3) * 2];
2776         MCHBAR32(C0ODT) = reg32;
2777
2778         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2779         reg32 |= odt[(cas-3) * 2];
2780         MCHBAR32(C1ODT) = reg32;
2781
2782         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2783         reg32 |= odt[((cas-3) * 2) + 1];
2784         MCHBAR32(C0ODT + 4) = reg32;
2785
2786         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2787         reg32 |= odt[((cas-3) * 2) + 1];
2788         MCHBAR32(C1ODT + 4) = reg32;
2789 }
2790
2791 /**
2792  * @brief Enable clocks to populated sockets
2793  */
2794
2795 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2796 {
2797         u8 clocks[2] = { 0, 0 };
2798
2799 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2800 #define CLOCKS_WIDTH 2
2801 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2802 #define CLOCKS_WIDTH 3
2803 #endif
2804         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2805                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2806
2807         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2808                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2809
2810         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2811                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2812
2813         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2814                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2815
2816 #if CONFIG_OVERRIDE_CLOCK_DISABLE
2817         /* Usually system firmware turns off system memory clock signals
2818          * to unused SO-DIMM slots to reduce EMI and power consumption.
2819          * However, the Kontron 986LCD-M does not like unused clock
2820          * signals to be disabled.
2821          */
2822
2823         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2824         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2825 #endif
2826
2827         MCHBAR8(C0DCLKDIS) = clocks[0];
2828         MCHBAR8(C1DCLKDIS) = clocks[1];
2829 }
2830
2831 #define RTT_ODT_NONE    0
2832 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2833 #define RTT_ODT_75_OHM  (1 << 5)
2834 #define RTT_ODT_150_OHM (1 << 9)
2835
2836 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2837
2838 #define MRS_CAS_3       (3 << 7)
2839 #define MRS_CAS_4       (4 << 7)
2840 #define MRS_CAS_5       (5 << 7)
2841
2842 #define MRS_TWR_3       (2 << 12)
2843 #define MRS_TWR_4       (3 << 12)
2844 #define MRS_TWR_5       (4 << 12)
2845
2846 #define MRS_BT          (1 << 6)
2847
2848 #define MRS_BL4         (2 << 3)
2849 #define MRS_BL8         (3 << 3)
2850
2851 static void sdram_jedec_enable(struct sys_info *sysinfo)
2852 {
2853         int i, nonzero;
2854         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2855
2856         for (i = 0, nonzero = -1; i < 8; i++) {
2857                 if (sysinfo->banksize[i]  == 0) {
2858                         continue;
2859                 }
2860
2861                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2862                 switch (i) {
2863                 case 0:
2864                         /* Start at address 0 */
2865                         bankaddr = 0;
2866                         break;
2867                 case 4:
2868                         if (sysinfo->interleaved) {
2869                                 bankaddr = 0x40;
2870                                 break;
2871                         }
2872                 default:
2873                         if (nonzero != -1) {
2874                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2875                                 bankaddr += sysinfo->banksize[nonzero] <<
2876                                         (sysinfo->interleaved ? 26 : 25);
2877                                 break;
2878                         }
2879                         /* No populated bank hit before. Start at address 0 */
2880                         bankaddr = 0;
2881                 }
2882
2883                 /* We have a bank with a non-zero size.. Remember it
2884                  * for the next offset we have to calculate
2885                  */
2886                 nonzero = i;
2887
2888                 /* Get CAS latency set up */
2889                 switch (sysinfo->cas) {
2890                 case 5: mrsaddr = MRS_CAS_5; break;
2891                 case 4: mrsaddr = MRS_CAS_4; break;
2892                 case 3: mrsaddr = MRS_CAS_3; break;
2893                 default: die("Jedec Error (CAS).\n");
2894                 }
2895
2896                 /* Get tWR set */
2897                 switch (sysinfo->twr) {
2898                 case 5: mrsaddr |= MRS_TWR_5; break;
2899                 case 4: mrsaddr |= MRS_TWR_4; break;
2900                 case 3: mrsaddr |= MRS_TWR_3; break;
2901                 default: die("Jedec Error (tWR).\n");
2902                 }
2903
2904                 /* Set "Burst Type" */
2905                 mrsaddr |= MRS_BT;
2906
2907                 /* Interleaved */
2908                 if (sysinfo->interleaved) {
2909                         mrsaddr = mrsaddr << 1;
2910                 }
2911
2912                 /* Only burst length 8 supported */
2913                 mrsaddr |= MRS_BL8;
2914
2915                 /* Apply NOP */
2916                 PRINTK_DEBUG("Apply NOP\n");
2917                 do_ram_command(RAM_COMMAND_NOP);
2918                 ram_read32(bankaddr);
2919
2920                 /* Precharge all banks */
2921                 PRINTK_DEBUG("All Banks Precharge\n");
2922                 do_ram_command(RAM_COMMAND_PRECHARGE);
2923                 ram_read32(bankaddr);
2924
2925                 /* Extended Mode Register Set (2) */
2926                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2927                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2928                 ram_read32(bankaddr);
2929
2930                 /* Extended Mode Register Set (3) */
2931                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2932                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2933                 ram_read32(bankaddr);
2934
2935                 /* Extended Mode Register Set */
2936                 PRINTK_DEBUG("Extended Mode Register Set\n");
2937                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2938                 tmpaddr = bankaddr;
2939                 if (!sdram_capabilities_dual_channel()) {
2940                         tmpaddr |= RTT_ODT_75_OHM;
2941                 } else if (sysinfo->interleaved) {
2942                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2943                 } else {
2944                         tmpaddr |= RTT_ODT_150_OHM;
2945                 }
2946                 ram_read32(tmpaddr);
2947
2948                 /* Mode Register Set: Reset DLLs */
2949                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2950                 do_ram_command(RAM_COMMAND_MRS);
2951                 tmpaddr = bankaddr;
2952                 tmpaddr |= mrsaddr;
2953                 /* Set DLL reset bit */
2954                 if (sysinfo->interleaved)
2955                         tmpaddr |= (1 << 12);
2956                 else
2957                         tmpaddr |= (1 << 11);
2958                 ram_read32(tmpaddr);
2959
2960                 /* Precharge all banks */
2961                 PRINTK_DEBUG("All Banks Precharge\n");
2962                 do_ram_command(RAM_COMMAND_PRECHARGE);
2963                 ram_read32(bankaddr);
2964
2965                 /* CAS before RAS Refresh */
2966                 PRINTK_DEBUG("CAS before RAS\n");
2967                 do_ram_command(RAM_COMMAND_CBR);
2968
2969                 /* CBR wants two READs */
2970                 ram_read32(bankaddr);
2971                 ram_read32(bankaddr);
2972
2973                 /* Mode Register Set: Enable DLLs */
2974                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2975                 do_ram_command(RAM_COMMAND_MRS);
2976
2977                 tmpaddr = bankaddr;
2978                 tmpaddr |= mrsaddr;
2979                 ram_read32(tmpaddr);
2980
2981                 /* Extended Mode Register Set */
2982                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2983                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2984
2985                 tmpaddr = bankaddr;
2986                 if (!sdram_capabilities_dual_channel()) {
2987
2988                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2989                 } else if (sysinfo->interleaved) {
2990                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2991                 } else {
2992                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2993                 }
2994                 ram_read32(tmpaddr);
2995
2996                 /* Extended Mode Register Set */
2997                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2998                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2999
3000                 tmpaddr = bankaddr;
3001                 if (!sdram_capabilities_dual_channel()) {
3002                         tmpaddr |= RTT_ODT_75_OHM;
3003                 } else if (sysinfo->interleaved) {
3004                         tmpaddr |= (RTT_ODT_150_OHM << 1);
3005                 } else {
3006                         tmpaddr |= RTT_ODT_150_OHM;
3007                 }
3008                 ram_read32(tmpaddr);
3009         }
3010 }
3011
3012 static void sdram_init_complete(void)
3013 {
3014         PRINTK_DEBUG("Normal Operation\n");
3015         do_ram_command(RAM_COMMAND_NORMAL);
3016 }
3017
3018 static void sdram_setup_processor_side(void)
3019 {
3020         if (i945_silicon_revision() == 0)
3021                 MCHBAR32(FSBPMC3) |= (1 << 2);
3022
3023         MCHBAR8(0xb00) |= 1;
3024
3025         if (i945_silicon_revision() == 0)
3026                 MCHBAR32(SLPCTL) |= (1 << 8);
3027 }
3028
3029 /**
3030  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3031  */
3032 void sdram_initialize(int boot_path)
3033 {
3034         struct sys_info sysinfo;
3035         u8 reg8, cas_mask;
3036
3037         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3038
3039         memset(&sysinfo, 0, sizeof(sysinfo));
3040
3041         sysinfo.boot_path = boot_path;
3042
3043         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3044         sdram_get_dram_configuration(&sysinfo);
3045
3046         /* If error, do cold boot */
3047         sdram_detect_errors(&sysinfo);
3048
3049         /* Check whether we have stacked DIMMs */
3050         sdram_verify_package_type(&sysinfo);
3051
3052         /* Determine common CAS */
3053         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3054
3055         /* Choose Common Frequency */
3056         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3057
3058         /* Determine smallest common tRAS */
3059         sdram_detect_smallest_tRAS(&sysinfo);
3060
3061         /* Determine tRP */
3062         sdram_detect_smallest_tRP(&sysinfo);
3063
3064         /* Determine tRCD */
3065         sdram_detect_smallest_tRCD(&sysinfo);
3066
3067         /* Determine smallest refresh period */
3068         sdram_detect_smallest_refresh(&sysinfo);
3069
3070         /* Verify all DIMMs support burst length 8 */
3071         sdram_verify_burst_length(&sysinfo);
3072
3073         /* determine tWR */
3074         sdram_detect_smallest_tWR(&sysinfo);
3075
3076         /* Determine DIMM size parameters (rows, columns banks) */
3077         sdram_detect_dimm_size(&sysinfo);
3078
3079         /* determine tRFC */
3080         sdram_detect_smallest_tRFC(&sysinfo);
3081
3082         /* Program PLL settings */
3083         sdram_program_pll_settings(&sysinfo);
3084
3085         /* Program Graphics Frequency */
3086         sdram_program_graphics_frequency(&sysinfo);
3087
3088         /* Program System Memory Frequency */
3089         sdram_program_memory_frequency(&sysinfo);
3090
3091         /* Determine Mode of Operation (Interleaved etc) */
3092         sdram_set_channel_mode(&sysinfo);
3093
3094         /* Program Clock Crossing values */
3095         sdram_program_clock_crossing();
3096
3097         /* Disable fast dispatch */
3098         sdram_disable_fast_dispatch();
3099
3100         /* Enable WIODLL Power Down in ACPI states */
3101         MCHBAR32(C0DMC) |= (1 << 24);
3102         MCHBAR32(C1DMC) |= (1 << 24);
3103
3104         /* Program DRAM Row Boundary/Attribute Registers */
3105
3106         /* program row size DRB and set TOLUD */
3107         sdram_program_row_boundaries(&sysinfo);
3108
3109         /* program page size DRA */
3110         sdram_set_row_attributes(&sysinfo);
3111
3112         /* Program CxBNKARC */
3113         sdram_set_bank_architecture(&sysinfo);
3114
3115         /* Program DRAM Timing and Control registers based on SPD */
3116         sdram_set_timing_and_control(&sysinfo);
3117
3118         /* On-Die Termination Adjustment */
3119         sdram_on_die_termination(&sysinfo);
3120
3121         /* Pre Jedec Initialization */
3122         sdram_pre_jedec_initialization();
3123
3124         /* Perform System Memory IO Initialization */
3125         sdram_initialize_system_memory_io(&sysinfo);
3126
3127         /* Perform System Memory IO Buffer Enable */
3128         sdram_enable_system_memory_io(&sysinfo);
3129
3130         /* Enable System Memory Clocks */
3131         sdram_enable_memory_clocks(&sysinfo);
3132
3133         if (boot_path == BOOT_PATH_NORMAL) {
3134                 /* Jedec Initialization sequence */
3135                 sdram_jedec_enable(&sysinfo);
3136         }
3137
3138         /* Program Power Management Registers */
3139         sdram_power_management(&sysinfo);
3140
3141         /* Post Jedec Init */
3142         sdram_post_jedec_initialization(&sysinfo);
3143
3144         /* Program DRAM Throttling */
3145         sdram_thermal_management();
3146
3147         /* Normal Operations */
3148         sdram_init_complete();
3149
3150         /* Program Receive Enable Timings */
3151         sdram_program_receive_enable(&sysinfo);
3152
3153         /* Enable Periodic RCOMP */
3154         sdram_enable_rcomp();
3155
3156         /* Tell ICH7 that we're done */
3157         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3158         reg8 &= ~(1 << 7);
3159         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3160
3161         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3162
3163         sdram_setup_processor_side();
3164 }
3165
3166 unsigned long get_top_of_ram(void)
3167 {
3168         /* This will not work if TSEG is in place! */
3169         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3170
3171         return (unsigned long) tom;
3172 }
3173