src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <cpu/x86/mtrr.h>
  21 #include <cpu/x86/cache.h>
  22 #include <spd.h>
  23 #include "raminit.h"
  24 #include "i945.h"
  25
  26 /* Debugging macros. */
  27 #if CONFIG_DEBUG_RAM_SETUP
  28 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  29 #else
  30 #define PRINTK_DEBUG(x...)
  31 #endif
  32
  33 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  34
  35 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  36 #define RAM_COMMAND_NOP                 (0x1 << 16)
  37 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  38 #define RAM_COMMAND_MRS                 (0x3 << 16)
  39 #define RAM_COMMAND_EMRS                (0x4 << 16)
  40 #define RAM_COMMAND_CBR                 (0x6 << 16)
  41 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  42
  43 #define RAM_EMRS_1                      (0x0 << 21)
  44 #define RAM_EMRS_2                      (0x1 << 21)
  45 #define RAM_EMRS_3                      (0x2 << 21)
  46
  47 static void do_ram_command(u32 command)
  48 {
  49         u32 reg32;
  50
  51         reg32 = MCHBAR32(DCC);
  52         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  53         reg32 |= command;
  54
  55         /* Also set Init Complete */
  56         if (command == RAM_COMMAND_NORMAL)
  57                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  58
  59         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  60
  61         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  62
  63         PRINTK_DEBUG("...done\n");
  64 }
  65
  66 static void ram_read32(u32 offset)
  67 {
  68         PRINTK_DEBUG("   ram read: %08x\n", offset);
  69
  70         read32(offset);
  71 }
  72
  73 #if CONFIG_DEBUG_RAM_SETUP
  74 static void sdram_dump_mchbar_registers(void)
  75 {
  76         int i;
  77         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  78
  79         for (i=0; i<0xfff; i+=4) {
  80                 if (MCHBAR32(i) == 0)
  81                         continue;
  82                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  83         }
  84 }
  85 #endif
  86
  87 static int memclk(void)
  88 {
  89         int offset = 0;
  90 #ifdef CHIPSET_I945GM
  91         offset++;
  92 #endif
  93         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
  94         case 1: return 400;
  95         case 2: return 533;
  96         case 3: return 667;
  97         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
  98         }
  99         return -1;
 100 }
 101
 102 #ifdef CHIPSET_I945GM
 103 static int fsbclk(void)
 104 {
 105         switch (MCHBAR32(CLKCFG) & 7) {
 106         case 0: return 400;
 107         case 1: return 533;
 108         case 3: return 667;
 109         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 110         }
 111         return -1;
 112 }
 113 #endif
 114 #ifdef CHIPSET_I945GC
 115 static int fsbclk(void)
 116 {
 117         switch (MCHBAR32(CLKCFG) & 7) {
 118         case 0: return 1066;
 119         case 1: return 533;
 120         case 2: return 800;
 121         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 122         }
 123         return -1;
 124 }
 125 #endif
 126
 127 static int sdram_capabilities_max_supported_memory_frequency(void)
 128 {
 129         u32 reg32;
 130
 131 #ifdef MAXIMUM_SUPPORTED_FREQUENCY
 132         return MAXIMUM_SUPPORTED_FREQUENCY;
 133 #endif
 134
 135         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
 136         reg32 &= (7 << 0);
 137
 138         switch (reg32) {
 139         case 4: return 400;
 140         case 3: return 533;
 141         case 2: return 667;
 142         }
 143         /* Newer revisions of this chipset rather support faster memory clocks,
 144          * so if it's a reserved value, return the fastest memory clock that we
 145          * know of and can handle
 146          */
 147         return 667;
 148 }
 149
 150 /**
 151  * @brief determine whether chipset is capable of dual channel interleaved mode
 152  *
 153  * @return 1 if interleaving is supported, 0 otherwise
 154  */
 155 static int sdram_capabilities_interleave(void)
 156 {
 157         u32 reg32;
 158
 159         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 160         reg32 >>= 25;
 161         reg32 &= 1;
 162
 163         return (!reg32);
 164 }
 165
 166 /**
 167  * @brief determine whether chipset is capable of two memory channels
 168  *
 169  * @return 1 if dual channel operation is supported, 0 otherwise
 170  */
 171 static int sdram_capabilities_dual_channel(void)
 172 {
 173         u32 reg32;
 174
 175         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 176         reg32 >>= 24;
 177         reg32 &= 1;
 178
 179         return (!reg32);
 180 }
 181
 182 static int sdram_capabilities_enhanced_addressing_xor(void)
 183 {
 184         u8 reg8;
 185
 186         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 187         reg8 &= (1 << 7);
 188
 189         return (!reg8);
 190 }
 191
 192 static int sdram_capabilities_two_dimms_per_channel(void)
 193 {
 194         u8 reg8;
 195
 196         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 197         reg8 &= (1 << 0);
 198
 199         return (reg8 != 0);
 200 }
 201
 202 // TODO check if we ever need this function
 203 #if 0
 204 static int sdram_capabilities_MEM4G_disable(void)
 205 {
 206         u8 reg8;
 207
 208         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
 209         reg8 &= (1 << 0);
 210
 211         return (reg8 != 0);
 212 }
 213 #endif
 214
 215 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 216 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 217 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 218 #define GFX_FREQUENCY_CAP_ALL           0x00
 219
 220 static int sdram_capabilities_core_frequencies(void)
 221 {
 222         u8 reg8;
 223
 224         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 225         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 226         reg8 >>= 1;
 227
 228         return (reg8);
 229 }
 230
 231 static void sdram_detect_errors(void)
 232 {
 233         u8 reg8;
 234         u8 do_reset = 0;
 235
 236         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 237
 238         if (reg8 & ((1<<7)|(1<<2))) {
 239                 if (reg8 & (1<<2)) {
 240                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 241                         /* Write back clears bit 2 */
 242                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 243                         do_reset = 1;
 244
 245                 }
 246
 247                 if (reg8 & (1<<7)) {
 248                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 249                         reg8 &= ~(1<<7);
 250                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 251                         do_reset = 1;
 252                 }
 253
 254                 /* Set SLP_S3# Assertion Stretch Enable */
 255                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 256                 reg8 |= (1 << 3);
 257                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 258
 259                 if (do_reset) {
 260                         printk(BIOS_DEBUG, "Reset required.\n");
 261                         outb(0x00, 0xcf9);
 262                         outb(0x0e, 0xcf9);
 263                         for (;;) asm("hlt"); /* Wait for reset! */
 264                 }
 265         }
 266
 267         /* Set DRAM initialization bit in ICH7 */
 268         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 269         reg8 |= (1<<7);
 270         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 271
 272 }
 273
 274 /**
 275  * @brief Get generic DIMM parameters.
 276  * @param sysinfo Central memory controller information structure
 277  *
 278  * This function gathers several pieces of information for each system DIMM:
 279  *  o DIMM width (x8 / x16)
 280  *  o DIMM sides (single sided / dual sided)
 281  *
 282  *  Also, some non-supported scenarios are detected.
 283  */
 284
 285 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 286 {
 287         u32 dimm_mask = 0;
 288         int i;
 289
 290         /**
 291          * i945 supports two DIMMs, in two configurations:
 292          *
 293          * - single channel with two dimms
 294          * - dual channel with one dimm per channel
 295          *
 296          * In practice dual channel mainboards have their spd at 0x50, 0x52
 297          * whereas single channel configurations have their spd at 0x50/x51
 298          *
 299          * The capability register knows a lot about the channel configuration
 300          * but for now we stick with the information we gather from the SPD
 301          * ROMs
 302          */
 303
 304         if (sdram_capabilities_dual_channel()) {
 305                 sysinfo->dual_channel = 1;
 306                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 307         } else {
 308                 sysinfo->dual_channel = 0;
 309                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 310         }
 311
 312         /**
 313          * Since we only support two DIMMs in total, there is a limited number
 314          * of combinations. This function returns the type of DIMMs.
 315          * return value:
 316          *   [0:7]  lower DIMM population
 317          *   [8-15] higher DIMM population
 318          *   [16]   dual channel?
 319          *
 320          * There are 5 different possible populations for a DIMM socket:
 321          * 1. x16 double sided (X16DS)
 322          * 2. x8 double sided  (X8DS)
 323          * 3. x16 single sided (X16SS)
 324          * 4. x8 double stacked (X8DDS)
 325          * 5. not populated (NC)
 326          *
 327          * For the return value we start counting at zero.
 328          *
 329          */
 330
 331         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 332                 u8 reg8, device = DIMM_SPD_BASE + i;
 333
 334                 /* Initialize the socket information with a sane value */
 335                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 336
 337                 /* Dual Channel not supported, but Channel 1? Bail out */
 338                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 339                         continue;
 340
 341                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 342                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 343                         continue;
 344
 345                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 346
 347                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 348                         printk(BIOS_DEBUG, "N/A\n");
 349                         continue;
 350                 }
 351
 352                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 353                 if (reg8 == ERROR_SCHEME_ECC)
 354                         die("Error: ECC memory not supported by this chipset\n");
 355
 356                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 357                 if (reg8 & MODULE_BUFFERED)
 358                         die("Error: Buffered memory not supported by this chipset\n");
 359                 if (reg8 & MODULE_REGISTERED)
 360                         die("Error: Registered memory not supported by this chipset\n");
 361
 362                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 363                 case 0x08:
 364                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 365                         case 1:
 366                                 printk(BIOS_DEBUG, "x8DDS\n");
 367                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 368                                 break;
 369                         case 0:
 370                                 printk(BIOS_DEBUG, "x8DS\n");
 371                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 372                                 break;
 373                         default:
 374                                 printk(BIOS_DEBUG, "Unsupported.\n");
 375                         }
 376                         break;
 377                 case 0x10:
 378                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 379                         case 1:
 380                                 printk(BIOS_DEBUG, "x16DS\n");
 381                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 382                                 break;
 383                         case 0:
 384                                 printk(BIOS_DEBUG, "x16SS\n");
 385                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 386                                 break;
 387                         default:
 388                                 printk(BIOS_DEBUG, "Unsupported.\n");
 389                         }
 390                         break;
 391                 default:
 392                         die("Unsupported DDR-II memory width.\n");
 393                 }
 394
 395                 dimm_mask |= (1 << i);
 396         }
 397
 398         if (!dimm_mask) {
 399                 die("No memory installed.\n");
 400         }
 401
 402         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 403                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 404         }
 405 }
 406
 407 /**
 408  * @brief determine if any DIMMs are stacked
 409  *
 410  * @param sysinfo central sysinfo data structure.
 411  */
 412 static void sdram_verify_package_type(struct sys_info * sysinfo)
 413 {
 414         int i;
 415
 416         /* Assume no stacked DIMMs are available until we find one */
 417         sysinfo->package = 0;
 418         for (i=0; i<2*DIMM_SOCKETS; i++) {
 419                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 420                         continue;
 421
 422                 /* Is the current DIMM a stacked DIMM? */
 423                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 424                         sysinfo->package = 1;
 425         }
 426 }
 427
 428 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 429 {
 430         int i;
 431         u8 cas_mask;
 432
 433         /* Setup CAS mask with all supported CAS Latencies */
 434         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 435                    SPD_CAS_LATENCY_DDR2_4 |
 436                    SPD_CAS_LATENCY_DDR2_5;
 437
 438         for (i=0; i<2*DIMM_SOCKETS; i++) {
 439                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 440                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 441         }
 442
 443         if(!cas_mask) {
 444                 die("No DDR-II modules with accepted CAS latencies found.\n");
 445         }
 446
 447         return cas_mask;
 448 }
 449
 450 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 451 {
 452         int i, j, idx;
 453         int lowest_common_cas = 0;
 454         int max_ram_speed = 0;
 455
 456         const u8 ddr2_speeds_table[] = {
 457                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 458                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 459                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 460         };
 461
 462         const u8 spd_lookup_table[] = {
 463                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 464                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 465                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 466         };
 467
 468         switch (sdram_capabilities_max_supported_memory_frequency()) {
 469         case 400: max_ram_speed = 0; break;
 470         case 533: max_ram_speed = 1; break;
 471         case 667: max_ram_speed = 2; break;
 472         }
 473
 474         if (fsbclk() == 533)
 475                 max_ram_speed = 1;
 476
 477         sysinfo->memory_frequency = 0;
 478         sysinfo->cas = 0;
 479
 480         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 481                 lowest_common_cas = 3;
 482         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 483                 lowest_common_cas = 4;
 484         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 485                 lowest_common_cas = 5;
 486         }
 487         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 488
 489         for (j = max_ram_speed; j>=0; j--) {
 490                 int freq_cas_mask = cas_mask;
 491
 492                 PRINTK_DEBUG("Probing Speed %d\n", j);
 493                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 494                         int current_cas_mask;
 495
 496                         PRINTK_DEBUG("  DIMM: %d\n", i);
 497                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 498                                 continue;
 499                         }
 500
 501                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 502
 503                         while (current_cas_mask) {
 504                                 int highest_supported_cas = 0, current_cas = 0;
 505                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 506                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 507                                         highest_supported_cas = 5;
 508                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 509                                         highest_supported_cas = 4;
 510                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 511                                         highest_supported_cas = 3;
 512                                 }
 513                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 514                                         current_cas = 3;
 515                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 516                                         current_cas = 4;
 517                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 518                                         current_cas = 5;
 519                                 }
 520
 521                                 idx = highest_supported_cas - current_cas;
 522                                 PRINTK_DEBUG("idx=%d, ", idx);
 523                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 524                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 525
 526                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 527                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 528                                         PRINTK_DEBUG(":    OK\n");
 529                                         break;
 530                                 }
 531
 532                                 PRINTK_DEBUG(":    Not fast enough!\n");
 533
 534                                 current_cas_mask &= ~(1 << (current_cas));
 535                         }
 536
 537                         freq_cas_mask &= current_cas_mask;
 538                         if (!current_cas_mask) {
 539                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 540                                 break;
 541                         }
 542                 }
 543                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 544                 if (freq_cas_mask) {
 545                         switch (j) {
 546                         case 0: sysinfo->memory_frequency = 400; break;
 547                         case 1: sysinfo->memory_frequency = 533; break;
 548                         case 2: sysinfo->memory_frequency = 667; break;
 549                         }
 550                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 551                                 sysinfo->cas = 3;
 552                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 553                                 sysinfo->cas = 4;
 554                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 555                                 sysinfo->cas = 5;
 556                         }
 557                         break;
 558                 }
 559         }
 560
 561         if (sysinfo->memory_frequency && sysinfo->cas) {
 562                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 563                                 sysinfo->memory_frequency, sysinfo->cas);
 564         } else {
 565                 die("Could not find common memory frequency and CAS\n");
 566         }
 567 }
 568
 569 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 570 {
 571         int i;
 572         int tRAS_time;
 573         int tRAS_cycles;
 574         int freq_multiplier = 0;
 575
 576         switch (sysinfo->memory_frequency) {
 577         case 400: freq_multiplier = 0x14; break; /* 5ns */
 578         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 579         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 580         }
 581
 582         tRAS_cycles = 4; /* 4 clocks minimum */
 583         tRAS_time = tRAS_cycles * freq_multiplier;
 584
 585         for (i=0; i<2*DIMM_SOCKETS; i++) {
 586                 u8 reg8;
 587
 588                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 589                         continue;
 590
 591                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 592                 if (!reg8) {
 593                         die("Invalid tRAS value.\n");
 594                 }
 595
 596                 while ((tRAS_time >> 2) < reg8) {
 597                         tRAS_time += freq_multiplier;
 598                         tRAS_cycles++;
 599                 }
 600         }
 601         if(tRAS_cycles > 0x18) {
 602                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 603         }
 604
 605         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 606         sysinfo->tras = tRAS_cycles;
 607 }
 608
 609 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 610 {
 611         int i;
 612         int tRP_time;
 613         int tRP_cycles;
 614         int freq_multiplier = 0;
 615
 616         switch (sysinfo->memory_frequency) {
 617         case 400: freq_multiplier = 0x14; break; /* 5ns */
 618         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 619         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 620         }
 621
 622         tRP_cycles = 2; /* 2 clocks minimum */
 623         tRP_time = tRP_cycles * freq_multiplier;
 624
 625         for (i=0; i<2*DIMM_SOCKETS; i++) {
 626                 u8 reg8;
 627
 628                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 629                         continue;
 630
 631                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 632                 if (!reg8) {
 633                         die("Invalid tRP value.\n");
 634                 }
 635
 636                 while (tRP_time < reg8) {
 637                         tRP_time += freq_multiplier;
 638                         tRP_cycles++;
 639                 }
 640         }
 641
 642         if(tRP_cycles > 6) {
 643                 die("DDR-II Module does not support this frequency (tRP error)\n");
 644         }
 645
 646         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 647         sysinfo->trp = tRP_cycles;
 648 }
 649
 650 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 651 {
 652         int i;
 653         int tRCD_time;
 654         int tRCD_cycles;
 655         int freq_multiplier = 0;
 656
 657         switch (sysinfo->memory_frequency) {
 658         case 400: freq_multiplier = 0x14; break; /* 5ns */
 659         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 660         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 661         }
 662
 663         tRCD_cycles = 2; /* 2 clocks minimum */
 664         tRCD_time = tRCD_cycles * freq_multiplier;
 665
 666         for (i=0; i<2*DIMM_SOCKETS; i++) {
 667                 u8 reg8;
 668
 669                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 670                         continue;
 671
 672                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 673                 if (!reg8) {
 674                         die("Invalid tRCD value.\n");
 675                 }
 676
 677                 while (tRCD_time < reg8) {
 678                         tRCD_time += freq_multiplier;
 679                         tRCD_cycles++;
 680                 }
 681         }
 682         if(tRCD_cycles > 6) {
 683                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 684         }
 685
 686         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 687         sysinfo->trcd = tRCD_cycles;
 688 }
 689
 690 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 691 {
 692         int i;
 693         int tWR_time;
 694         int tWR_cycles;
 695         int freq_multiplier = 0;
 696
 697         switch (sysinfo->memory_frequency) {
 698         case 400: freq_multiplier = 0x14; break; /* 5ns */
 699         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 700         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 701         }
 702
 703         tWR_cycles = 2; /* 2 clocks minimum */
 704         tWR_time = tWR_cycles * freq_multiplier;
 705
 706         for (i=0; i<2*DIMM_SOCKETS; i++) {
 707                 u8 reg8;
 708
 709                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 710                         continue;
 711
 712                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 713                 if (!reg8) {
 714                         die("Invalid tWR value.\n");
 715                 }
 716
 717                 while (tWR_time < reg8) {
 718                         tWR_time += freq_multiplier;
 719                         tWR_cycles++;
 720                 }
 721         }
 722         if(tWR_cycles > 5) {
 723                 die("DDR-II Module does not support this frequency (tWR error)\n");
 724         }
 725
 726         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 727         sysinfo->twr = tWR_cycles;
 728 }
 729
 730 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 731 {
 732         int i, index = 0;
 733
 734         const u8 tRFC_cycles[] = {
 735              /* 75 105 127.5 */
 736                 15, 21, 26,     /* DDR2-400 */
 737                 20, 28, 34,     /* DDR2-533 */
 738                 25, 35, 43      /* DDR2-667 */
 739         };
 740
 741         for (i=0; i<2*DIMM_SOCKETS; i++) {
 742                 u8 reg8;
 743
 744                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 745                         continue;
 746
 747                 reg8 = sysinfo->banksize[i*2];
 748                 switch (reg8) {
 749                 case 0x04: reg8 = 0; break;
 750                 case 0x08: reg8 = 1; break;
 751                 case 0x10: reg8 = 2; break;
 752                 case 0x20: reg8 = 3; break;
 753                 }
 754
 755                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 756                         reg8++;
 757
 758                 if (reg8 > 3) {
 759                         /* Can this happen? Go back to 127.5ns just to be sure
 760                          * we don't run out of the array. This may be wrong
 761                          */
 762                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 763                         reg8 = 3;
 764                 }
 765
 766                 if (reg8 > index)
 767                         index = reg8;
 768
 769         }
 770         index--;
 771         switch (sysinfo->memory_frequency) {
 772         case 667: index += 3; /* Fallthrough */
 773         case 533: index += 3; /* Fallthrough */
 774         case 400: break;
 775         }
 776
 777         sysinfo->trfc = tRFC_cycles[index];
 778         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 779 }
 780
 781 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 782 {
 783         int i;
 784
 785         sysinfo->refresh = 0;
 786
 787         for (i=0; i<2*DIMM_SOCKETS; i++) {
 788                 int refresh;
 789
 790                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 791                         continue;
 792
 793                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 794
 795                 /* 15.6us */
 796                 if (!refresh)
 797                         continue;
 798
 799                 /* Refresh is slower than 15.6us, use 15.6us */
 800                 if (refresh > 2)
 801                         continue;
 802
 803                 if (refresh == 2) {
 804                         sysinfo->refresh = 1;
 805                         break;
 806                 }
 807
 808                 die("DDR-II module has unsupported refresh value\n");
 809         }
 810         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 811 }
 812
 813 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 814 {
 815         int i;
 816
 817         for (i=0; i<2*DIMM_SOCKETS; i++) {
 818                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 819                         continue;
 820
 821                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 822                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 823         }
 824 }
 825
 826 static void sdram_program_dram_width(struct sys_info * sysinfo)
 827 {
 828         u16 c0dramw=0, c1dramw=0;
 829         int idx;
 830
 831         if (sysinfo->dual_channel)
 832                 idx = 2;
 833         else
 834                 idx = 1;
 835
 836         switch (sysinfo->dimm[0]) {
 837         case 0: c0dramw = 0x0000; break; /* x16DS */
 838         case 1: c0dramw = 0x0001; break; /* x8DS */
 839         case 2: c0dramw = 0x0000; break; /* x16SS */
 840         case 3: c0dramw = 0x0005; break; /* x8DDS */
 841         case 4: c0dramw = 0x0000; break; /* NC */
 842         }
 843
 844         switch (sysinfo->dimm[idx]) {
 845         case 0: c1dramw = 0x0000; break; /* x16DS */
 846         case 1: c1dramw = 0x0010; break; /* x8DS */
 847         case 2: c1dramw = 0x0000; break; /* x16SS */
 848         case 3: c1dramw = 0x0050; break; /* x8DDS */
 849         case 4: c1dramw = 0x0000; break; /* NC */
 850         }
 851
 852         if ( !sdram_capabilities_dual_channel() ) {
 853                 /* Single Channel */
 854                 c0dramw |= c1dramw;
 855                 c1dramw = 0;
 856         }
 857
 858         MCHBAR16(C0DRAMW) = c0dramw;
 859         MCHBAR16(C1DRAMW) = c1dramw;
 860 }
 861
 862 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 863 {
 864         int i;
 865
 866         for (i=0; i<16; i++)
 867                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 868 }
 869
 870 static const u32 dq2030[] = {
 871         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 872         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 873         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 874         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 875 };
 876
 877 static const u32 dq2330[] = {
 878         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 879         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 880         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 881         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 882 };
 883
 884 static const u32 cmd2710[] = {
 885         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 886         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 887         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 888         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 889 };
 890
 891 static const u32 cmd3210[] = {
 892         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 893         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 894         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 895         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 896 };
 897
 898 static const u32 clk2030[] = {
 899         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 900         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 901         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 902         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 903 };
 904
 905 static const u32 ctl3215[] = {
 906         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 907         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 908         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 909         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 910 };
 911
 912 static const u32 ctl3220[] = {
 913         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 914         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 915         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 916         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 917 };
 918
 919 static const u32 nc[] = {
 920         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 921         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 922         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 923         0x00000000, 0x00000000, 0x00000000, 0x00000000
 924 };
 925
 926 enum {
 927         DQ2030,
 928         DQ2330,
 929         CMD2710,
 930         CMD3210,
 931         CLK2030,
 932         CTL3215,
 933         CTL3220,
 934         NC,
 935 };
 936
 937 static const u8 dual_channel_slew_group_lookup[] = {
 938         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 939         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 940         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 941         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 942         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 943
 944         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 945         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 946         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 947         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 948         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 949
 950         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 951         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 952         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 953         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 954         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 955
 956         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 957         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 958         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 959         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 960         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 961
 962         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 963         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 964         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 965         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 966 };
 967
 968 static const u8 single_channel_slew_group_lookup[] = {
 969         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 970         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 971         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 972         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 973         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 974
 975         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 976         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 977         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 978         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 979         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 980
 981         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 982         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 983         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 984         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 985         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 986
 987         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 988         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 989         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 990         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
 991         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 992
 993         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 994         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 995         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 996         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
 997 };
 998
 999 static const u32 *slew_group_lookup(int dual_channel, int index)
1000 {
1001         const u8 *slew_group;
1002         /* Dual Channel needs different tables. */
1003         if (dual_channel)
1004                 slew_group   = dual_channel_slew_group_lookup;
1005         else
1006                 slew_group   = single_channel_slew_group_lookup;
1007
1008         switch (slew_group[index]) {
1009         case DQ2030:    return dq2030;
1010         case DQ2330:    return dq2330;
1011         case CMD2710:   return cmd2710;
1012         case CMD3210:   return cmd3210;
1013         case CLK2030:   return clk2030;
1014         case CTL3215:   return ctl3215;
1015         case CTL3220:   return ctl3220;
1016         case NC:        return nc;
1017         }
1018
1019         return nc;
1020 }
1021
1022 #ifdef CHIPSET_I945GM
1023 /* Strength multiplier tables */
1024 static const u8 dual_channel_strength_multiplier[] = {
1025         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1026         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1027         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1028         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1029         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1030         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1031         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1032         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1033         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1034         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1035         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1036         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1037         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1038         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1039         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1040         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1041         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1042         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1043         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1044         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1045         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1046         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1047         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1048         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1049 };
1050
1051 static const u8 single_channel_strength_multiplier[] = {
1052         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1053         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1054         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1055         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1056         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1057         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1058         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1059         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1060         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1061         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1062         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1063         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1064         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1065         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1066         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1067         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1068         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1069         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1070         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1071         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1072         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1073         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1074         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1075         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1076 };
1077 #endif
1078 #ifdef CHIPSET_I945GC
1079 static const u8 dual_channel_strength_multiplier[] = {
1080         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1081         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1082         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1083         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1084         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1085         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1086         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1087         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1088         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1089         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1090         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1091         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1092         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1093         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1094         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1095         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1096         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1097         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1098         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1099         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1100         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1101         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1102         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1103         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1104 };
1105
1106 static const u8 single_channel_strength_multiplier[] = {
1107         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1108         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1109         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1110         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1111         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1112         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1113         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1114         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1115         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1116         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1117         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1118         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1119         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1120         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1121         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1122         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1123         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1124         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1125         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1126         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1127         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1128         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1129         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1130         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1131 };
1132 #endif
1133
1134 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1135 {
1136         const u8 * strength_multiplier;
1137         int idx, dual_channel;
1138
1139         /* Set Strength Multipliers */
1140
1141         /* Dual Channel needs different tables. */
1142         if (sdram_capabilities_dual_channel()) {
1143                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1144                 strength_multiplier = dual_channel_strength_multiplier;
1145                 dual_channel = 1;
1146                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1147         } else {
1148                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1149                 strength_multiplier = single_channel_strength_multiplier;
1150                 dual_channel = 0;
1151                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1152         }
1153
1154         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1155
1156         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1157         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1158         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1159         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1160         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1161         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1162         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1163         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1164
1165         /* Channel 0 */
1166         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1167         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1168         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1169
1170                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1171         } else {
1172                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1173         }
1174         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1175         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1176         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1177
1178         /* Channel 1 */
1179         if (sysinfo->dual_channel) {
1180                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1181                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1182         } else {
1183                 sdram_write_slew_rates(G7SRPUT, nc);
1184                 sdram_write_slew_rates(G8SRPUT, nc);
1185         }
1186 }
1187
1188 static void sdram_enable_rcomp(void)
1189 {
1190         u32 reg32;
1191         /* Enable Global Periodic RCOMP */
1192         udelay(300);
1193         reg32 = MCHBAR32(GBRCOMPCTL);
1194         reg32 &= ~(1 << 23);
1195         MCHBAR32(GBRCOMPCTL) = reg32;
1196 }
1197
1198 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1199 {
1200         u32 chan0dll = 0, chan1dll = 0;
1201         int i;
1202
1203         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1204
1205         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1206         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1207
1208         /* We drive both channels with the same speed */
1209         switch (sysinfo->memory_frequency) {
1210         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1211         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1212         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1213         }
1214
1215         for (i=0; i < 4; i++) {
1216                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1217                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1218                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1219                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1220         }
1221 }
1222
1223 static void sdram_force_rcomp(void)
1224 {
1225         u32 reg32;
1226         u8 reg8;
1227
1228         reg32 = MCHBAR32(ODTC);
1229         reg32 |= (1 << 28);
1230         MCHBAR32(ODTC) = reg32;
1231
1232         reg32 = MCHBAR32(SMSRCTL);
1233         reg32 |= (1 << 0);
1234         MCHBAR32(SMSRCTL) = reg32;
1235
1236         /* Start initial RCOMP */
1237         reg32 = MCHBAR32(GBRCOMPCTL);
1238         reg32 |= (1 << 8);
1239         MCHBAR32(GBRCOMPCTL) = reg32;
1240
1241         reg8 = i945_silicon_revision();
1242         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1243
1244                 reg32 = MCHBAR32(GBRCOMPCTL);
1245                 reg32 |= (3 << 5);
1246                 MCHBAR32(GBRCOMPCTL) = reg32;
1247         }
1248 }
1249
1250 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1251 {
1252         u8 reg8;
1253         u32 reg32;
1254
1255         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1256         /* Enable Data Half Clock Pushout */
1257         reg8 = MCHBAR8(C0HCTC);
1258         reg8 &= ~0x1f;
1259         reg8 |= ( 1 << 0);
1260         MCHBAR8(C0HCTC) = reg8;
1261
1262         reg8 = MCHBAR8(C1HCTC);
1263         reg8 &= ~0x1f;
1264         reg8 |= ( 1 << 0);
1265         MCHBAR8(C1HCTC) = reg8;
1266
1267         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1268         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1269
1270         MCHBAR8(C0WDLLCMC) = 0;
1271         MCHBAR8(C1WDLLCMC) = 0;
1272
1273         /* Program RCOMP Settings */
1274         sdram_program_dram_width(sysinfo);
1275
1276         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1277
1278         /* Indicate that RCOMP programming is done */
1279         reg32 = MCHBAR32(GBRCOMPCTL);
1280         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1281         reg32 |= (3 << 27) | (3 << 0);
1282         MCHBAR32(GBRCOMPCTL) = reg32;
1283
1284         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1285
1286         /* Program DLL Timings */
1287         sdram_program_dll_timings(sysinfo);
1288
1289         /* Force RCOMP cycle */
1290         sdram_force_rcomp();
1291 }
1292
1293 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1294 {
1295         u32 reg32;
1296
1297         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1298
1299         reg32 = MCHBAR32(RCVENMT);
1300         reg32 &= ~(0x3f << 6);
1301         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1302
1303         reg32 |= (1 << 11) | (1 << 9);
1304         MCHBAR32(RCVENMT) = reg32;
1305
1306         reg32 = MCHBAR32(DRTST);
1307         reg32 |= (1 << 3) | (1 << 2);
1308         MCHBAR32(DRTST) = reg32;
1309
1310         reg32 = MCHBAR32(DRTST);
1311         reg32 |= (1 << 6) | (1 << 4);
1312         MCHBAR32(DRTST) = reg32;
1313
1314         asm volatile ("nop; nop;");
1315
1316         reg32 = MCHBAR32(DRTST);
1317
1318         /* Is channel 0 populated? */
1319         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1320                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1321                 reg32 |= (1 << 7) | (1 << 5);
1322         else
1323                 reg32 |= (1 << 31);
1324
1325         /* Is channel 1 populated? */
1326         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1327                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1328                 reg32 |= (1 << 9) | (1 << 8);
1329         else
1330                 reg32 |= (1 << 30);
1331
1332         MCHBAR32(DRTST) = reg32;
1333
1334         /* Activate DRAM Channel IO Buffers */
1335         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1336                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1337                 reg32 = MCHBAR32(C0DRC1);
1338                 reg32 |= (1 << 8);
1339                 MCHBAR32(C0DRC1) = reg32;
1340         }
1341         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1342                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1343                 reg32 = MCHBAR32(C1DRC1);
1344                 reg32 |= (1 << 8);
1345                 MCHBAR32(C1DRC1) = reg32;
1346         }
1347 }
1348
1349 struct dimm_size {
1350         unsigned long side1;
1351         unsigned long side2;
1352 };
1353
1354 static struct dimm_size sdram_get_dimm_size(u16 device)
1355 {
1356         /* Calculate the log base 2 size of a DIMM in bits */
1357         struct dimm_size sz;
1358         int value, low, rows, columns;
1359
1360         sz.side1 = 0;
1361         sz.side2 = 0;
1362
1363         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1364         if (rows < 0) goto hw_err;
1365         if ((rows & 0xf) == 0) goto val_err;
1366         sz.side1 += rows & 0xf;
1367
1368         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1369         if (columns < 0) goto hw_err;
1370         if ((columns & 0xf) == 0) goto val_err;
1371         sz.side1 += columns & 0xf;
1372
1373         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1374         if (value < 0) goto hw_err;
1375         if ((value & 0xff) == 0) goto val_err;
1376         sz.side1 += log2(value & 0xff);
1377
1378         /* Get the module data width and convert it to a power of two */
1379         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1380         if (value < 0) goto hw_err;
1381         value &= 0xff;
1382         value <<= 8;
1383
1384         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1385         if (low < 0) goto hw_err;
1386         value = value | (low & 0xff);
1387         if ((value != 72) && (value != 64)) goto val_err;
1388         sz.side1 += log2(value);
1389
1390         /* side 2 */
1391         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1392
1393         if (value < 0) goto hw_err;
1394         value &= 7;
1395         value++;
1396         if (value == 1) goto out;
1397         if (value != 2) goto val_err;
1398
1399         /* Start with the symmetrical case */
1400         sz.side2 = sz.side1;
1401
1402         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1403
1404         /* Don't die here, I have not come across any of these to test what
1405          * actually happens.
1406          */
1407         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1408
1409         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1410         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1411
1412         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1413         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1414
1415         goto out;
1416
1417  val_err:
1418         die("Bad SPD value\n");
1419  hw_err:
1420         /* If a hardware error occurs the spd rom probably does not exist.
1421          * In this case report that there is no memory
1422          */
1423         sz.side1 = 0;
1424         sz.side2 = 0;
1425  out:
1426         return sz;
1427 }
1428
1429 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1430 {
1431         int i;
1432
1433         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1434                 struct dimm_size sz;
1435
1436                 sysinfo->banksize[i * 2] = 0;
1437                 sysinfo->banksize[(i * 2) + 1] = 0;
1438
1439                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1440                         continue;
1441
1442                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1443
1444                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1445
1446                 if (sz.side1 < 30)
1447                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1448
1449                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1450
1451                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1452
1453                 if (!sz.side2)
1454                         continue;
1455
1456                 /* If there is a second side, it has to have at least 128M, too */
1457                 if (sz.side2 < 30)
1458                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1459
1460                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1461
1462                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1463         }
1464 }
1465
1466 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1467 {
1468         int i;
1469         int cum0, cum1, tolud, tom;
1470
1471         printk(BIOS_DEBUG, "Setting RAM size... \n");
1472
1473         cum0 = 0;
1474         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1475                 cum0 += sysinfo->banksize[i];
1476                 MCHBAR8(C0DRB0+i) = cum0;
1477         }
1478
1479         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1480         cum1 = cum0;
1481
1482         /* Exception: Interleaved starts from the beginning */
1483         if (sysinfo->interleaved)
1484                 cum1 = 0;
1485
1486 #if 0
1487         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1488         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1489                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1490                 cum1 = 0;
1491 #endif
1492
1493         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1494                 cum1 += sysinfo->banksize[i + 4];
1495                 MCHBAR8(C1DRB0+i) = cum1;
1496         }
1497
1498         /* Set TOLUD Top Of Low Usable DRAM */
1499         if (sysinfo->interleaved)
1500                 tolud = (cum0 + cum1) << 1;
1501         else
1502                 tolud = (cum1 ? cum1 : cum0)  << 1;
1503
1504         /* The TOM register has a different format */
1505         tom = tolud >> 3;
1506
1507         /* Limit the value of TOLUD to leave some space for PCI memory. */
1508         if (tolud > 0xd0)
1509                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1510
1511         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1512
1513         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1514         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1515         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1516
1517         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1518
1519         return 0;
1520 }
1521
1522 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1523 {
1524         int i, value;
1525         u16 dra0=0, dra1=0, dra = 0;
1526
1527         printk(BIOS_DEBUG, "Setting row attributes... \n");
1528         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1529                 u16 device;
1530                 u8 columnsrows;
1531
1532                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1533                         continue;
1534                 }
1535
1536                 device = DIMM_SPD_BASE + i;
1537
1538                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1539                 columnsrows = (value & 0x0f);
1540
1541                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1542                 columnsrows |= (value & 0xf) << 4;
1543
1544                 switch (columnsrows) {
1545                 case 0x9d: dra = 2; break;
1546                 case 0xad: dra = 3; break;
1547                 case 0xbd: dra = 4; break;
1548                 case 0xae: dra = 3; break;
1549                 case 0xbe: dra = 4; break;
1550                 default: die("Unsupported Rows/Columns. (DRA)");
1551                 }
1552
1553                 /* Double Sided DIMMs? */
1554                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1555                         dra = (dra << 4) | dra;
1556                 }
1557
1558                 if (i < DIMM_SOCKETS)
1559                         dra0 |= (dra << (i*8));
1560                 else
1561                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1562         }
1563
1564         MCHBAR16(C0DRA0) = dra0;
1565         MCHBAR16(C1DRA0) = dra1;
1566
1567         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1568         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1569
1570         return 0;
1571 }
1572
1573 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1574 {
1575         u32 off32;
1576         int i;
1577
1578         MCHBAR16(C1BNKARC) &= 0xff00;
1579         MCHBAR16(C0BNKARC) &= 0xff00;
1580
1581         off32 = C0BNKARC;
1582         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1583                 /* Switch to second channel */
1584                 if (i == DIMM_SOCKETS)
1585                         off32 = C1BNKARC;
1586
1587                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1588                         continue;
1589
1590                 if (sysinfo->banks[i] != 8)
1591                         continue;
1592
1593                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1594
1595                 if (i & 1)
1596                         MCHBAR16(off32) |= 0x50;
1597                 else
1598                         MCHBAR16(off32) |= 0x05;
1599         }
1600 }
1601
1602 #define REFRESH_7_8US   1
1603 #define REFRESH_15_6US  0
1604 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1605 {
1606         u32 reg32;
1607
1608         if (sysinfo->refresh == REFRESH_7_8US) {
1609                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1610         } else {
1611                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1612         }
1613
1614         MCHBAR32(C0DRC0) &= ~(7 << 8);
1615         MCHBAR32(C0DRC0) |= reg32;
1616
1617         MCHBAR32(C1DRC0) &= ~(7 << 8);
1618         MCHBAR32(C1DRC0) |= reg32;
1619 }
1620
1621 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1622 {
1623         u32 reg32;
1624         int i;
1625
1626         reg32 = MCHBAR32(C0DRC1);
1627
1628         for (i=0; i < 4; i++) {
1629                 if (sysinfo->banksize[i] == 0) {
1630                         reg32 |= (1 << (16 + i));
1631                 }
1632         }
1633
1634         reg32 |= (1 << 12);
1635
1636         reg32 |= (1 << 11);
1637         MCHBAR32(C0DRC1) = reg32;
1638
1639         /* Do we have to do this if we're in Single Channel Mode?  */
1640         reg32 = MCHBAR32(C1DRC1);
1641
1642         for (i=4; i < 8; i++) {
1643                 if (sysinfo->banksize[i] == 0) {
1644                         reg32 |= (1 << (12 + i));
1645                 }
1646         }
1647
1648         reg32 |= (1 << 12);
1649
1650         reg32 |= (1 << 11);
1651         MCHBAR32(C1DRC1) = reg32;
1652 }
1653
1654 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1655 {
1656         u32 reg32;
1657         int i;
1658
1659         reg32 = MCHBAR32(C0DRC2);
1660
1661         for (i=0; i < 4; i++) {
1662                 if (sysinfo->banksize[i] == 0) {
1663                         reg32 |= (1 << (24 + i));
1664                 }
1665         }
1666         MCHBAR32(C0DRC2) = reg32;
1667
1668         reg32 = MCHBAR32(C1DRC2);
1669
1670         for (i=4; i < 8; i++) {
1671                 if (sysinfo->banksize[i] == 0) {
1672                         reg32 |= (1 << (20 + i));
1673                 }
1674         }
1675         MCHBAR32(C1DRC2) = reg32;
1676 }
1677
1678 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1679 {
1680         u32 reg32, off32;
1681         u32 tWTR;
1682         u32 temp_drt;
1683         int i, page_size;
1684
1685         static const u8 const drt0_table[] = {
1686           /* CL 3, 4, 5 */
1687                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1688                 4, 5, 6,        /* FSB667, DDR533/400 */
1689                 4, 5, 6,        /* FSB667, DDR667 */
1690         };
1691
1692         static const u8 const cas_table[] = {
1693                 2, 1, 0, 3
1694         };
1695
1696         reg32 = MCHBAR32(C0DRC0);
1697         reg32 |= (1 << 2);      /* Burst Length 8 */
1698         reg32 &= ~( (1 << 13) | (1 << 12) );
1699         MCHBAR32(C0DRC0) = reg32;
1700
1701         reg32 = MCHBAR32(C1DRC0);
1702         reg32 |= (1 << 2);      /* Burst Length 8 */
1703         reg32 &= ~( (1 << 13) | (1 << 12) );
1704         MCHBAR32(C1DRC0) = reg32;
1705
1706         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1707                         SYSINFO_DIMM_NOT_POPULATED) {
1708                 reg32 = MCHBAR32(C0DRC0);
1709                 reg32 |= (1 << 15);
1710                 MCHBAR32(C0DRC0) = reg32;
1711         }
1712
1713         sdram_program_refresh_rate(sysinfo);
1714
1715         sdram_program_cke_tristate(sysinfo);
1716
1717         sdram_program_odt_tristate(sysinfo);
1718
1719         /* Calculate DRT0 */
1720
1721         temp_drt = 0;
1722
1723         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1724         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1725         temp_drt |= (reg32 << 28);
1726
1727         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1728         reg32 += sysinfo->trp;
1729         temp_drt |= (reg32 << 4);
1730
1731         if (sysinfo->memory_frequency == 667) {
1732                 tWTR = 3; /* 667MHz */
1733         } else {
1734                 tWTR = 2; /* 400 and 533 */
1735         }
1736
1737         /* B2B Write to Read Command Spacing */
1738         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1739         temp_drt |= (reg32 << 24);
1740
1741         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1742         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1743
1744         /* Program Write Auto Precharge to Activate */
1745         off32 = 0;
1746         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1747                 off32 += 3;
1748         }
1749         if (sysinfo->memory_frequency == 667) {
1750                 off32 += 3;
1751         }
1752         off32 += sysinfo->cas - 3;
1753         reg32 = drt0_table[off32];
1754         temp_drt |= (reg32 << 11);
1755
1756         /* Read Auto Precharge to Activate */
1757
1758         temp_drt |= (8 << 0);
1759
1760         MCHBAR32(C0DRT0) = temp_drt;
1761         MCHBAR32(C1DRT0) = temp_drt;
1762
1763         /* Calculate DRT1 */
1764
1765         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1766
1767         /* DRAM RASB Precharge */
1768         temp_drt |= (sysinfo->trp - 2) << 0;
1769
1770         /* DRAM RASB to CASB Delay */
1771         temp_drt |= (sysinfo->trcd - 2) << 4;
1772
1773         /* CASB Latency */
1774         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1775
1776         /* Refresh Cycle Time */
1777         temp_drt |= (sysinfo->trfc) << 10;
1778
1779         /* Pre-All to Activate Delay */
1780         temp_drt |= (0 << 16);
1781
1782         /* Precharge to Precharge Delay stays at 1 clock */
1783         temp_drt |= (0 << 18);
1784
1785         /* Activate to Precharge Delay */
1786         temp_drt |= (sysinfo->tras << 19);
1787
1788         /* Read to Precharge (tRTP) */
1789         if (sysinfo->memory_frequency == 667) {
1790                 temp_drt |= (1 << 28);
1791         } else {
1792                 temp_drt |= (0 << 28);
1793         }
1794
1795         /* Determine page size */
1796         reg32 = 0;
1797         page_size = 1; /* Default: 1k pagesize */
1798         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1799                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1800                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1801                         page_size = 2; /* 2k pagesize */
1802         }
1803
1804         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1805                 reg32 = 1;
1806         }
1807         if (sysinfo->memory_frequency == 667) {
1808                 reg32 = page_size;
1809         }
1810
1811         temp_drt |= (reg32 << 30);
1812
1813         MCHBAR32(C0DRT1) = temp_drt;
1814         MCHBAR32(C1DRT1) = temp_drt;
1815
1816         /* Program DRT2 */
1817         reg32 = MCHBAR32(C0DRT2);
1818         reg32 &= ~(1 << 8);
1819         MCHBAR32(C0DRT2) = reg32;
1820
1821         reg32 = MCHBAR32(C1DRT2);
1822         reg32 &= ~(1 << 8);
1823         MCHBAR32(C1DRT2) = reg32;
1824
1825         /* Calculate DRT3 */
1826         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1827
1828         /* Get old tRFC value */
1829         reg32 = MCHBAR32(C0DRT1) >> 10;
1830         reg32 &= 0x3f;
1831
1832         /* 788nS - tRFC */
1833         switch (sysinfo->memory_frequency) {
1834         case 400: /* 5nS */
1835                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1836                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1837                 break;
1838         case 533: /* 3.75nS */
1839                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1840                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1841                 break;
1842         case 667: /* 3nS */
1843                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1844                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1845                 break;
1846         }
1847
1848         temp_drt |= reg32;
1849
1850         MCHBAR32(C0DRT3) = temp_drt;
1851         MCHBAR32(C1DRT3) = temp_drt;
1852 }
1853
1854 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1855 {
1856         u32 reg32;
1857
1858         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1859
1860         if (sdram_capabilities_interleave() &&
1861                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1862                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1863                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1864                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1865                 /* Both channels equipped with DIMMs of the same size */
1866                 sysinfo->interleaved = 1;
1867         } else {
1868                 sysinfo->interleaved = 0;
1869         }
1870
1871         reg32 = MCHBAR32(DCC);
1872         reg32 &= ~(7 << 0);
1873
1874         if(sysinfo->interleaved) {
1875                 /* Dual Channel Interleaved */
1876                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1877                 reg32 |= (1 << 1);
1878         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1879                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1880                 /* Channel 1 only */
1881                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1882                 reg32 |= (1 << 2);
1883         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1884                         SYSINFO_DIMM_NOT_POPULATED) {
1885                 /* Dual Channel Assymetric */
1886                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1887                 reg32 |= (1 << 0);
1888         } else {
1889                 /* All bits 0 means Single Channel 0 operation */
1890                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1891         }
1892
1893         reg32 |= (1 << 10);
1894
1895         MCHBAR32(DCC) = reg32;
1896
1897         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1898 }
1899
1900 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1901 {
1902         volatile u16 reg16;
1903
1904         MCHBAR32(PLLMON) = 0x80800000;
1905
1906         sysinfo->fsb_frequency = fsbclk();
1907         if (sysinfo->fsb_frequency == -1)
1908                 die("Unsupported FSB speed");
1909
1910         /* Program CPCTL according to FSB speed */
1911         /* Only write the lower byte */
1912         switch (sysinfo->fsb_frequency) {
1913         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1914         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1915         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1916         }
1917
1918         MCHBAR16(CPCTL) &= ~(1 << 11);
1919
1920         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1921 }
1922
1923 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1924 {
1925         u8  reg8;
1926         u16 reg16;
1927         u8  freq, second_vco, voltage;
1928
1929 #define CRCLK_166MHz    0x00
1930 #define CRCLK_200MHz    0x01
1931 #define CRCLK_250MHz    0x03
1932 #define CRCLK_400MHz    0x05
1933
1934 #define CDCLK_200MHz    0x00
1935 #define CDCLK_320MHz    0x40
1936
1937 #define VOLTAGE_1_05    0x00
1938 #define VOLTAGE_1_50    0x01
1939
1940         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1941
1942         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1943
1944         voltage = VOLTAGE_1_05;
1945         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1946                 voltage = VOLTAGE_1_50;
1947         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1948
1949         /* Gate graphics hardware for frequency change */
1950         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1951         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1952         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1953
1954         /* Get graphics frequency capabilities */
1955         reg8 = sdram_capabilities_core_frequencies();
1956
1957         freq = CRCLK_250MHz;
1958         switch (reg8) {
1959         case GFX_FREQUENCY_CAP_ALL:
1960                 if (voltage == VOLTAGE_1_05)
1961                         freq = CRCLK_250MHz;
1962                 else
1963                         freq = CRCLK_400MHz;
1964                 break;
1965         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1966         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1967         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
1968         }
1969
1970         if (freq != CRCLK_400MHz) {
1971                 /* What chipset are we? Force 166MHz for GMS */
1972                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1973                 if (reg8==2)
1974                         freq = CRCLK_166MHz;
1975         }
1976
1977         printk(BIOS_DEBUG, "Render: ");
1978         switch (freq) {
1979         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
1980         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
1981         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
1982         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
1983         }
1984
1985         if (i945_silicon_revision() == 0) {
1986                 sysinfo->mvco4x = 1;
1987         } else {
1988                 sysinfo->mvco4x = 0;
1989         }
1990
1991         second_vco = 0;
1992
1993         if (voltage == VOLTAGE_1_50) {
1994                 second_vco = 1;
1995         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
1996                 u16 mem = sysinfo->memory_frequency;
1997                 u16 fsb = sysinfo->fsb_frequency;
1998
1999                 if ( (fsb == 667 && mem == 533) ||
2000                      (fsb == 533 && mem == 533) ||
2001                      (fsb == 533 && mem == 400)) {
2002                         second_vco = 1;
2003                 }
2004
2005                 if (fsb == 667 && mem == 533)
2006                         sysinfo->mvco4x = 1;
2007         }
2008
2009         if (second_vco) {
2010                 sysinfo->clkcfg_bit7=1;
2011         } else {
2012                 sysinfo->clkcfg_bit7=0;
2013         }
2014
2015         /* Graphics Core Render Clock */
2016         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2017         reg16 &= ~( (7 << 0) | (1 << 13) );
2018         reg16 |= freq;
2019         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2020
2021         /* Graphics Core Display Clock */
2022         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2023         reg8 &= ~( (1<<7) | (7<<4) );
2024
2025         if (voltage == VOLTAGE_1_05) {
2026                 reg8 |= CDCLK_200MHz;
2027                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2028         } else {
2029                 reg8 |= CDCLK_320MHz;
2030                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2031         }
2032         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2033
2034         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2035
2036         reg8 |= (1<<3) | (1<<1);
2037         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2038
2039         reg8 |= 0x0f;
2040         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2041
2042         /* Ungate core render and display clocks */
2043         reg8 &= 0xf0;
2044         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2045 }
2046
2047 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2048 {
2049         u32 clkcfg;
2050         u8 reg8;
2051
2052         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2053
2054         clkcfg = MCHBAR32(CLKCFG);
2055
2056         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2057
2058         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2059
2060         if (sysinfo->mvco4x) {
2061                 printk(BIOS_DEBUG, "MVCO 4x, ");
2062                 clkcfg &= ~(1 << 12);
2063         }
2064
2065         if (sysinfo->clkcfg_bit7) {
2066                 printk(BIOS_DEBUG, "second VCO, ");
2067
2068                 clkcfg |= (1 << 7);
2069         }
2070
2071         switch (sysinfo->memory_frequency) {
2072         case 400: clkcfg |= (2 << 4); break;
2073         case 533: clkcfg |= (3 << 4); break;
2074         case 667: clkcfg |= (4 << 4); break;
2075         default: die("Target Memory Frequency Error");
2076         }
2077
2078         if (MCHBAR32(CLKCFG) == clkcfg) {
2079                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2080                 return;
2081         }
2082
2083         MCHBAR32(CLKCFG) = clkcfg;
2084
2085         /* Make sure the following code is in the
2086          * cache before we execute it.
2087          */
2088         goto cache_code;
2089 vco_update:
2090         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2091         reg8 &= ~(1 << 7);
2092         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2093
2094         clkcfg &= ~(1 << 10);
2095         MCHBAR32(CLKCFG) = clkcfg;
2096         clkcfg |= (1 << 10);
2097         MCHBAR32(CLKCFG) = clkcfg;
2098
2099         __asm__ __volatile__ (
2100                 "       movl $0x100, %%ecx\n"
2101                 "delay_update:\n"
2102                 "       nop\n"
2103                 "       nop\n"
2104                 "       nop\n"
2105                 "       nop\n"
2106                 "       loop delay_update\n"
2107                 : /* No outputs */
2108                 : /* No inputs */
2109                 : "%ecx"
2110                 );
2111
2112         clkcfg &= ~(1 << 10);
2113         MCHBAR32(CLKCFG) = clkcfg;
2114
2115         goto out;
2116 cache_code:
2117         goto vco_update;
2118 out:
2119
2120         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2121         printk(BIOS_DEBUG, "ok\n");
2122 }
2123
2124 static void sdram_program_clock_crossing(void)
2125 {
2126         int idx = 0;
2127
2128         /**
2129          * We add the indices according to our clocks from CLKCFG.
2130          */
2131 #ifdef CHIPSET_I945GM
2132         static const u32 data_clock_crossing[] = {
2133                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2134                 0xffffffff, 0xffffffff, /*  nonexistant  */
2135                 0xffffffff, 0xffffffff, /*  nonexistant  */
2136
2137                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2138                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2139                 0xffffffff, 0xffffffff, /*  nonexistant  */
2140
2141                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2142                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2143                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2144
2145                 0xffffffff, 0xffffffff, /*  nonexistant  */
2146                 0xffffffff, 0xffffffff, /*  nonexistant  */
2147                 0xffffffff, 0xffffffff, /*  nonexistant  */
2148
2149                 0xffffffff, 0xffffffff, /*  nonexistant  */
2150                 0xffffffff, 0xffffffff, /*  nonexistant  */
2151                 0xffffffff, 0xffffffff, /*  nonexistant  */
2152         };
2153
2154         static const u32 command_clock_crossing[] = {
2155                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2156                 0xffffffff, 0xffffffff, /*  nonexistant  */
2157                 0xffffffff, 0xffffffff, /*  nonexistant  */
2158
2159                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2160                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2161                 0xffffffff, 0xffffffff, /*  nonexistant  */
2162
2163                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2164                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2165                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2166
2167                 0xffffffff, 0xffffffff, /*  nonexistant  */
2168                 0xffffffff, 0xffffffff, /*  nonexistant  */
2169                 0xffffffff, 0xffffffff, /*  nonexistant  */
2170
2171                 0xffffffff, 0xffffffff, /*  nonexistant  */
2172                 0xffffffff, 0xffffffff, /*  nonexistant  */
2173                 0xffffffff, 0xffffffff, /*  nonexistant  */
2174         };
2175
2176 #endif
2177 #ifdef CHIPSET_I945GC
2178         /* i945 G/P */
2179         static const u32 data_clock_crossing[] = {
2180                 0xffffffff, 0xffffffff, /*  nonexistant  */
2181                 0xffffffff, 0xffffffff, /*  nonexistant  */
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183
2184                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2185                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2186                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2187
2188                 0xffffffff, 0xffffffff, /*  nonexistant  */
2189                 0xffffffff, 0xffffffff, /*  nonexistant  */
2190                 0xffffffff, 0xffffffff, /*  nonexistant  */
2191
2192                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2193                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2194                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2195
2196                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2197                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2198                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2199         };
2200
2201         static const u32 command_clock_crossing[] = {
2202                 0xffffffff, 0xffffffff, /*  nonexistant  */
2203                 0xffffffff, 0xffffffff, /*  nonexistant  */
2204                 0xffffffff, 0xffffffff, /*  nonexistant  */
2205
2206                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2207                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2208                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2209
2210                 0xffffffff, 0xffffffff, /*  nonexistant  */
2211                 0xffffffff, 0xffffffff, /*  nonexistant  */
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213
2214                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2215                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2216                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2217
2218                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2219                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2220                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2221         };
2222 #endif
2223
2224         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2225
2226         printk(BIOS_DEBUG, "MEM=");
2227         switch (memclk()) {
2228         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2229         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2230         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2231         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2232         }
2233
2234         printk(BIOS_DEBUG, " FSB=");
2235         switch (fsbclk()) {
2236         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2237         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2238         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2239         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2240         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2241         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2242         }
2243
2244         if (command_clock_crossing[idx]==0xffffffff) {
2245                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2246         }
2247
2248         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2249         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2250
2251         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2252         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2253         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2254         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2255
2256         printk(BIOS_DEBUG, "... ok\n");
2257 }
2258
2259 static void sdram_disable_fast_dispatch(void)
2260 {
2261         u32 reg32;
2262
2263         reg32 = MCHBAR32(FSBPMC3);
2264         reg32 |= (1 << 1);
2265         MCHBAR32(FSBPMC3) = reg32;
2266
2267         reg32 = MCHBAR32(SBTEST);
2268         reg32 |= (3 << 1);
2269         MCHBAR32(SBTEST) = reg32;
2270 }
2271
2272 static void sdram_pre_jedec_initialization(void)
2273 {
2274         u32 reg32;
2275
2276         reg32 = MCHBAR32(WCC);
2277         reg32 &= 0x113ff3ff;
2278         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2279         MCHBAR32(WCC) = reg32;
2280
2281         MCHBAR32(SMVREFC) |= (1 << 6);
2282
2283         MCHBAR32(MMARB0) &= ~(3 << 17);
2284         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2285
2286         MCHBAR32(MMARB1) &= ~(7 << 8);
2287         MCHBAR32(MMARB1) |= (3 << 8);
2288
2289         /* Adaptive Idle Timer Control */
2290         MCHBAR32(C0AIT) = 0x000006c4;
2291         MCHBAR32(C0AIT+4) = 0x871a066d;
2292
2293         MCHBAR32(C1AIT) = 0x000006c4;
2294         MCHBAR32(C1AIT+4) = 0x871a066d;
2295 }
2296
2297 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2298 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2299 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2300 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2301 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2302 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2303 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2304 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2305
2306 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2307 {
2308         u32 chan0 = 0, chan1 = 0;
2309         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2310
2311         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2312                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2313         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2314                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2315         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2316         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2317
2318         if (sdram_capabilities_enhanced_addressing_xor()) {
2319                 if (!sysinfo->interleaved) {
2320                         /* Single Channel & Dual Channel Assymetric */
2321                         if (chan0_populated) {
2322                                 if (chan0_dualsided) {
2323                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2324                                 } else {
2325                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2326                                 }
2327                         }
2328                         if (chan1_populated) {
2329                                 if (chan1_dualsided) {
2330                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2331                                 } else {
2332                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2333                                 }
2334                         }
2335                 } else {
2336                         /* Interleaved has always both channels populated */
2337                         if (chan0_dualsided) {
2338                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2339                         } else {
2340                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2341                         }
2342
2343                         if (chan1_dualsided) {
2344                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2345                         } else {
2346                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2347                         }
2348                 }
2349         } else {
2350                 if (!sysinfo->interleaved) {
2351                         /* Single Channel & Dual Channel Assymetric */
2352                         if (chan0_populated) {
2353                                 if (chan0_dualsided) {
2354                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2355                                 } else {
2356                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2357                                 }
2358                         }
2359                         if (chan1_populated) {
2360                                 if (chan1_dualsided) {
2361                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2362                                 } else {
2363                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2364                                 }
2365                         }
2366                 } else {
2367                         /* Interleaved has always both channels populated */
2368                         if (chan0_dualsided) {
2369                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2370                         } else {
2371                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2372                         }
2373
2374                         if (chan1_dualsided) {
2375                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2376                         } else {
2377                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2378                         }
2379                 }
2380         }
2381
2382         MCHBAR32(C0DRC1) &= 0x00ffffff;
2383         MCHBAR32(C0DRC1) |= chan0;
2384         MCHBAR32(C1DRC1) &= 0x00ffffff;
2385         MCHBAR32(C1DRC1) |= chan1;
2386 }
2387
2388 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2389 {
2390         u32 reg32;
2391
2392         /* Enable Channel XORing for Dual Channel Interleave */
2393         if (sysinfo->interleaved) {
2394
2395                 reg32 = MCHBAR32(DCC);
2396 #if CHANNEL_XOR_RANDOMIZATION
2397                 reg32 &= ~(1 << 10);
2398                 reg32 |= (1 << 9);
2399 #else
2400                 reg32 &= ~(1 << 9);
2401 #endif
2402                 MCHBAR32(DCC) = reg32;
2403         }
2404
2405         /* DRAM mode optimizations */
2406         sdram_enhanced_addressing_mode(sysinfo);
2407
2408         reg32 = MCHBAR32(FSBPMC3);
2409         reg32 &= ~(1 << 1);
2410         MCHBAR32(FSBPMC3) = reg32;
2411
2412         reg32 = MCHBAR32(SBTEST);
2413         reg32 &= ~(1 << 2);
2414         MCHBAR32(SBTEST) = reg32;
2415
2416         reg32 = MCHBAR32(SBOCC);
2417         reg32 &= 0xffbdb6ff;
2418         reg32 |= (0xbdb6 << 8) | (1 << 0);
2419         MCHBAR32(SBOCC) = reg32;
2420 }
2421
2422 static void sdram_power_management(struct sys_info *sysinfo)
2423 {
2424         u8 reg8;
2425         u16 reg16;
2426         u32 reg32;
2427         int integrated_graphics = 1;
2428         int i;
2429
2430         reg32 = MCHBAR32(C0DRT2);
2431         reg32 &= 0xffffff00;
2432         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2433         reg32 |= (1 << 5) | (1 << 4);
2434         MCHBAR32(C0DRT2) = reg32;
2435
2436         reg32 = MCHBAR32(C1DRT2);
2437         reg32 &= 0xffffff00;
2438         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2439         reg32 |= (1 << 5) | (1 << 4);
2440         MCHBAR32(C1DRT2) = reg32;
2441
2442         reg32 = MCHBAR32(C0DRC1);
2443
2444         reg32 |= (1 << 12) | (1 << 11);
2445         MCHBAR32(C0DRC1) = reg32;
2446
2447         reg32 = MCHBAR32(C1DRC1);
2448
2449         reg32 |= (1 << 12) | (1 << 11);
2450         MCHBAR32(C1DRC1) = reg32;
2451
2452         if (i945_silicon_revision()>1) {
2453                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2454                 u16 peg_bits = (1 << 5) | (1 << 0);
2455
2456                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2457         } else {
2458                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2459                 u16 peg_bits = (1 << 5) | (1 << 0);
2460
2461                 /* Rev 0 and 1 */
2462                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2463         }
2464
2465         reg16 = MCHBAR16(UPMC2);
2466         reg16 &= 0xfc00;
2467         reg16 |= 0x0100;
2468         MCHBAR16(UPMC2) = reg16;
2469
2470         MCHBAR32(UPMC3) = 0x000f06ff;
2471
2472         for (i=0; i<5; i++) {
2473                 MCHBAR32(UPMC3) &= ~(1 << 16);
2474                 MCHBAR32(UPMC3) |= (1 << 16);
2475         }
2476
2477         MCHBAR32(GIPMC1) = 0x8000000c;
2478
2479         reg16 = MCHBAR16(CPCTL);
2480         reg16 &= ~(7 << 11);
2481         if (i945_silicon_revision()>2) {
2482                 reg16 |= (6 << 11);
2483         } else {
2484                 reg16 |= (4 << 11);
2485         }
2486         MCHBAR16(CPCTL) = reg16;
2487
2488 #if 0
2489         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2490 #else
2491         if (i945_silicon_revision() != 0) {
2492 #endif
2493                 switch (sysinfo->fsb_frequency) {
2494                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2495                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2496                 }
2497         } else {
2498                 switch (sysinfo->fsb_frequency) {
2499                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2500                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2501                 }
2502         }
2503
2504         MCHBAR32(FSBPMC1) = 0x8000000c;
2505
2506         reg32 = MCHBAR32(C2C3TT);
2507         reg32 &= 0xffff0000;
2508         switch (sysinfo->fsb_frequency) {
2509         case 667: reg32 |= 0x0600; break;
2510         case 533: reg32 |= 0x0480; break;
2511         }
2512         MCHBAR32(C2C3TT) = reg32;
2513
2514         reg32 = MCHBAR32(C3C4TT);
2515         reg32 &= 0xffff0000;
2516         switch (sysinfo->fsb_frequency) {
2517         case 667: reg32 |= 0x0b80; break;
2518         case 533: reg32 |= 0x0980; break;
2519         }
2520         MCHBAR32(C3C4TT) = reg32;
2521
2522         if (i945_silicon_revision() == 0) {
2523                 MCHBAR32(ECO) &= ~(1 << 16);
2524         } else {
2525                 MCHBAR32(ECO) |= (1 << 16);
2526         }
2527
2528 #if 0
2529
2530         if (i945_silicon_revision() == 0) {
2531                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2532         } else {
2533                 MCHBAR32(FSBPMC3) |= (1 << 29);
2534         }
2535 #endif
2536         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2537
2538         MCHBAR32(FSBPMC3) |= (1 << 21);
2539
2540         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2541
2542         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2543
2544         reg32 = MCHBAR32(FSBPMC4);
2545         reg32 &= ~(3 << 24);
2546         reg32 |= ( 2 << 24);
2547         MCHBAR32(FSBPMC4) = reg32;
2548
2549         MCHBAR32(FSBPMC4) |= (1 << 21);
2550
2551         MCHBAR32(FSBPMC4) |= (1 << 5);
2552
2553         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2554                 /* stepping 0 and 1 or CPUID 6e8 */
2555                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2556         } else {
2557                 MCHBAR32(FSBPMC4) |= (1 << 4);
2558         }
2559
2560         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2561         reg8 |= (1 << 4);
2562         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2563
2564         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2565         reg8 |= (1 << 2);
2566         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2567
2568 #ifdef C2_SELF_REFRESH_DISABLE
2569
2570         if (integrated_graphics) {
2571                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2572                 MCHBAR16(MIPMC4) = 0x0468;
2573                 MCHBAR16(MIPMC5) = 0x046c;
2574                 MCHBAR16(MIPMC6) = 0x046c;
2575         } else {
2576                 MCHBAR16(MIPMC4) = 0x6468;
2577                 MCHBAR16(MIPMC5) = 0x646c;
2578                 MCHBAR16(MIPMC6) = 0x646c;
2579         }
2580 #else
2581         if (integrated_graphics) {
2582                 MCHBAR16(MIPMC4) = 0x04f8;
2583                 MCHBAR16(MIPMC5) = 0x04fc;
2584                 MCHBAR16(MIPMC6) = 0x04fc;
2585         } else {
2586                 MCHBAR16(MIPMC4) = 0x64f8;
2587                 MCHBAR16(MIPMC5) = 0x64fc;
2588                 MCHBAR16(MIPMC6) = 0x64fc;
2589         }
2590
2591 #endif
2592
2593         reg32 = MCHBAR32(PMCFG);
2594         reg32 &= ~(3 << 17);
2595         reg32 |= (2 << 17);
2596         MCHBAR32(PMCFG) = reg32;
2597
2598         MCHBAR32(PMCFG) |= (1 << 4);
2599
2600         reg32 = MCHBAR32(0xc30);
2601         reg32 &= 0xffffff00;
2602         reg32 |= 0x01;
2603         MCHBAR32(0xc30) = reg32;
2604
2605         MCHBAR32(0xb18) &= ~(1 << 21);
2606 }
2607
2608 static void sdram_thermal_management(void)
2609 {
2610
2611         MCHBAR8(TCO1) = 0x00;
2612         MCHBAR8(TCO0) = 0x00;
2613
2614         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2615          * 0x30/0x32.
2616          */
2617
2618 }
2619
2620 static void sdram_save_receive_enable(void)
2621 {
2622         int i;
2623         u32 reg32;
2624         u8 values[4];
2625
2626         /* The following values are stored to an unused CMOS
2627          * area and restored instead of recalculated in case
2628          * of an S3 resume.
2629          *
2630          * C0WL0REOST [7:0]             -> 8 bit
2631          * C1WL0REOST [7:0]             -> 8 bit
2632          * RCVENMT    [11:8] [3:0]      -> 8 bit
2633          * C0DRT1     [27:24]           -> 4 bit
2634          * C1DRT1     [27:24]           -> 4 bit
2635          */
2636
2637         values[0] = MCHBAR8(C0WL0REOST);
2638         values[1] = MCHBAR8(C1WL0REOST);
2639
2640         reg32 = MCHBAR32(RCVENMT);
2641         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2642
2643         reg32 = MCHBAR32(C0DRT1);
2644         values[3] = (reg32 >> 24) & 0x0f;
2645         reg32 = MCHBAR32(C1DRT1);
2646         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2647
2648         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2649          * so we grad bytes 128 - 131 to save the receive enable values
2650          */
2651
2652         for (i=0; i<4; i++)
2653                 cmos_write(values[i], 128 + i);
2654 }
2655
2656 static void sdram_recover_receive_enable(void)
2657 {
2658         int i;
2659         u32 reg32;
2660         u8 values[4];
2661
2662         for (i=0; i<4; i++)
2663                 values[i] = cmos_read(128 + i);
2664
2665         MCHBAR8(C0WL0REOST) = values[0];
2666         MCHBAR8(C1WL0REOST) = values[1];
2667
2668         reg32 = MCHBAR32(RCVENMT);
2669         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2670         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2671         MCHBAR32(RCVENMT) = reg32;
2672
2673         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2674         reg32 |= (u32)(values[3] & 0x0f) << 24;
2675         MCHBAR32(C0DRT1) = reg32;
2676
2677         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2678         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2679         MCHBAR32(C1DRT1) = reg32;
2680 }
2681
2682 #include "rcven.c"
2683
2684 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2685 {
2686         MCHBAR32(REPC) |= (1 << 0);
2687
2688         /* enable upper CMOS */
2689         RCBA32(0x3400) = (1 << 2);
2690
2691         /* Program Receive Enable Timings */
2692         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2693                 sdram_recover_receive_enable();
2694         } else {
2695                 receive_enable_adjust(sysinfo);
2696                 sdram_save_receive_enable();
2697         }
2698
2699         MCHBAR32(C0DRC1) |= (1 << 6);
2700         MCHBAR32(C1DRC1) |= (1 << 6);
2701         MCHBAR32(C0DRC1) &= ~(1 << 6);
2702         MCHBAR32(C1DRC1) &= ~(1 << 6);
2703
2704         MCHBAR32(MIPMC3) |= (0x0f << 0);
2705 }
2706
2707 /**
2708  * @brief Enable On-Die Termination for DDR2.
2709  *
2710  */
2711
2712 static void sdram_on_die_termination(struct sys_info *sysinfo)
2713 {
2714         static const u32 odt[] = {
2715                 0x00024911, 0xe0010000,
2716                 0x00049211, 0xe0020000,
2717                 0x0006db11, 0xe0030000,
2718         };
2719
2720         u32 reg32;
2721         int cas;
2722
2723         reg32 = MCHBAR32(ODTC);
2724         reg32 &= ~(3 << 16);
2725         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2726         MCHBAR32(ODTC) = reg32;
2727
2728         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2729                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2730                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2731
2732                 reg32 = MCHBAR32(C0ODT);
2733                 reg32 &= ~(7 << 28);
2734                 MCHBAR32(C0ODT) = reg32;
2735                 reg32 = MCHBAR32(C1ODT);
2736                 reg32 &= ~(7 << 28);
2737                 MCHBAR32(C1ODT) = reg32;
2738         }
2739
2740         cas = sysinfo->cas;
2741
2742         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2743         reg32 |= odt[(cas-3) * 2];
2744         MCHBAR32(C0ODT) = reg32;
2745
2746         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2747         reg32 |= odt[(cas-3) * 2];
2748         MCHBAR32(C1ODT) = reg32;
2749
2750         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2751         reg32 |= odt[((cas-3) * 2) + 1];
2752         MCHBAR32(C0ODT + 4) = reg32;
2753
2754         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2755         reg32 |= odt[((cas-3) * 2) + 1];
2756         MCHBAR32(C1ODT + 4) = reg32;
2757 }
2758
2759 /**
2760  * @brief Enable clocks to populated sockets
2761  */
2762
2763 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2764 {
2765         u8 clocks[2] = { 0, 0 };
2766
2767 #ifdef CHIPSET_I945GM
2768 #define CLOCKS_WIDTH 2
2769 #endif
2770 #ifdef CHIPSET_I945GC
2771 #define CLOCKS_WIDTH 3
2772 #endif
2773         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2774                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2775
2776         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2777                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2778
2779         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2780                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2781
2782         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2783                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2784
2785 #ifdef OVERRIDE_CLOCK_DISABLE
2786         /* Usually system firmware turns off system memory clock signals
2787          * to unused SO-DIMM slots to reduce EMI and power consumption.
2788          * However, the Kontron 986LCD-M does not like unused clock
2789          * signals to be disabled.
2790          * If other similar mainboard occur, it would make sense to make
2791          * this an entry in the sysinfo structure, and pre-initialize that
2792          * structure in the mainboard's romstage.c main() function.
2793          * For now an #ifdef will do.
2794          */
2795
2796         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2797         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2798 #endif
2799
2800         MCHBAR8(C0DCLKDIS) = clocks[0];
2801         MCHBAR8(C1DCLKDIS) = clocks[1];
2802 }
2803
2804 #define RTT_ODT_NONE    0
2805 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2806 #define RTT_ODT_75_OHM  (1 << 5)
2807 #define RTT_ODT_150_OHM (1 << 9)
2808
2809 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2810
2811 #define MRS_CAS_3       (3 << 7)
2812 #define MRS_CAS_4       (4 << 7)
2813 #define MRS_CAS_5       (5 << 7)
2814
2815 #define MRS_TWR_3       (2 << 12)
2816 #define MRS_TWR_4       (3 << 12)
2817 #define MRS_TWR_5       (4 << 12)
2818
2819 #define MRS_BT          (1 << 6)
2820
2821 #define MRS_BL4         (2 << 3)
2822 #define MRS_BL8         (3 << 3)
2823
2824 static void sdram_jedec_enable(struct sys_info *sysinfo)
2825 {
2826         int i, nonzero;
2827         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2828
2829         for (i = 0, nonzero = -1; i < 8; i++) {
2830                 if (sysinfo->banksize[i]  == 0) {
2831                         continue;
2832                 }
2833
2834                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2835                 switch (i) {
2836                 case 0:
2837                         /* Start at address 0 */
2838                         bankaddr = 0;
2839                         break;
2840                 case 4:
2841                         if (sysinfo->interleaved) {
2842                                 bankaddr = 0x40;
2843                                 break;
2844                         }
2845                 default:
2846                         if (nonzero != -1) {
2847                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2848                                 bankaddr += sysinfo->banksize[nonzero] <<
2849                                         (sysinfo->interleaved ? 26 : 25);
2850                                 break;
2851                         }
2852                         /* No populated bank hit before. Start at address 0 */
2853                         bankaddr = 0;
2854                 }
2855
2856                 /* We have a bank with a non-zero size.. Remember it
2857                  * for the next offset we have to calculate
2858                  */
2859                 nonzero = i;
2860
2861                 /* Get CAS latency set up */
2862                 switch (sysinfo->cas) {
2863                 case 5: mrsaddr = MRS_CAS_5; break;
2864                 case 4: mrsaddr = MRS_CAS_4; break;
2865                 case 3: mrsaddr = MRS_CAS_3; break;
2866                 default: die("Jedec Error (CAS).\n");
2867                 }
2868
2869                 /* Get tWR set */
2870                 switch (sysinfo->twr) {
2871                 case 5: mrsaddr |= MRS_TWR_5; break;
2872                 case 4: mrsaddr |= MRS_TWR_4; break;
2873                 case 3: mrsaddr |= MRS_TWR_3; break;
2874                 default: die("Jedec Error (tWR).\n");
2875                 }
2876
2877                 /* Set "Burst Type" */
2878                 mrsaddr |= MRS_BT;
2879
2880                 /* Interleaved */
2881                 if (sysinfo->interleaved) {
2882                         mrsaddr = mrsaddr << 1;
2883                 }
2884
2885                 /* Only burst length 8 supported */
2886                 mrsaddr |= MRS_BL8;
2887
2888                 /* Apply NOP */
2889                 PRINTK_DEBUG("Apply NOP\n");
2890                 do_ram_command(RAM_COMMAND_NOP);
2891                 ram_read32(bankaddr);
2892
2893                 /* Precharge all banks */
2894                 PRINTK_DEBUG("All Banks Precharge\n");
2895                 do_ram_command(RAM_COMMAND_PRECHARGE);
2896                 ram_read32(bankaddr);
2897
2898                 /* Extended Mode Register Set (2) */
2899                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2900                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2901                 ram_read32(bankaddr);
2902
2903                 /* Extended Mode Register Set (3) */
2904                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2905                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2906                 ram_read32(bankaddr);
2907
2908                 /* Extended Mode Register Set */
2909                 PRINTK_DEBUG("Extended Mode Register Set\n");
2910                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2911                 tmpaddr = bankaddr;
2912                 if (!sdram_capabilities_dual_channel()) {
2913                         tmpaddr |= RTT_ODT_75_OHM;
2914                 } else if (sysinfo->interleaved) {
2915                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2916                 } else {
2917                         tmpaddr |= RTT_ODT_150_OHM;
2918                 }
2919                 ram_read32(tmpaddr);
2920
2921                 /* Mode Register Set: Reset DLLs */
2922                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2923                 do_ram_command(RAM_COMMAND_MRS);
2924                 tmpaddr = bankaddr;
2925                 tmpaddr |= mrsaddr;
2926                 /* Set DLL reset bit */
2927                 if (sysinfo->interleaved)
2928                         tmpaddr |= (1 << 12);
2929                 else
2930                         tmpaddr |= (1 << 11);
2931                 ram_read32(tmpaddr);
2932
2933                 /* Precharge all banks */
2934                 PRINTK_DEBUG("All Banks Precharge\n");
2935                 do_ram_command(RAM_COMMAND_PRECHARGE);
2936                 ram_read32(bankaddr);
2937
2938                 /* CAS before RAS Refresh */
2939                 PRINTK_DEBUG("CAS before RAS\n");
2940                 do_ram_command(RAM_COMMAND_CBR);
2941
2942                 /* CBR wants two READs */
2943                 ram_read32(bankaddr);
2944                 ram_read32(bankaddr);
2945
2946                 /* Mode Register Set: Enable DLLs */
2947                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2948                 do_ram_command(RAM_COMMAND_MRS);
2949
2950                 tmpaddr = bankaddr;
2951                 tmpaddr |= mrsaddr;
2952                 ram_read32(tmpaddr);
2953
2954                 /* Extended Mode Register Set */
2955                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2956                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2957
2958                 tmpaddr = bankaddr;
2959                 if (!sdram_capabilities_dual_channel()) {
2960
2961                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2962                 } else if (sysinfo->interleaved) {
2963                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2964                 } else {
2965                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2966                 }
2967                 ram_read32(tmpaddr);
2968
2969                 /* Extended Mode Register Set */
2970                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2971                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2972
2973                 tmpaddr = bankaddr;
2974                 if (!sdram_capabilities_dual_channel()) {
2975                         tmpaddr |= RTT_ODT_75_OHM;
2976                 } else if (sysinfo->interleaved) {
2977                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2978                 } else {
2979                         tmpaddr |= RTT_ODT_150_OHM;
2980                 }
2981                 ram_read32(tmpaddr);
2982         }
2983 }
2984
2985 static void sdram_init_complete(void)
2986 {
2987         PRINTK_DEBUG("Normal Operation\n");
2988         do_ram_command(RAM_COMMAND_NORMAL);
2989 }
2990
2991 static void sdram_setup_processor_side(void)
2992 {
2993         if (i945_silicon_revision() == 0)
2994                 MCHBAR32(FSBPMC3) |= (1 << 2);
2995
2996         MCHBAR8(0xb00) |= 1;
2997
2998         if (i945_silicon_revision() == 0)
2999                 MCHBAR32(SLPCTL) |= (1 << 8);
3000 }
3001
3002 /**
3003  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3004  */
3005 void sdram_initialize(int boot_path)
3006 {
3007         struct sys_info sysinfo;
3008         u8 reg8, cas_mask;
3009
3010         sdram_detect_errors();
3011
3012         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3013
3014         memset(&sysinfo, 0, sizeof(sysinfo));
3015
3016         sysinfo.boot_path = boot_path;
3017
3018         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3019         sdram_get_dram_configuration(&sysinfo);
3020
3021         /* Check whether we have stacked DIMMs */
3022         sdram_verify_package_type(&sysinfo);
3023
3024         /* Determine common CAS */
3025         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3026
3027         /* Choose Common Frequency */
3028         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3029
3030         /* Determine smallest common tRAS */
3031         sdram_detect_smallest_tRAS(&sysinfo);
3032
3033         /* Determine tRP */
3034         sdram_detect_smallest_tRP(&sysinfo);
3035
3036         /* Determine tRCD */
3037         sdram_detect_smallest_tRCD(&sysinfo);
3038
3039         /* Determine smallest refresh period */
3040         sdram_detect_smallest_refresh(&sysinfo);
3041
3042         /* Verify all DIMMs support burst length 8 */
3043         sdram_verify_burst_length(&sysinfo);
3044
3045         /* determine tWR */
3046         sdram_detect_smallest_tWR(&sysinfo);
3047
3048         /* Determine DIMM size parameters (rows, columns banks) */
3049         sdram_detect_dimm_size(&sysinfo);
3050
3051         /* determine tRFC */
3052         sdram_detect_smallest_tRFC(&sysinfo);
3053
3054         /* Program PLL settings */
3055         sdram_program_pll_settings(&sysinfo);
3056
3057         /* Program Graphics Frequency */
3058         sdram_program_graphics_frequency(&sysinfo);
3059
3060         /* Program System Memory Frequency */
3061         sdram_program_memory_frequency(&sysinfo);
3062
3063         /* Determine Mode of Operation (Interleaved etc) */
3064         sdram_set_channel_mode(&sysinfo);
3065
3066         /* Program Clock Crossing values */
3067         sdram_program_clock_crossing();
3068
3069         /* Disable fast dispatch */
3070         sdram_disable_fast_dispatch();
3071
3072         /* Enable WIODLL Power Down in ACPI states */
3073         MCHBAR32(C0DMC) |= (1 << 24);
3074         MCHBAR32(C1DMC) |= (1 << 24);
3075
3076         /* Program DRAM Row Boundary/Attribute Registers */
3077
3078         /* program row size DRB and set TOLUD */
3079         sdram_program_row_boundaries(&sysinfo);
3080
3081         /* program page size DRA */
3082         sdram_set_row_attributes(&sysinfo);
3083
3084         /* Program CxBNKARC */
3085         sdram_set_bank_architecture(&sysinfo);
3086
3087         /* Program DRAM Timing and Control registers based on SPD */
3088         sdram_set_timing_and_control(&sysinfo);
3089
3090         /* On-Die Termination Adjustment */
3091         sdram_on_die_termination(&sysinfo);
3092
3093         /* Pre Jedec Initialization */
3094         sdram_pre_jedec_initialization();
3095
3096         /* Perform System Memory IO Initialization */
3097         sdram_initialize_system_memory_io(&sysinfo);
3098
3099         /* Perform System Memory IO Buffer Enable */
3100         sdram_enable_system_memory_io(&sysinfo);
3101
3102         /* Enable System Memory Clocks */
3103         sdram_enable_memory_clocks(&sysinfo);
3104
3105         if (boot_path == BOOT_PATH_NORMAL) {
3106                 /* Jedec Initialization sequence */
3107                 sdram_jedec_enable(&sysinfo);
3108         }
3109
3110         /* Program Power Management Registers */
3111         sdram_power_management(&sysinfo);
3112
3113         /* Post Jedec Init */
3114         sdram_post_jedec_initialization(&sysinfo);
3115
3116         /* Program DRAM Throttling */
3117         sdram_thermal_management();
3118
3119         /* Normal Operations */
3120         sdram_init_complete();
3121
3122         /* Program Receive Enable Timings */
3123         sdram_program_receive_enable(&sysinfo);
3124
3125         /* Enable Periodic RCOMP */
3126         sdram_enable_rcomp();
3127
3128         /* Tell ICH7 that we're done */
3129         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3130         reg8 &= ~(1 << 7);
3131         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3132
3133         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3134
3135         sdram_setup_processor_side();
3136 }
3137
3138 unsigned long get_top_of_ram(void)
3139 {
3140         /* This will not work if TSEG is in place! */
3141         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3142
3143         return (unsigned long) tom;
3144 }
3145