src/northbridge/intel/i945/acpi/hostbridge.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22
  23 Name(_HID,EISAID("PNP0A08"))    // PCIe
  24 Name(_CID,EISAID("PNP0A03"))    // PCI
  25
  26 Name(_ADR, 0)
  27 Name(_BBN, 0)
  28
  29 Device (MCHC)
  30 {
  31         Name(_ADR, 0x00000000)  // 0:0.0
  32
  33         OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
  34         Field (MCHP, DWordAcc, NoLock, Preserve)
  35         {
  36                 Offset (0x40),  // EPBAR
  37                 EPEN,    1,     // Enable
  38                 ,       11,     //
  39                 EPBR,   20,     // EPBAR
  40
  41                 Offset (0x44),  // MCHBAR
  42                 MHEN,    1,     // Enable
  43                 ,       13,     //
  44                 MHBR,   18,     // MCHBAR
  45
  46                 Offset (0x48),  // PCIe BAR
  47                 PXEN,    1,     // Enable
  48                 PXSZ,    2,     // BAR size
  49                 ,       23,     //
  50                 PXBR,    6,     // PCIe BAR
  51
  52                 Offset (0x4c),  // DMIBAR
  53                 DMEN,    1,     // Enable
  54                 ,       11,     //
  55                 DMBR,   20,     // DMIBAR
  56
  57                 // ...
  58
  59                 Offset (0x90),  // PAM0
  60                 ,        4,
  61                 PM0H,    2,
  62                 ,        2,
  63                 Offset (0x91),  // PAM1
  64                 PM1L,    2,
  65                 ,        2,
  66                 PM1H,    2,
  67                 ,        2,
  68                 Offset (0x92),  // PAM2
  69                 PM2L,    2,
  70                 ,        2,
  71                 PM2H,    2,
  72                 ,        2,
  73                 Offset (0x93),  // PAM3
  74                 PM3L,    2,
  75                 ,        2,
  76                 PM3H,    2,
  77                 ,        2,
  78                 Offset (0x94),  // PAM4
  79                 PM4L,    2,
  80                 ,        2,
  81                 PM4H,    2,
  82                 ,        2,
  83                 Offset (0x95),  // PAM5
  84                 PM5L,    2,
  85                 ,        2,
  86                 PM5H,    2,
  87                 ,        2,
  88                 Offset (0x96),  // PAM6
  89                 PM6L,    2,
  90                 ,        2,
  91                 PM6H,    2,
  92                 ,        2,
  93
  94                 Offset (0x9c),  // Top of Low Used Memory
  95                 ,        3,
  96                 TLUD,    5,
  97
  98                 Offset (0xa0),  // Top of Used Memory
  99                 TOM,    16,
 100         }
 101
 102 }
 103
 104
 105 // Current Resource Settings
 106
 107 Method (_CRS, 0, Serialized)
 108 {
 109         Name (MCRS, ResourceTemplate()
 110         {
 111                 // Bus Numbers
 112                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 113                                 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 114
 115                 // IO Region 0
 116                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 117                                 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 118
 119                 // PCI Config Space
 120                 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 121
 122                 // IO Region 1
 123                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 124                                 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 125
 126                 // VGA memory (0xa0000-0xbffff)
 127                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 128                                 Cacheable, ReadWrite,
 129                                 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
 130                                 0x00020000,,, ASEG)
 131
 132                 // OPROM reserved (0xc0000-0xc3fff)
 133                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 134                                 Cacheable, ReadWrite,
 135                                 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
 136                                 0x00004000,,, OPR0)
 137
 138                 // OPROM reserved (0xc4000-0xc7fff)
 139                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 140                                 Cacheable, ReadWrite,
 141                                 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
 142                                 0x00004000,,, OPR1)
 143
 144                 // OPROM reserved (0xc8000-0xcbfff)
 145                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 146                                 Cacheable, ReadWrite,
 147                                 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 148                                 0x00004000,,, OPR2)
 149
 150                 // OPROM reserved (0xcc000-0xcffff)
 151                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 152                                 Cacheable, ReadWrite,
 153                                 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 154                                 0x00004000,,, OPR3)
 155
 156                 // OPROM reserved (0xd0000-0xd3fff)
 157                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 158                                 Cacheable, ReadWrite,
 159                                 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 160                                 0x00004000,,, OPR4)
 161
 162                 // OPROM reserved (0xd4000-0xd7fff)
 163                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 164                                 Cacheable, ReadWrite,
 165                                 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 166                                 0x00004000,,, OPR5)
 167
 168                 // OPROM reserved (0xd8000-0xdbfff)
 169                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 170                                 Cacheable, ReadWrite,
 171                                 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 172                                 0x00004000,,, OPR6)
 173
 174                 // OPROM reserved (0xdc000-0xdffff)
 175                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 176                                 Cacheable, ReadWrite,
 177                                 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 178                                 0x00004000,,, OPR7)
 179
 180                 // BIOS Extension (0xe0000-0xe3fff)
 181                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 182                                 Cacheable, ReadWrite,
 183                                 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 184                                 0x00004000,,, ESG0)
 185
 186                 // BIOS Extension (0xe4000-0xe7fff)
 187                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 188                                 Cacheable, ReadWrite,
 189                                 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 190                                 0x00004000,,, ESG1)
 191
 192                 // BIOS Extension (0xe8000-0xebfff)
 193                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 194                                 Cacheable, ReadWrite,
 195                                 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 196                                 0x00004000,,, ESG2)
 197
 198                 // BIOS Extension (0xec000-0xeffff)
 199                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 200                                 Cacheable, ReadWrite,
 201                                 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 202                                 0x00004000,,, ESG3)
 203
 204                 // System BIOS (0xf0000-0xfffff)
 205                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 206                                 Cacheable, ReadWrite,
 207                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 208                                 0x00010000,,, FSEG)
 209
 210                 // PCI Memory Region (Top of memory-0xfebfffff)
 211                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 212                                 Cacheable, ReadWrite,
 213                                 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
 214                                 0xfec00000,,, PM01)
 215
 216                 // TPM Area (0xfed40000-0xfed44fff)
 217                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 218                                 Cacheable, ReadWrite,
 219                                 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 220                                 0x00005000,,, TPMR)
 221         })
 222
 223         // Find PCI resource area in MCRS
 224         CreateDwordField(MCRS, PM01._MIN, PMIN)
 225         CreateDwordField(MCRS, PM01._MAX, PMAX)
 226         CreateDwordField(MCRS, PM01._LEN, PLEN)
 227
 228         // Fix up PCI memory region:
 229         // Enter actual TOLUD. The TOLUD register contains bits 27-31 of
 230         // the top of memory address.
 231         ShiftLeft (^MCHC.TLUD, 27, PMIN)
 232         Add(Subtract(PMAX, PMIN), 1, PLEN)
 233
 234         Return (MCRS)
 235 }
 236
 237 /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
 238 #include "acpi/i945_pci_irqs.asl"
 239
 240