2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Ronald G. Minnich
5 * Copyright (C) 2003-2004 Eric W. Biederman
6 * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
31 #include <cpu/x86/cache.h>
34 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
36 static void pci_domain_read_resources(device_t dev)
38 struct resource *resource;
41 /* Initialize the system wide io space constraints */
42 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
43 resource->limit = 0xffffUL;
44 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
46 /* Initialize the system wide memory resources constraints */
47 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
48 resource->limit = 0xffffffffULL;
49 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
52 static void ram_resource(device_t dev, unsigned long index,
53 unsigned long basek, unsigned long sizek)
55 struct resource *resource;
60 resource = new_resource(dev, index);
61 resource->base = ((resource_t)basek) << 10;
62 resource->size = ((resource_t)sizek) << 10;
63 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
64 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
67 static void tolm_test(void *gp, struct device *dev, struct resource *new)
69 struct resource **best_p = gp;
70 struct resource *best;
72 if (!best || (best->base > new->base)) {
78 static uint32_t find_pci_tolm(struct bus *bus)
83 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
85 if (min && tolm > min->base) {
91 #if CONFIG_HAVE_HIGH_TABLES==1
92 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
93 extern uint64_t high_tables_base, high_tables_size;
95 static void pci_domain_set_resources(device_t dev)
100 printk_debug("Entered with dev vid = %x\n", dev->vendor);
101 printk_debug("Entered with dev did = %x\n", dev->device);
103 pci_tolm = find_pci_tolm(&dev->link[0]);
104 mc_dev = dev->link[0].children->sibling;
105 printk_debug("MC dev vendor = %x\n", mc_dev->vendor);
106 printk_debug("MC dev device = %x\n", mc_dev->device);
109 /* Figure out which areas are/should be occupied by RAM.
110 * This is all computed in kilobytes and converted to/from
111 * the memory controller right at the edges.
112 * Having different variables in different units is
113 * too confusing to get right. Kilobytes are good up to
114 * 4 Terabytes of RAM...
116 uint16_t tolm_r, vga_mem;
117 unsigned long tomk, tolmk;
118 unsigned long remapbasek, remaplimitk;
121 /* Get the value of the highest DRB. This tells the end of
122 * the physical memory. The units are ticks of 32MB
125 tomk = (unsigned long)pci_read_config8(mc_dev, 0x43);
126 tomk = tomk * 32 * 1024;
127 /* add vga_mem detection */
128 tomk = tomk - 16 * 1024;
129 /* Compute the top of Low memory */
130 tolmk = pci_tolm >> 10;
132 /* The PCI hole does not overlap memory
136 /* Write the ram configuration registers,
137 * preserving the reserved bits.
140 /* Report the memory regions */
141 printk_debug("tomk = %d\n", tomk);
142 printk_debug("tolmk = %d\n", tolmk);
145 /* avoid pam region */
146 ram_resource(dev, idx++, 0, 640);
147 /* ram_resource(dev, idx++, 1024, tolmk - 1024); */
148 ram_resource(dev, idx++, 768, tolmk - 768);
150 #if CONFIG_HAVE_HIGH_TABLES==1
151 /* Leave some space for ACPI, PIRQ and MP tables */
152 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
153 high_tables_size = HIGH_TABLES_SIZE * 1024;
156 assign_resources(&dev->link[0]);
159 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
161 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
165 static struct device_operations pci_domain_ops = {
166 .read_resources = pci_domain_read_resources,
167 .set_resources = pci_domain_set_resources,
168 .enable_resources = enable_childrens_resources,
170 .scan_bus = pci_domain_scan_bus,
173 static void cpu_bus_init(device_t dev)
175 initialize_cpus(&dev->link[0]);
178 static void cpu_bus_noop(device_t dev)
182 static struct device_operations cpu_bus_ops = {
183 .read_resources = cpu_bus_noop,
184 .set_resources = cpu_bus_noop,
185 .enable_resources = cpu_bus_noop,
186 .init = cpu_bus_init,
190 static void enable_dev(struct device *dev)
192 struct device_path path;
194 /* Set the operations if it is a special bus type */
195 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
196 dev->ops = &pci_domain_ops;
199 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
200 dev->ops = &cpu_bus_ops;
204 struct chip_operations northbridge_intel_i855gme_ops = {
205 CHIP_NAME("Intel 855GME Northbridge")
206 .enable_dev = enable_dev,