src/northbridge/intel/i855/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <assert.h>
  22 #include <spd.h>
  23 #include <sdram_mode.h>
  24 #include <stdlib.h>
  25 #include <delay.h>
  26 #include "i855.h"
  27
  28 #define VALIDATE_DIMM_COMPATIBILITY
  29
  30 /* Debugging macros. */
  31 #if CONFIG_DEBUG_RAM_SETUP
  32 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  33 #define DUMPNORTH()             dump_pci_device(NORTHBRIDGE_MMC)
  34 #else
  35 #define PRINTK_DEBUG(x...)
  36 #define DUMPNORTH()
  37 #endif
  38
  39 #define delay() udelay(200)
  40
  41 #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)
  42
  43 /* DRC[10:8] - Refresh Mode Select (RMS).
  44  * 0x0 for Refresh Disabled (Self Refresh)
  45  * 0x1 for Refresh interval 15.6 us for 133MHz
  46  * 0x2 for Refresh interval 7.8 us for 133MHz
  47  * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode)
  48  */
  49 #define RAM_COMMAND_REFRESH             0x1
  50
  51 /* DRC[6:4] - SDRAM Mode Select (SMS). */
  52 #define RAM_COMMAND_SELF_REFRESH        0x0
  53 #define RAM_COMMAND_NOP                 0x1
  54 #define RAM_COMMAND_PRECHARGE           0x2
  55 #define RAM_COMMAND_MRS                 0x3
  56 #define RAM_COMMAND_EMRS                0x4
  57 #define RAM_COMMAND_CBR                 0x6
  58 #define RAM_COMMAND_NORMAL              0x7
  59
  60 /* DRC[29] - Initialization Complete (IC). */
  61 #define RAM_COMMAND_IC                  0x1
  62
  63 struct dimm_size {
  64         unsigned int side1;
  65         unsigned int side2;
  66 };
  67
  68 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
  69 /*                              DEFINITIONS                                       */
  70 /**********************************************************************************/
  71
  72 static const uint32_t refresh_frequency[] = {
  73         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  74          * (RMS) value (array index)
  75          * 0 == least frequent refresh (longest interval between refreshes)
  76          * [0] disabled  -> 0
  77          * [1] 15.6 usec -> 2
  78          * [2]  7.8 usec -> 3
  79          * [3] 64   usec -> 1
  80          * [4] reserved  -> 0
  81          * [5] reserved  -> 0
  82          * [6] reserved  -> 0
  83          * [7] 64 clocks -> 4
  84          */
  85         0, 2, 3, 1, 0, 0, 0, 4
  86 };
  87
  88 static const uint32_t refresh_rate_map[] = {
  89         /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode
  90          * Select values (array value)
  91          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  92          * The i855 supports only 15.6 us (1), 7.8 us (2) and
  93          * 64 clock (481 ns) (7) refresh.
  94          * [0] ==  15.625 us -> 15.6 us
  95          * [1] ==   3.9   us -> 481  ns
  96          * [2] ==   7.8   us ->  7.8 us
  97          * [3] ==  31.3   us -> 15.6 us
  98          * [4] ==  62.5   us -> 15.6 us
  99          * [5] == 125     us -> 15.6 us
 100          */
 101         1, 7, 2, 1, 1, 1
 102 };
 103
 104 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
 105
 106 /*-----------------------------------------------------------------------------
 107 SPD functions.
 108 -----------------------------------------------------------------------------*/
 109
 110 static void die_on_spd_error(int spd_return_value)
 111 {
 112         if (spd_return_value < 0)
 113                 PRINTK_DEBUG("Error reading SPD info: got %d\n", spd_return_value);
 114 /*
 115         if (spd_return_value < 0)
 116                 die("Error reading SPD info\n");
 117 */
 118 }
 119
 120 //----------------------------------------------------------------------------------
 121 // Function:            sdram_spd_get_page_size
 122 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 123 // Return Value:        struct dimm_size - log2(page size) for each side of the DIMM.
 124 // Description:         Calculate the page size for each physical bank of the DIMM:
 125 //                                              log2(page size) = (# columns) + log2(data width)
 126 //
 127 //                                      NOTE: page size is the total number of data bits in a row.
 128 //
 129 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
 130 {
 131         uint16_t module_data_width;
 132         int value;
 133         struct dimm_size pgsz;
 134
 135         pgsz.side1 = 0;
 136         pgsz.side2 = 0;
 137
 138         // Side 1
 139         value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 140         die_on_spd_error(value);
 141
 142         pgsz.side1 = value & 0xf;       // # columns in bank 1
 143
 144         /* Get the module data width and convert it to a power of two */
 145         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 146         die_on_spd_error(value);
 147
 148         module_data_width = (value & 0xff) << 8;
 149
 150         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 151         die_on_spd_error(value);
 152
 153         module_data_width |= (value & 0xff);
 154
 155         pgsz.side1 += log2(module_data_width);
 156
 157         /* side two */
 158         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 159         die_on_spd_error(value);
 160
 161 /*
 162         if (value > 2)
 163                 die("Bad SPD value\n");
 164 */
 165         if (value > 2)
 166                 PRINTK_DEBUG("Bad SPD value\n");
 167
 168         if (value == 2) {
 169                 pgsz.side2 = pgsz.side1;        // Assume symmetric banks until we know differently
 170                 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 171                 die_on_spd_error(value);
 172
 173                 if ((value & 0xf0) != 0) {
 174                         // Asymmetric banks
 175                         pgsz.side2 -= value & 0xf;      /* Subtract out columns on side 1 */
 176                         pgsz.side2 += (value >> 4) & 0xf;       /* Add in columns on side 2 */
 177                 }
 178         }
 179
 180         return pgsz;
 181 }
 182
 183 //----------------------------------------------------------------------------------
 184 // Function:            sdram_spd_get_width
 185 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 186 // Return Value:        dimm_size - width in bits of each DIMM side's DRAMs.
 187 // Description:         Read the width in bits of each DIMM side's DRAMs via SPD.
 188 //                                      (i.e. 4, 8, 16)
 189 //
 190 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 191 {
 192         int value;
 193         struct dimm_size width;
 194
 195         width.side1 = 0;
 196         width.side2 = 0;
 197
 198         value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 199         die_on_spd_error(value);
 200
 201         width.side1 = value & 0x7f;     // Mask off bank 2 flag
 202
 203         if (value & 0x80) {
 204                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 205         } else {
 206                 // If bank 2 exists, it's the same width as bank 1
 207                 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 208                 die_on_spd_error(value);
 209
 210 #ifdef ROMCC_IF_BUG_FIXED
 211                 if (value == 2)
 212                         width.side2 = width.side1;
 213 #else
 214                 switch (value) {
 215                 case 2:
 216                         width.side2 = width.side1;
 217                         break;
 218
 219                 default:
 220                         break;
 221                 }
 222 #endif
 223         }
 224
 225         return width;
 226 }
 227
 228 //----------------------------------------------------------------------------------
 229 // Function:            spd_get_dimm_size
 230 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 231 // Return Value:        dimm_size - log2(number of bits) for each side of the DIMM
 232 // Description:         Calculate the log base 2 size in bits of both DIMM sides.
 233 //                      log2(# bits) = (# columns) + log2(data width) +
 234 //                                         (# rows) + log2(banks per SDRAM)
 235 //
 236 //                      Note that it might be easier to use SPD byte 31 here, it has the
 237 //                      DIMM size as a multiple of 4MB.  The way we do it now we can size
 238 //                      both sides of an asymmetric dimm.
 239 //
 240 static struct dimm_size spd_get_dimm_size(unsigned dimm)
 241 {
 242         int value;
 243
 244         // Start with log2(page size)
 245         struct dimm_size sz = sdram_spd_get_page_size(dimm);
 246
 247         if (sz.side1 > 0) {
 248                 value = spd_read_byte(dimm, SPD_NUM_ROWS);
 249                 die_on_spd_error(value);
 250
 251                 sz.side1 += value & 0xf;
 252
 253                 if (sz.side2 > 0) {
 254                         // Double-sided DIMM
 255                         if (value & 0xF0)
 256                                 sz.side2 += value >> 4; // Asymmetric
 257                         else
 258                                 sz.side2 += value;      // Symmetric
 259                 }
 260
 261                 value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 262                 die_on_spd_error(value);
 263
 264                 value = log2(value);
 265                 sz.side1 += value;
 266                 if (sz.side2 > 0)
 267                         sz.side2 += value;
 268         }
 269
 270         return sz;
 271 }
 272
 273 //----------------------------------------------------------------------------------
 274 // Function:            spd_get_supported_dimms
 275 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 276 //                                              SMBus addresses of DIMM slots on the mainboard
 277 // Return Value:        uint8_t - a bitmask indicating which sockets contain a compatible DIMM.
 278 // Description:         Scan for compatible DIMMs.
 279 //
 280 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 281 {
 282         int i;
 283         uint8_t dimm_mask = 0;
 284
 285         for (i = 0; i < DIMM_SOCKETS; i++) {
 286                 uint16_t dimm = ctrl->channel0[i];
 287
 288 #ifdef VALIDATE_DIMM_COMPATIBILITY
 289                 struct dimm_size page_size;
 290                 struct dimm_size sdram_width;
 291 #endif
 292                 int spd_value;
 293
 294                 if (dimm == 0)
 295                         continue;       // No such socket on this mainboard
 296
 297                 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
 298                         continue;
 299
 300 #ifdef VALIDATE_DIMM_COMPATIBILITY
 301                 if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) {
 302                         PRINTK_DEBUG("Skipping DIMM with unsupported voltage: %02x\n", spd_value);
 303                         continue;       // Unsupported voltage
 304                 }
 305
 306 /*
 307                 // E7501 does not support unregistered DIMMs
 308                 spd_value = spd_read_byte(dimm, SPD_MODULE_ATTRIBUTES);
 309                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 310                         PRINTK_DEBUG("Skipping unregistered DIMM: %02x\n", spd_value);
 311                         continue;
 312                 }
 313 */
 314
 315                 page_size = sdram_spd_get_page_size(dimm);
 316                 sdram_width = sdram_spd_get_width(dimm);
 317
 318                 // Validate DIMM page size
 319                 // The i855 only supports page sizes of 4, 8, 16 KB per channel
 320                 // NOTE:  4 KB =  32 Kb = 2^15
 321                 //       16 KB = 128 Kb = 2^17
 322
 323                 if ((page_size.side1 < 15) || (page_size.side1 > 17)) {
 324                         PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side1);
 325                         continue;
 326                 }
 327
 328                 // If DIMM is double-sided, verify side2 page size
 329                 if (page_size.side2 != 0) {
 330                         if ((page_size.side2 < 15) || (page_size.side2 > 17)) {
 331                                 PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side2);
 332                                 continue;
 333                         }
 334                 }
 335                 // Validate SDRAM width
 336                 // The i855 only supports x8 and x16 devices
 337                 if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) {
 338                         PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 339                         continue;
 340                 }
 341
 342                 // If DIMM is double-sided, verify side2 width
 343                 if (sdram_width.side2 != 0) {
 344                         if ((sdram_width.side2 != 8)
 345                             && (sdram_width.side2 != 16)) {
 346                                 PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 347                                 continue;
 348                         }
 349                 }
 350 #endif
 351                 // Made it through all the checks, this DIMM is usable
 352                 dimm_mask |= (1 << i);
 353         }
 354
 355         return dimm_mask;
 356 }
 357
 358 /*-----------------------------------------------------------------------------
 359 DIMM-initialization functions.
 360 -----------------------------------------------------------------------------*/
 361 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 362 {
 363         int i;
 364         u32 reg32;
 365         uint8_t dimm_start_32M_multiple = 0;
 366         uint16_t i855_mode_bits = jedec_mode_bits;
 367
 368         /* Configure the RAM command. */
 369         reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 370         reg32 &= ~(7 << 4);
 371         reg32 |= (command << 4);
 372         PRINTK_DEBUG("  Sending RAM command 0x%08x\n", reg32);
 373         pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
 374
 375         // RAM_COMMAND_NORMAL is an exception.
 376         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 377
 378         if (command != RAM_COMMAND_NORMAL) {
 379
 380                 // Send the command to all DIMMs by accessing a memory location within each
 381                 // NOTE: for mode select commands, some of the location address bits
 382                 // are part of the command
 383
 384                 // Map JEDEC mode bits to i855
 385                 if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
 386                         /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
 387                         i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
 388                 }
 389
 390                 for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
 391                         uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
 392                         if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
 393
 394                                 uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
 395                                 PRINTK_DEBUG("  Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
 396                                 read32(dimm_start_address + i855_mode_bits);
 397
 398                                 // Set the start of the next DIMM
 399                                 dimm_start_32M_multiple = dimm_end_32M_multiple;
 400                         }
 401                 }
 402         }
 403 }
 404
 405 static void set_initialize_complete(const struct mem_controller *ctrl)
 406 {
 407         uint32_t drc_reg;
 408
 409         drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 410         drc_reg |= (1 << 29);
 411         pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
 412 }
 413
 414 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 415 {
 416         int i;
 417
 418         print_debug("Ram enable 1\n");
 419         delay();
 420         delay();
 421
 422         /* NOP command */
 423         PRINTK_DEBUG(" NOP\n");
 424         do_ram_command(RAM_COMMAND_NOP, 0);
 425         delay();
 426         delay();
 427         delay();
 428
 429         /* Pre-charge all banks (at least 200 us after NOP) */
 430         PRINTK_DEBUG(" Pre-charging all banks\n");
 431         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 432         delay();
 433         delay();
 434         delay();
 435
 436         print_debug("Ram enable 4\n");
 437         do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
 438         delay();
 439         delay();
 440         delay();
 441
 442         print_debug("Ram enable 5\n");
 443         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
 444
 445         print_debug("Ram enable 6\n");
 446         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 447         delay();
 448         delay();
 449         delay();
 450
 451         /* 8 CBR refreshes (Auto Refresh) */
 452         PRINTK_DEBUG(" 8 CBR refreshes\n");
 453         for(i = 0; i < 8; i++) {
 454                 do_ram_command(RAM_COMMAND_CBR, 0);
 455                 delay();
 456                 delay();
 457                 delay();
 458         }
 459
 460         print_debug("Ram enable 8\n");
 461         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
 462
 463         /* Set GME-M Mode Select bits back to NORMAL operation mode */
 464         PRINTK_DEBUG(" Normal operation mode\n");
 465         do_ram_command(RAM_COMMAND_NORMAL, 0);
 466         delay();
 467         delay();
 468         delay();
 469
 470         print_debug("Ram enable 9\n");
 471         set_initialize_complete(ctrl);
 472
 473         delay();
 474         delay();
 475         delay();
 476         delay();
 477         delay();
 478
 479         print_debug("After configuration:\n");
 480         /* dump_pci_devices(); */
 481
 482         /*
 483         print_debug("\n\n***** RAM TEST *****\n");
 484         ram_check(0, 0xa0000);
 485         ram_check(0x100000, 0x40000000);
 486         */
 487 }
 488
 489 /*-----------------------------------------------------------------------------
 490 DIMM-independant configuration functions.
 491 -----------------------------------------------------------------------------*/
 492
 493 /**
 494   * Set only what I need until it works, then make it figure things out on boot
 495   * assumes only one dimm is populated
 496   */
 497
 498 static void sdram_set_registers(const struct mem_controller *ctrl)
 499 {
 500         /*
 501         print_debug("Before configuration:\n");
 502         dump_pci_devices();
 503         */
 504 }
 505
 506 static void spd_set_row_attributes(const struct mem_controller *ctrl, uint8_t dimm_mask)
 507 {
 508         int i;
 509         uint16_t row_attributes = 0;
 510
 511         for (i = 0; i < DIMM_SOCKETS; i++) {
 512                 uint16_t dimm = ctrl->channel0[i];
 513                 struct dimm_size page_size;
 514                 struct dimm_size sdram_width;
 515
 516                 if (!(dimm_mask & (1 << i))) {
 517                         row_attributes |= 0x77 << (i << 3);
 518                         continue;       // This DIMM not usable
 519                 }
 520
 521                 // Get the relevant parameters via SPD
 522                 page_size = sdram_spd_get_page_size(dimm);
 523                 sdram_width = sdram_spd_get_width(dimm);
 524
 525                 // Update the DRAM Row Attributes.
 526                 // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3
 527                 // NOTE:  2 KB =  16 Kb = 2^14
 528                 row_attributes |= (page_size.side1 - 14) << (i << 3);   // Side 1 of each DIMM is an EVEN row
 529
 530                 if (sdram_width.side2 > 0)
 531                         row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4);     // Side 2 is ODD
 532                 else
 533                         row_attributes |= 7 << ((i << 3) + 4);
 534                 /* go to the next DIMM */
 535         }
 536
 537         PRINTK_DEBUG("DRA: %04x\n", row_attributes);
 538
 539         /* Write the new row attributes register */
 540         pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes);
 541 }
 542
 543 static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint8_t dimm_mask)
 544 {
 545         int i;
 546
 547         // Initial settings
 548         u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 549         u32 system_refresh_mode = (controller_mode >> 7) & 7;
 550
 551         controller_mode |= (1 << 20);  // ECC
 552         controller_mode |= (1 << 15);  // RAS lockout
 553         controller_mode |= (1 << 12);  // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected?????
 554         controller_mode |= (2 << 10);  // FIXME: Undocumented, really needed?????
 555
 556         for (i = 0; i < DIMM_SOCKETS; i++) {
 557                 uint16_t dimm = ctrl->channel0[i];
 558                 uint32_t dimm_refresh_mode;
 559                 int value;
 560                 u8 tRCD, tRP;
 561
 562                 if (!(dimm_mask & (1 << i))) {
 563                         continue;       // This DIMM not usable
 564                 }
 565
 566                 // Disable ECC mode if any one of the DIMMs does not support ECC
 567                 value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE);
 568                 die_on_spd_error(value);
 569                 if (value != ERROR_SCHEME_ECC)
 570                         controller_mode &= ~(3 << 20);
 571
 572                 value = spd_read_byte(dimm, SPD_REFRESH);
 573                 die_on_spd_error(value);
 574                 value &= 0x7f;  // Mask off self-refresh bit
 575                 if (value > MAX_SPD_REFRESH_RATE) {
 576                         print_err("unsupported refresh rate\n");
 577                         continue;
 578                 }
 579                 // Get the appropriate i855 refresh mode for this DIMM
 580                 dimm_refresh_mode = refresh_rate_map[value];
 581                 if (dimm_refresh_mode > 7) {
 582                         print_err("unsupported refresh rate\n");
 583                         continue;
 584                 }
 585                 // If this DIMM requires more frequent refresh than others,
 586                 // update the system setting
 587                 if (refresh_frequency[dimm_refresh_mode] >
 588                     refresh_frequency[system_refresh_mode])
 589                         system_refresh_mode = dimm_refresh_mode;
 590
 591                 /* FIXME: is this correct? */
 592                 tRCD = spd_read_byte(dimm, SPD_tRCD);
 593                 tRP = spd_read_byte(dimm, SPD_tRP);
 594                 if (tRCD != tRP) {
 595                         PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);
 596                         controller_mode &= ~(1 << 15);
 597                 }
 598
 599                 /* go to the next DIMM */
 600         }
 601
 602         controller_mode &= ~(7 << 7);
 603         controller_mode |= (system_refresh_mode << 7);
 604         PRINTK_DEBUG("DRC: %08x\n", controller_mode);
 605
 606         pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode);
 607 }
 608
 609 static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
 610 {
 611         int i;
 612         u32 dram_timing;
 613
 614         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
 615         // NOTE: i82822 supports only 2.0 and 2.5
 616         uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
 617         uint8_t slowest_row_precharge = 0;
 618         uint8_t slowest_ras_cas_delay = 0;
 619         uint8_t slowest_active_to_precharge_delay = 0;
 620
 621         for (i = 0; i < DIMM_SOCKETS; i++) {
 622                 uint16_t dimm = ctrl->channel0[i];
 623                 int value;
 624                 uint32_t current_cas_latency;
 625                 uint32_t dimm_compatible_cas_latencies;
 626                 if (!(dimm_mask & (1 << i)))
 627                         continue;       // This DIMM not usable
 628
 629                 value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
 630                 PRINTK_DEBUG("SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value);
 631                 die_on_spd_error(value);
 632
 633                 dimm_compatible_cas_latencies = value & 0x7f;   // Start with all supported by DIMM
 634                 PRINTK_DEBUG("dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies);
 635
 636                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
 637                 PRINTK_DEBUG("current_cas_latency: %d\n", current_cas_latency);
 638
 639                 // Can we support the highest CAS# latency?
 640                 value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 641                 die_on_spd_error(value);
 642                 PRINTK_DEBUG("SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf);
 643
 644                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
 645                 if (value > 0x75) {
 646                         // Our bus is too fast for this CAS# latency
 647                         // Remove it from the bitmask of those supported by the DIMM that are compatible
 648                         dimm_compatible_cas_latencies &= ~current_cas_latency;
 649                         PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 650                 }
 651                 // Can we support the next-highest CAS# latency (max - 0.5)?
 652
 653                 current_cas_latency >>= 1;
 654                 if (current_cas_latency != 0) {
 655                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
 656                         die_on_spd_error(value);
 657                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf);
 658                         if (value > 0x75) {
 659                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 660                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 661                         }
 662                 }
 663                 // Can we support the next-highest CAS# latency (max - 1.0)?
 664                 current_cas_latency >>= 1;
 665                 if (current_cas_latency != 0) {
 666                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
 667                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf);
 668                         die_on_spd_error(value);
 669                         if (value > 0x75) {
 670                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 671                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 672                         }
 673                 }
 674                 // Restrict the system to CAS# latencies compatible with this DIMM
 675                 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
 676
 677                 value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME);
 678                 die_on_spd_error(value);
 679                 if (value > slowest_row_precharge)
 680                         slowest_row_precharge = value;
 681
 682                 value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY);
 683                 die_on_spd_error(value);
 684                 if (value > slowest_ras_cas_delay)
 685                         slowest_ras_cas_delay = value;
 686
 687                 value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 688                 die_on_spd_error(value);
 689                 if (value > slowest_active_to_precharge_delay)
 690                         slowest_active_to_precharge_delay = value;
 691
 692                 /* go to the next DIMM */
 693         }
 694         PRINTK_DEBUG("CAS latency: %d\n", system_compatible_cas_latencies);
 695
 696         dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT);
 697         dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK);
 698         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 699
 700         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
 701                 dram_timing |= DRT_CAS_2_0;
 702         } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
 703                 dram_timing |= DRT_CAS_2_5;
 704         } else
 705                 die("No CAS# latencies compatible with all DIMMs!!\n");
 706
 707         uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK;
 708
 709         /* tRP */
 710
 711         PRINTK_DEBUG("slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3);
 712         // i855 supports only 2, 3 or 4 clocks for tRP
 713         if (slowest_row_precharge > ((30 << 2)))
 714                 die("unsupported DIMM tRP");    //  > 30.0 ns: 5 or more clocks
 715         else if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
 716                 dram_timing |= DRT_TRP_4;       //  > 22.5 ns: 4 or more clocks
 717         else if (slowest_row_precharge > (15 << 2))
 718                 dram_timing |= DRT_TRP_3;       //  > 15.0 ns: 3 clocks
 719         else
 720                 dram_timing |= DRT_TRP_2;       // <= 15.0 ns: 2 clocks
 721
 722         /*  tRCD */
 723
 724         PRINTK_DEBUG("slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3);
 725         // i855 supports only 2, 3 or 4 clocks for tRCD
 726         if (slowest_ras_cas_delay > ((30 << 2)))
 727                 die("unsupported DIMM tRCD");   //  > 30.0 ns: 5 or more clocks
 728         else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
 729                 dram_timing |= DRT_RCD_4;       //  > 22.5 ns: 4 or more clocks
 730         else if (slowest_ras_cas_delay > (15 << 2))
 731                 dram_timing |= DRT_RCD_3;       //  > 15.0 ns: 3 clocks
 732         else
 733                 dram_timing |= DRT_RCD_2;       // <= 15.0 ns: 2 clocks
 734
 735         /* tRAS, min */
 736
 737         PRINTK_DEBUG("slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay);
 738         // i855 supports only 5, 6, 7 or 8 clocks for tRAS
 739         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns
 740         if (slowest_active_to_precharge_delay > 60)
 741                 die("unsupported DIMM tRAS");   // > 52 ns:      8 or more clocks
 742         else if (slowest_active_to_precharge_delay > 52)
 743                 dram_timing |= DRT_TRAS_MIN_8;  // 46-52 ns:     7 clocks
 744         else if (slowest_active_to_precharge_delay > 45)
 745                 dram_timing |= DRT_TRAS_MIN_7;  // 46-52 ns:     7 clocks
 746         else if (slowest_active_to_precharge_delay > 37)
 747                 dram_timing |= DRT_TRAS_MIN_6;  // 38-45 ns:     6 clocks
 748         else
 749                 dram_timing |= DRT_TRAS_MIN_5;  // < 38 ns:      5 clocks
 750
 751         /* FIXME: guess work starts here...
 752          *
 753          * Intel refers to DQ turn-arround values for back to calculate the values,
 754          * but i have no idea what this means
 755          */
 756
 757         /*
 758          * Back to Back Read-Write command spacing (DDR, different Rows/Bank)
 759          */
 760         /* Set to a 3 clock back to back read to write turn around.
 761          *  2 is a good delay if the CAS latency is 2.0 */
 762         dram_timing &= ~(3 << 28);
 763         if (current_cas_latency == DRT_CAS_2_0)
 764                 dram_timing |= (2 << 28);       // 2 clocks
 765         else
 766                 dram_timing |= (1 << 28);       // 3 clocks
 767
 768         /*
 769          * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank)
 770          */
 771         dram_timing &= ~(3 << 26);
 772         if (current_cas_latency == DRT_CAS_2_0)
 773                 dram_timing |= (2 << 26);       // 5 clocks
 774         else
 775                 dram_timing |= (1 << 26);       // 6 clocks
 776
 777         /*
 778          * Back To Back Read-Read commands spacing (DDR, different Rows):
 779          */
 780         dram_timing &= ~(1 << 25);
 781         dram_timing |= (1 << 25);       // 3 clocks
 782
 783         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 784         pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing);
 785 }
 786
 787 static void spd_set_dram_size(const struct mem_controller *ctrl, uint8_t dimm_mask)
 788 {
 789         int i;
 790         int total_dram = 0;
 791         uint32_t drb_reg = 0;
 792
 793         for (i = 0; i < DIMM_SOCKETS; i++) {
 794                 uint16_t dimm = ctrl->channel0[i];
 795                 struct dimm_size sz;
 796
 797                 if (!(dimm_mask & (1 << i))) {
 798                         /* fill values even for not present DIMMs */
 799                         drb_reg |= (total_dram << (i * 16));
 800                         drb_reg |= (total_dram << ((i * 16) + 8));
 801
 802                         continue;       // This DIMM not usable
 803                 }
 804                 sz = spd_get_dimm_size(dimm);
 805
 806                 total_dram += (1 << (sz.side1 - 28));
 807                 drb_reg |= (total_dram << (i * 16));
 808
 809                 total_dram += (1 << (sz.side2 - 28));
 810                 drb_reg |= (total_dram << ((i * 16) + 8));
 811         }
 812         PRINTK_DEBUG("DRB: %08x\n", drb_reg);
 813         pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg);
 814 }
 815
 816
 817 static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
 818 {
 819         uint32_t pwrmg_reg;
 820
 821         pwrmg_reg = 0x10f10430;
 822         pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg);
 823 }
 824
 825 static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
 826 {
 827         uint32_t dtc_reg = 0;
 828
 829         /* DDR SDRAM Throttle Mode (TMODE):
 830          *   0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-
 831          *          DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT
 832          */
 833         dtc_reg |= (3 << 28);
 834
 835         /* Read Counter Based Power Throttle Control (RCTC):
 836          *   0 = 85%
 837          */
 838         dtc_reg |= (0 << 24);
 839
 840         /* Write Counter Based Power Throttle Control (WCTC):
 841          *   0 = 85%
 842          */
 843         dtc_reg |= (0 << 20);
 844
 845         /* Read Thermal Based Power Throttle Control (RTTC):
 846          *   0xA = 20%
 847          */
 848         dtc_reg |= (0xA << 16);
 849
 850         /* Write Thermal Based Power Throttle Control (WTTC):
 851          *   0xA = 20%
 852          */
 853         dtc_reg |= (0xA << 12);
 854
 855         /* Counter Based Throttle Lock (CTLOCK): */
 856         dtc_reg |= (0 << 11);
 857
 858         /* Thermal Throttle Lock (TTLOCK): */
 859         dtc_reg |= (0 << 10);
 860
 861         /* Thermal Power Throttle Control fields Enable: */
 862         dtc_reg |= (1 << 9);
 863
 864         /* High Priority Stream Throttling Enable: */
 865         dtc_reg |= (0 << 8);
 866
 867         /* Global DDR SDRAM Sampling Window (GDSW): */
 868         dtc_reg |= 0xff;
 869         PRINTK_DEBUG("DTC: %08x\n", dtc_reg);
 870         pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg);
 871 }
 872
 873 static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value)
 874 {
 875 #if CONFIG_DEBUG_RAM_SETUP
 876         u32 value1 = pci_read_config32(ctrl->d0, reg);
 877 #endif
 878         pci_write_config32(ctrl->d0, reg, new_value);
 879 #if CONFIG_DEBUG_RAM_SETUP
 880         u32 value2 = pci_read_config32(ctrl->d0, reg);
 881         PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 882 #endif
 883 }
 884
 885 /* if ram still doesn't work do this function */
 886 static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
 887 {
 888         spd_update(ctrl, 0x74, 0x00000001);
 889         spd_update(ctrl, 0x78, 0x001fe974);
 890         spd_update(ctrl, 0x80, 0x00af0039);
 891         spd_update(ctrl, 0x84, 0x0000033c);
 892         spd_update(ctrl, 0x88, 0x00000010);
 893
 894         spd_update(ctrl, 0xc0, 0x00000003);
 895 }
 896
 897 static void northbridge_set_registers(void)
 898 {
 899         u16 value;
 900         int video_memory = 0;
 901
 902         printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
 903
 904         /* Set the value for Fixed DRAM Hole Control Register */
 905         pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
 906
 907         /* Set the value for Programable Attribute Map Registers
 908          * Ideally, this should be R/W for as many ranges as possible.
 909          */
 910         pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
 911         pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
 912         pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
 913         pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
 914         pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
 915         pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
 916         pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
 917
 918         /* Set the value for System Management RAM Control Register */
 919         pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
 920
 921         /* Set the value for GMCH Control Register #1 */
 922         switch (CONFIG_VIDEO_MB) {
 923         case 1: /* 1M of memory */
 924                 video_memory = 0x1;
 925                 break;
 926         case 4: /* 4M of memory */
 927                 video_memory = 0x2;
 928                 break;
 929         case 8: /* 8M of memory */
 930                 video_memory = 0x3;
 931                 break;
 932         case 16: /* 16M of memory */
 933                 video_memory = 0x4;
 934                 break;
 935         case 32: /* 32M of memory */
 936                 video_memory = 0x5;
 937                 break;
 938         default: /* No memory */
 939                 pci_write_config16(NORTHBRIDGE, GMC, pci_read_config16(NORTHBRIDGE, GMC) | 1);
 940                 video_memory = 0x0;
 941         }
 942
 943         value = pci_read_config16(NORTHBRIDGE, GGC);
 944         value |= video_memory << 4;
 945         if (video_memory == 0) {
 946                 value &= ~(1 < 1);
 947         } else
 948                 value |= (1 < 1);
 949         pci_write_config16(NORTHBRIDGE, GGC, value);
 950
 951         /* AGPCMD: disable AGP, Data-Rate: 1x */
 952         pci_write_config32(NORTHBRIDGE, AGPCMD, 0x00000001);
 953
 954         pci_write_config8(NORTHBRIDGE, AMTT, 0x20);
 955         pci_write_config8(NORTHBRIDGE, LPTT, 0x10);
 956
 957         printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
 958 }
 959
 960 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 961 {
 962         uint8_t dimm_mask;
 963
 964         PRINTK_DEBUG("Reading SPD data...\n");
 965
 966         dimm_mask = spd_get_supported_dimms(ctrl);
 967
 968         if (dimm_mask == 0) {
 969                 print_debug("No usable memory for this controller\n");
 970         } else {
 971                 PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
 972
 973                 spd_set_row_attributes(ctrl, dimm_mask);
 974                 spd_set_dram_controller_mode(ctrl, dimm_mask);
 975                 spd_set_dram_timing(ctrl, dimm_mask);
 976                 spd_set_dram_size(ctrl, dimm_mask);
 977                 spd_set_dram_pwr_management(ctrl);
 978                 spd_set_dram_throttle_control(ctrl);
 979                 spd_set_undocumented_registers(ctrl);
 980         }
 981
 982         /* Setup Initial Northbridge Registers */
 983         northbridge_set_registers();
 984 }
 985