src/northbridge/intel/i855/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <assert.h>
  22 #include <spd.h>
  23 #include <sdram_mode.h>
  24 #include <stdlib.h>
  25 #include <delay.h>
  26 #include "i855.h"
  27
  28 /*-----------------------------------------------------------------------------
  29 Macros and definitions:
  30 -----------------------------------------------------------------------------*/
  31
  32 #define VALIDATE_DIMM_COMPATIBILITY
  33
  34 /* Debugging macros. */
  35 #if CONFIG_DEBUG_RAM_SETUP
  36 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  37 #define DUMPNORTH()             dump_pci_device(NORTHBRIDGE_MMC)
  38 #else
  39 #define PRINTK_DEBUG(x...)
  40 #define DUMPNORTH()
  41 #endif
  42
  43 #define delay() udelay(200)
  44
  45 #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)
  46
  47 /* DRC[10:8] - Refresh Mode Select (RMS).
  48  * 0x0 for Refresh Disabled (Self Refresh)
  49  * 0x1 for Refresh interval 15.6 us for 133MHz
  50  * 0x2 for Refresh interval 7.8 us for 133MHz
  51  * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode)
  52  */
  53 #define RAM_COMMAND_REFRESH             0x1
  54
  55 /* DRC[6:4] - SDRAM Mode Select (SMS). */
  56 #define RAM_COMMAND_SELF_REFRESH        0x0
  57 #define RAM_COMMAND_NOP                 0x1
  58 #define RAM_COMMAND_PRECHARGE           0x2
  59 #define RAM_COMMAND_MRS                 0x3
  60 #define RAM_COMMAND_EMRS                0x4
  61 #define RAM_COMMAND_CBR                 0x6
  62 #define RAM_COMMAND_NORMAL              0x7
  63
  64 /* DRC[29] - Initialization Complete (IC). */
  65 #define RAM_COMMAND_IC                  0x1
  66
  67 struct dimm_size {
  68         unsigned int side1;
  69         unsigned int side2;
  70 };
  71
  72 static const uint32_t refresh_frequency[] = {
  73         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  74          * (RMS) value (array index)
  75          * 0 == least frequent refresh (longest interval between refreshes)
  76          * [0] disabled  -> 0
  77          * [1] 15.6 usec -> 2
  78          * [2]  7.8 usec -> 3
  79          * [3] 64   usec -> 1
  80          * [4] reserved  -> 0
  81          * [5] reserved  -> 0
  82          * [6] reserved  -> 0
  83          * [7] 64 clocks -> 4
  84          */
  85         0, 2, 3, 1, 0, 0, 0, 4
  86 };
  87
  88 static const uint32_t refresh_rate_map[] = {
  89         /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode
  90          * Select values (array value)
  91          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  92          * The i855 supports only 15.6 us (1), 7.8 us (2) and
  93          * 64 clock (481 ns) (7) refresh.
  94          * [0] ==  15.625 us -> 15.6 us
  95          * [1] ==   3.9   us -> 481  ns
  96          * [2] ==   7.8   us ->  7.8 us
  97          * [3] ==  31.3   us -> 15.6 us
  98          * [4] ==  62.5   us -> 15.6 us
  99          * [5] == 125     us -> 15.6 us
 100          */
 101         1, 7, 2, 1, 1, 1
 102 };
 103
 104 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
 105
 106 /*-----------------------------------------------------------------------------
 107 SPD functions:
 108 -----------------------------------------------------------------------------*/
 109
 110 static void die_on_spd_error(int spd_return_value)
 111 {
 112         if (spd_return_value < 0)
 113                 PRINTK_DEBUG("Error reading SPD info: got %d\n", spd_return_value);
 114 /*
 115         if (spd_return_value < 0)
 116                 die("Error reading SPD info\n");
 117 */
 118 }
 119
 120 /**
 121  * Calculate the page size for each physical bank of the DIMM:
 122  *
 123  *   log2(page size) = (# columns) + log2(data width)
 124  *
 125  * NOTE: Page size is the total number of data bits in a row.
 126  *
 127  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 128  * @return log2(page size) for each side of the DIMM.
 129  */
 130 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
 131 {
 132         uint16_t module_data_width;
 133         int value;
 134         struct dimm_size pgsz;
 135
 136         pgsz.side1 = 0;
 137         pgsz.side2 = 0;
 138
 139         // Side 1
 140         value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 141         die_on_spd_error(value);
 142
 143         pgsz.side1 = value & 0xf;       // # columns in bank 1
 144
 145         /* Get the module data width and convert it to a power of two */
 146         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 147         die_on_spd_error(value);
 148
 149         module_data_width = (value & 0xff) << 8;
 150
 151         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 152         die_on_spd_error(value);
 153
 154         module_data_width |= (value & 0xff);
 155
 156         pgsz.side1 += log2(module_data_width);
 157
 158         /* side two */
 159         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 160         die_on_spd_error(value);
 161
 162 /*
 163         if (value > 2)
 164                 die("Bad SPD value\n");
 165 */
 166         if (value > 2)
 167                 PRINTK_DEBUG("Bad SPD value\n");
 168
 169         if (value == 2) {
 170                 pgsz.side2 = pgsz.side1;        // Assume symmetric banks until we know differently
 171                 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 172                 die_on_spd_error(value);
 173
 174                 if ((value & 0xf0) != 0) {
 175                         // Asymmetric banks
 176                         pgsz.side2 -= value & 0xf;      /* Subtract out columns on side 1 */
 177                         pgsz.side2 += (value >> 4) & 0xf;       /* Add in columns on side 2 */
 178                 }
 179         }
 180
 181         return pgsz;
 182 }
 183
 184 /**
 185  * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
 186  *
 187  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 188  * @return Width in bits of each DIMM side's DRAMs.
 189  */
 190 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 191 {
 192         int value;
 193         struct dimm_size width;
 194
 195         width.side1 = 0;
 196         width.side2 = 0;
 197
 198         value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 199         die_on_spd_error(value);
 200
 201         width.side1 = value & 0x7f;     // Mask off bank 2 flag
 202
 203         if (value & 0x80) {
 204                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 205         } else {
 206                 // If bank 2 exists, it's the same width as bank 1
 207                 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 208                 die_on_spd_error(value);
 209
 210 #ifdef ROMCC_IF_BUG_FIXED
 211                 if (value == 2)
 212                         width.side2 = width.side1;
 213 #else
 214                 switch (value) {
 215                 case 2:
 216                         width.side2 = width.side1;
 217                         break;
 218
 219                 default:
 220                         break;
 221                 }
 222 #endif
 223         }
 224
 225         return width;
 226 }
 227
 228 /**
 229  * Calculate the log base 2 size in bits of both DIMM sides.
 230  *
 231  * log2(# bits) = (# columns) + log2(data width) +
 232  *                (# rows) + log2(banks per SDRAM)
 233  *
 234  * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
 235  * as a multiple of 4MB. The way we do it now we can size both sides of an
 236  * asymmetric DIMM.
 237  *
 238  * @param dimm SMBus address of DIMM socket to interrogate.
 239  * @return log2(number of bits) for each side of the DIMM.
 240  */
 241 static struct dimm_size spd_get_dimm_size(unsigned dimm)
 242 {
 243         int value;
 244
 245         // Start with log2(page size)
 246         struct dimm_size sz = sdram_spd_get_page_size(dimm);
 247
 248         if (sz.side1 > 0) {
 249                 value = spd_read_byte(dimm, SPD_NUM_ROWS);
 250                 die_on_spd_error(value);
 251
 252                 sz.side1 += value & 0xf;
 253
 254                 if (sz.side2 > 0) {
 255                         // Double-sided DIMM
 256                         if (value & 0xF0)
 257                                 sz.side2 += value >> 4; // Asymmetric
 258                         else
 259                                 sz.side2 += value;      // Symmetric
 260                 }
 261
 262                 value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 263                 die_on_spd_error(value);
 264
 265                 value = log2(value);
 266                 sz.side1 += value;
 267                 if (sz.side2 > 0)
 268                         sz.side2 += value;
 269         }
 270
 271         return sz;
 272 }
 273
 274 /**
 275  * Scan for compatible DIMMs.
 276  *
 277  * @param ctrl PCI addresses of memory controller functions, and SMBus
 278  *             addresses of DIMM slots on the mainboard.
 279  * @return A bitmask indicating which sockets contain a compatible DIMM.
 280  */
 281 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 282 {
 283         int i;
 284         uint8_t dimm_mask = 0;
 285
 286         for (i = 0; i < DIMM_SOCKETS; i++) {
 287                 uint16_t dimm = ctrl->channel0[i];
 288
 289 #ifdef VALIDATE_DIMM_COMPATIBILITY
 290                 struct dimm_size page_size;
 291                 struct dimm_size sdram_width;
 292 #endif
 293                 int spd_value;
 294
 295                 if (dimm == 0)
 296                         continue;       // No such socket on this mainboard
 297
 298                 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
 299                         continue;
 300
 301 #ifdef VALIDATE_DIMM_COMPATIBILITY
 302                 if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) {
 303                         PRINTK_DEBUG("Skipping DIMM with unsupported voltage: %02x\n", spd_value);
 304                         continue;       // Unsupported voltage
 305                 }
 306
 307 /*
 308                 // E7501 does not support unregistered DIMMs
 309                 spd_value = spd_read_byte(dimm, SPD_MODULE_ATTRIBUTES);
 310                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 311                         PRINTK_DEBUG("Skipping unregistered DIMM: %02x\n", spd_value);
 312                         continue;
 313                 }
 314 */
 315
 316                 page_size = sdram_spd_get_page_size(dimm);
 317                 sdram_width = sdram_spd_get_width(dimm);
 318
 319                 // Validate DIMM page size
 320                 // The i855 only supports page sizes of 4, 8, 16 KB per channel
 321                 // NOTE:  4 KB =  32 Kb = 2^15
 322                 //       16 KB = 128 Kb = 2^17
 323
 324                 if ((page_size.side1 < 15) || (page_size.side1 > 17)) {
 325                         PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side1);
 326                         continue;
 327                 }
 328
 329                 // If DIMM is double-sided, verify side2 page size
 330                 if (page_size.side2 != 0) {
 331                         if ((page_size.side2 < 15) || (page_size.side2 > 17)) {
 332                                 PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side2);
 333                                 continue;
 334                         }
 335                 }
 336                 // Validate SDRAM width
 337                 // The i855 only supports x8 and x16 devices
 338                 if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) {
 339                         PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 340                         continue;
 341                 }
 342
 343                 // If DIMM is double-sided, verify side2 width
 344                 if (sdram_width.side2 != 0) {
 345                         if ((sdram_width.side2 != 8)
 346                             && (sdram_width.side2 != 16)) {
 347                                 PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 348                                 continue;
 349                         }
 350                 }
 351 #endif
 352                 // Made it through all the checks, this DIMM is usable
 353                 dimm_mask |= (1 << i);
 354         }
 355
 356         return dimm_mask;
 357 }
 358
 359 /*-----------------------------------------------------------------------------
 360 SDRAM configuration functions:
 361 -----------------------------------------------------------------------------*/
 362
 363 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 364 {
 365         int i;
 366         u32 reg32;
 367         uint8_t dimm_start_32M_multiple = 0;
 368         uint16_t i855_mode_bits = jedec_mode_bits;
 369
 370         /* Configure the RAM command. */
 371         reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 372         reg32 &= ~(7 << 4);
 373         reg32 |= (command << 4);
 374         PRINTK_DEBUG("  Sending RAM command 0x%08x\n", reg32);
 375         pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
 376
 377         // RAM_COMMAND_NORMAL is an exception.
 378         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 379
 380         if (command != RAM_COMMAND_NORMAL) {
 381
 382                 // Send the command to all DIMMs by accessing a memory location within each
 383                 // NOTE: for mode select commands, some of the location address bits
 384                 // are part of the command
 385
 386                 // Map JEDEC mode bits to i855
 387                 if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
 388                         /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
 389                         i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
 390                 }
 391
 392                 for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
 393                         uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
 394                         if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
 395
 396                                 uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
 397                                 PRINTK_DEBUG("  Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
 398                                 read32(dimm_start_address + i855_mode_bits);
 399
 400                                 // Set the start of the next DIMM
 401                                 dimm_start_32M_multiple = dimm_end_32M_multiple;
 402                         }
 403                 }
 404         }
 405 }
 406
 407 static void set_initialize_complete(const struct mem_controller *ctrl)
 408 {
 409         uint32_t drc_reg;
 410
 411         drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 412         drc_reg |= (1 << 29);
 413         pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
 414 }
 415
 416 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 417 {
 418         int i;
 419
 420         print_debug("Ram enable 1\n");
 421         delay();
 422         delay();
 423
 424         /* NOP command */
 425         PRINTK_DEBUG(" NOP\n");
 426         do_ram_command(RAM_COMMAND_NOP, 0);
 427         delay();
 428         delay();
 429         delay();
 430
 431         /* Pre-charge all banks (at least 200 us after NOP) */
 432         PRINTK_DEBUG(" Pre-charging all banks\n");
 433         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 434         delay();
 435         delay();
 436         delay();
 437
 438         print_debug("Ram enable 4\n");
 439         do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
 440         delay();
 441         delay();
 442         delay();
 443
 444         print_debug("Ram enable 5\n");
 445         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
 446
 447         print_debug("Ram enable 6\n");
 448         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 449         delay();
 450         delay();
 451         delay();
 452
 453         /* 8 CBR refreshes (Auto Refresh) */
 454         PRINTK_DEBUG(" 8 CBR refreshes\n");
 455         for(i = 0; i < 8; i++) {
 456                 do_ram_command(RAM_COMMAND_CBR, 0);
 457                 delay();
 458                 delay();
 459                 delay();
 460         }
 461
 462         print_debug("Ram enable 8\n");
 463         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
 464
 465         /* Set GME-M Mode Select bits back to NORMAL operation mode */
 466         PRINTK_DEBUG(" Normal operation mode\n");
 467         do_ram_command(RAM_COMMAND_NORMAL, 0);
 468         delay();
 469         delay();
 470         delay();
 471
 472         print_debug("Ram enable 9\n");
 473         set_initialize_complete(ctrl);
 474
 475         delay();
 476         delay();
 477         delay();
 478         delay();
 479         delay();
 480
 481         print_debug("After configuration:\n");
 482         /* dump_pci_devices(); */
 483
 484         /*
 485         print_debug("\n\n***** RAM TEST *****\n");
 486         ram_check(0, 0xa0000);
 487         ram_check(0x100000, 0x40000000);
 488         */
 489 }
 490
 491 /*-----------------------------------------------------------------------------
 492 DIMM-independant configuration functions:
 493 -----------------------------------------------------------------------------*/
 494
 495 /**
 496  * Set only what I need until it works, then make it figure things out on boot
 497  * assumes only one DIMM is populated.
 498  *
 499  * @param ctrl PCI addresses of memory controller functions, and SMBus
 500  *             addresses of DIMM slots on the mainboard.
 501  */
 502 static void sdram_set_registers(const struct mem_controller *ctrl)
 503 {
 504         /*
 505         print_debug("Before configuration:\n");
 506         dump_pci_devices();
 507         */
 508 }
 509
 510 static void spd_set_row_attributes(const struct mem_controller *ctrl, uint8_t dimm_mask)
 511 {
 512         int i;
 513         uint16_t row_attributes = 0;
 514
 515         for (i = 0; i < DIMM_SOCKETS; i++) {
 516                 uint16_t dimm = ctrl->channel0[i];
 517                 struct dimm_size page_size;
 518                 struct dimm_size sdram_width;
 519
 520                 if (!(dimm_mask & (1 << i))) {
 521                         row_attributes |= 0x77 << (i << 3);
 522                         continue;       // This DIMM not usable
 523                 }
 524
 525                 // Get the relevant parameters via SPD
 526                 page_size = sdram_spd_get_page_size(dimm);
 527                 sdram_width = sdram_spd_get_width(dimm);
 528
 529                 // Update the DRAM Row Attributes.
 530                 // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3
 531                 // NOTE:  2 KB =  16 Kb = 2^14
 532                 row_attributes |= (page_size.side1 - 14) << (i << 3);   // Side 1 of each DIMM is an EVEN row
 533
 534                 if (sdram_width.side2 > 0)
 535                         row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4);     // Side 2 is ODD
 536                 else
 537                         row_attributes |= 7 << ((i << 3) + 4);
 538                 /* go to the next DIMM */
 539         }
 540
 541         PRINTK_DEBUG("DRA: %04x\n", row_attributes);
 542
 543         /* Write the new row attributes register */
 544         pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes);
 545 }
 546
 547 static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint8_t dimm_mask)
 548 {
 549         int i;
 550
 551         // Initial settings
 552         u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 553         u32 system_refresh_mode = (controller_mode >> 7) & 7;
 554
 555         controller_mode |= (1 << 20);  // ECC
 556         controller_mode |= (1 << 15);  // RAS lockout
 557         controller_mode |= (1 << 12);  // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected?????
 558         controller_mode |= (2 << 10);  // FIXME: Undocumented, really needed?????
 559
 560         for (i = 0; i < DIMM_SOCKETS; i++) {
 561                 uint16_t dimm = ctrl->channel0[i];
 562                 uint32_t dimm_refresh_mode;
 563                 int value;
 564                 u8 tRCD, tRP;
 565
 566                 if (!(dimm_mask & (1 << i))) {
 567                         continue;       // This DIMM not usable
 568                 }
 569
 570                 // Disable ECC mode if any one of the DIMMs does not support ECC
 571                 value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE);
 572                 die_on_spd_error(value);
 573                 if (value != ERROR_SCHEME_ECC)
 574                         controller_mode &= ~(3 << 20);
 575
 576                 value = spd_read_byte(dimm, SPD_REFRESH);
 577                 die_on_spd_error(value);
 578                 value &= 0x7f;  // Mask off self-refresh bit
 579                 if (value > MAX_SPD_REFRESH_RATE) {
 580                         print_err("unsupported refresh rate\n");
 581                         continue;
 582                 }
 583                 // Get the appropriate i855 refresh mode for this DIMM
 584                 dimm_refresh_mode = refresh_rate_map[value];
 585                 if (dimm_refresh_mode > 7) {
 586                         print_err("unsupported refresh rate\n");
 587                         continue;
 588                 }
 589                 // If this DIMM requires more frequent refresh than others,
 590                 // update the system setting
 591                 if (refresh_frequency[dimm_refresh_mode] >
 592                     refresh_frequency[system_refresh_mode])
 593                         system_refresh_mode = dimm_refresh_mode;
 594
 595                 /* FIXME: is this correct? */
 596                 tRCD = spd_read_byte(dimm, SPD_tRCD);
 597                 tRP = spd_read_byte(dimm, SPD_tRP);
 598                 if (tRCD != tRP) {
 599                         PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);
 600                         controller_mode &= ~(1 << 15);
 601                 }
 602
 603                 /* go to the next DIMM */
 604         }
 605
 606         controller_mode &= ~(7 << 7);
 607         controller_mode |= (system_refresh_mode << 7);
 608         PRINTK_DEBUG("DRC: %08x\n", controller_mode);
 609
 610         pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode);
 611 }
 612
 613 static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
 614 {
 615         int i;
 616         u32 dram_timing;
 617
 618         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
 619         // NOTE: i82822 supports only 2.0 and 2.5
 620         uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
 621         uint8_t slowest_row_precharge = 0;
 622         uint8_t slowest_ras_cas_delay = 0;
 623         uint8_t slowest_active_to_precharge_delay = 0;
 624
 625         for (i = 0; i < DIMM_SOCKETS; i++) {
 626                 uint16_t dimm = ctrl->channel0[i];
 627                 int value;
 628                 uint32_t current_cas_latency;
 629                 uint32_t dimm_compatible_cas_latencies;
 630                 if (!(dimm_mask & (1 << i)))
 631                         continue;       // This DIMM not usable
 632
 633                 value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
 634                 PRINTK_DEBUG("SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value);
 635                 die_on_spd_error(value);
 636
 637                 dimm_compatible_cas_latencies = value & 0x7f;   // Start with all supported by DIMM
 638                 PRINTK_DEBUG("dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies);
 639
 640                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
 641                 PRINTK_DEBUG("current_cas_latency: %d\n", current_cas_latency);
 642
 643                 // Can we support the highest CAS# latency?
 644                 value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 645                 die_on_spd_error(value);
 646                 PRINTK_DEBUG("SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf);
 647
 648                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
 649                 if (value > 0x75) {
 650                         // Our bus is too fast for this CAS# latency
 651                         // Remove it from the bitmask of those supported by the DIMM that are compatible
 652                         dimm_compatible_cas_latencies &= ~current_cas_latency;
 653                         PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 654                 }
 655                 // Can we support the next-highest CAS# latency (max - 0.5)?
 656
 657                 current_cas_latency >>= 1;
 658                 if (current_cas_latency != 0) {
 659                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
 660                         die_on_spd_error(value);
 661                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf);
 662                         if (value > 0x75) {
 663                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 664                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 665                         }
 666                 }
 667                 // Can we support the next-highest CAS# latency (max - 1.0)?
 668                 current_cas_latency >>= 1;
 669                 if (current_cas_latency != 0) {
 670                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
 671                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf);
 672                         die_on_spd_error(value);
 673                         if (value > 0x75) {
 674                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 675                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 676                         }
 677                 }
 678                 // Restrict the system to CAS# latencies compatible with this DIMM
 679                 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
 680
 681                 value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME);
 682                 die_on_spd_error(value);
 683                 if (value > slowest_row_precharge)
 684                         slowest_row_precharge = value;
 685
 686                 value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY);
 687                 die_on_spd_error(value);
 688                 if (value > slowest_ras_cas_delay)
 689                         slowest_ras_cas_delay = value;
 690
 691                 value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 692                 die_on_spd_error(value);
 693                 if (value > slowest_active_to_precharge_delay)
 694                         slowest_active_to_precharge_delay = value;
 695
 696                 /* go to the next DIMM */
 697         }
 698         PRINTK_DEBUG("CAS latency: %d\n", system_compatible_cas_latencies);
 699
 700         dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT);
 701         dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK);
 702         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 703
 704         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
 705                 dram_timing |= DRT_CAS_2_0;
 706         } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
 707                 dram_timing |= DRT_CAS_2_5;
 708         } else
 709                 die("No CAS# latencies compatible with all DIMMs!!\n");
 710
 711         uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK;
 712
 713         /* tRP */
 714
 715         PRINTK_DEBUG("slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3);
 716         // i855 supports only 2, 3 or 4 clocks for tRP
 717         if (slowest_row_precharge > ((30 << 2)))
 718                 die("unsupported DIMM tRP");    //  > 30.0 ns: 5 or more clocks
 719         else if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
 720                 dram_timing |= DRT_TRP_4;       //  > 22.5 ns: 4 or more clocks
 721         else if (slowest_row_precharge > (15 << 2))
 722                 dram_timing |= DRT_TRP_3;       //  > 15.0 ns: 3 clocks
 723         else
 724                 dram_timing |= DRT_TRP_2;       // <= 15.0 ns: 2 clocks
 725
 726         /*  tRCD */
 727
 728         PRINTK_DEBUG("slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3);
 729         // i855 supports only 2, 3 or 4 clocks for tRCD
 730         if (slowest_ras_cas_delay > ((30 << 2)))
 731                 die("unsupported DIMM tRCD");   //  > 30.0 ns: 5 or more clocks
 732         else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
 733                 dram_timing |= DRT_RCD_4;       //  > 22.5 ns: 4 or more clocks
 734         else if (slowest_ras_cas_delay > (15 << 2))
 735                 dram_timing |= DRT_RCD_3;       //  > 15.0 ns: 3 clocks
 736         else
 737                 dram_timing |= DRT_RCD_2;       // <= 15.0 ns: 2 clocks
 738
 739         /* tRAS, min */
 740
 741         PRINTK_DEBUG("slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay);
 742         // i855 supports only 5, 6, 7 or 8 clocks for tRAS
 743         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns
 744         if (slowest_active_to_precharge_delay > 60)
 745                 die("unsupported DIMM tRAS");   // > 52 ns:      8 or more clocks
 746         else if (slowest_active_to_precharge_delay > 52)
 747                 dram_timing |= DRT_TRAS_MIN_8;  // 46-52 ns:     7 clocks
 748         else if (slowest_active_to_precharge_delay > 45)
 749                 dram_timing |= DRT_TRAS_MIN_7;  // 46-52 ns:     7 clocks
 750         else if (slowest_active_to_precharge_delay > 37)
 751                 dram_timing |= DRT_TRAS_MIN_6;  // 38-45 ns:     6 clocks
 752         else
 753                 dram_timing |= DRT_TRAS_MIN_5;  // < 38 ns:      5 clocks
 754
 755         /* FIXME: guess work starts here...
 756          *
 757          * Intel refers to DQ turn-arround values for back to calculate the values,
 758          * but i have no idea what this means
 759          */
 760
 761         /*
 762          * Back to Back Read-Write command spacing (DDR, different Rows/Bank)
 763          */
 764         /* Set to a 3 clock back to back read to write turn around.
 765          *  2 is a good delay if the CAS latency is 2.0 */
 766         dram_timing &= ~(3 << 28);
 767         if (current_cas_latency == DRT_CAS_2_0)
 768                 dram_timing |= (2 << 28);       // 2 clocks
 769         else
 770                 dram_timing |= (1 << 28);       // 3 clocks
 771
 772         /*
 773          * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank)
 774          */
 775         dram_timing &= ~(3 << 26);
 776         if (current_cas_latency == DRT_CAS_2_0)
 777                 dram_timing |= (2 << 26);       // 5 clocks
 778         else
 779                 dram_timing |= (1 << 26);       // 6 clocks
 780
 781         /*
 782          * Back To Back Read-Read commands spacing (DDR, different Rows):
 783          */
 784         dram_timing &= ~(1 << 25);
 785         dram_timing |= (1 << 25);       // 3 clocks
 786
 787         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 788         pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing);
 789 }
 790
 791 static void spd_set_dram_size(const struct mem_controller *ctrl, uint8_t dimm_mask)
 792 {
 793         int i;
 794         int total_dram = 0;
 795         uint32_t drb_reg = 0;
 796
 797         for (i = 0; i < DIMM_SOCKETS; i++) {
 798                 uint16_t dimm = ctrl->channel0[i];
 799                 struct dimm_size sz;
 800
 801                 if (!(dimm_mask & (1 << i))) {
 802                         /* fill values even for not present DIMMs */
 803                         drb_reg |= (total_dram << (i * 16));
 804                         drb_reg |= (total_dram << ((i * 16) + 8));
 805
 806                         continue;       // This DIMM not usable
 807                 }
 808                 sz = spd_get_dimm_size(dimm);
 809
 810                 total_dram += (1 << (sz.side1 - 28));
 811                 drb_reg |= (total_dram << (i * 16));
 812
 813                 total_dram += (1 << (sz.side2 - 28));
 814                 drb_reg |= (total_dram << ((i * 16) + 8));
 815         }
 816         PRINTK_DEBUG("DRB: %08x\n", drb_reg);
 817         pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg);
 818 }
 819
 820
 821 static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
 822 {
 823         uint32_t pwrmg_reg;
 824
 825         pwrmg_reg = 0x10f10430;
 826         pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg);
 827 }
 828
 829 static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
 830 {
 831         uint32_t dtc_reg = 0;
 832
 833         /* DDR SDRAM Throttle Mode (TMODE):
 834          *   0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-
 835          *          DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT
 836          */
 837         dtc_reg |= (3 << 28);
 838
 839         /* Read Counter Based Power Throttle Control (RCTC):
 840          *   0 = 85%
 841          */
 842         dtc_reg |= (0 << 24);
 843
 844         /* Write Counter Based Power Throttle Control (WCTC):
 845          *   0 = 85%
 846          */
 847         dtc_reg |= (0 << 20);
 848
 849         /* Read Thermal Based Power Throttle Control (RTTC):
 850          *   0xA = 20%
 851          */
 852         dtc_reg |= (0xA << 16);
 853
 854         /* Write Thermal Based Power Throttle Control (WTTC):
 855          *   0xA = 20%
 856          */
 857         dtc_reg |= (0xA << 12);
 858
 859         /* Counter Based Throttle Lock (CTLOCK): */
 860         dtc_reg |= (0 << 11);
 861
 862         /* Thermal Throttle Lock (TTLOCK): */
 863         dtc_reg |= (0 << 10);
 864
 865         /* Thermal Power Throttle Control fields Enable: */
 866         dtc_reg |= (1 << 9);
 867
 868         /* High Priority Stream Throttling Enable: */
 869         dtc_reg |= (0 << 8);
 870
 871         /* Global DDR SDRAM Sampling Window (GDSW): */
 872         dtc_reg |= 0xff;
 873         PRINTK_DEBUG("DTC: %08x\n", dtc_reg);
 874         pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg);
 875 }
 876
 877 static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value)
 878 {
 879 #if CONFIG_DEBUG_RAM_SETUP
 880         u32 value1 = pci_read_config32(ctrl->d0, reg);
 881 #endif
 882         pci_write_config32(ctrl->d0, reg, new_value);
 883 #if CONFIG_DEBUG_RAM_SETUP
 884         u32 value2 = pci_read_config32(ctrl->d0, reg);
 885         PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 886 #endif
 887 }
 888
 889 /* if ram still doesn't work do this function */
 890 static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
 891 {
 892         spd_update(ctrl, 0x74, 0x00000001);
 893         spd_update(ctrl, 0x78, 0x001fe974);
 894         spd_update(ctrl, 0x80, 0x00af0039);
 895         spd_update(ctrl, 0x84, 0x0000033c);
 896         spd_update(ctrl, 0x88, 0x00000010);
 897
 898         spd_update(ctrl, 0xc0, 0x00000003);
 899 }
 900
 901 static void northbridge_set_registers(void)
 902 {
 903         u16 value;
 904         int video_memory = 0;
 905
 906         printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
 907
 908         /* Set the value for Fixed DRAM Hole Control Register */
 909         pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
 910
 911         /* Set the value for Programable Attribute Map Registers
 912          * Ideally, this should be R/W for as many ranges as possible.
 913          */
 914         pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
 915         pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
 916         pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
 917         pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
 918         pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
 919         pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
 920         pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
 921
 922         /* Set the value for System Management RAM Control Register */
 923         pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
 924
 925         /* Set the value for GMCH Control Register #1 */
 926         switch (CONFIG_VIDEO_MB) {
 927         case 1: /* 1M of memory */
 928                 video_memory = 0x1;
 929                 break;
 930         case 4: /* 4M of memory */
 931                 video_memory = 0x2;
 932                 break;
 933         case 8: /* 8M of memory */
 934                 video_memory = 0x3;
 935                 break;
 936         case 16: /* 16M of memory */
 937                 video_memory = 0x4;
 938                 break;
 939         case 32: /* 32M of memory */
 940                 video_memory = 0x5;
 941                 break;
 942         default: /* No memory */
 943                 pci_write_config16(NORTHBRIDGE, GMC, pci_read_config16(NORTHBRIDGE, GMC) | 1);
 944                 video_memory = 0x0;
 945         }
 946
 947         value = pci_read_config16(NORTHBRIDGE, GGC);
 948         value |= video_memory << 4;
 949         if (video_memory == 0) {
 950                 value &= ~(1 < 1);
 951         } else
 952                 value |= (1 < 1);
 953         pci_write_config16(NORTHBRIDGE, GGC, value);
 954
 955         /* AGPCMD: disable AGP, Data-Rate: 1x */
 956         pci_write_config32(NORTHBRIDGE, AGPCMD, 0x00000001);
 957
 958         pci_write_config8(NORTHBRIDGE, AMTT, 0x20);
 959         pci_write_config8(NORTHBRIDGE, LPTT, 0x10);
 960
 961         printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
 962 }
 963
 964 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 965 {
 966         uint8_t dimm_mask;
 967
 968         PRINTK_DEBUG("Reading SPD data...\n");
 969
 970         dimm_mask = spd_get_supported_dimms(ctrl);
 971
 972         if (dimm_mask == 0) {
 973                 print_debug("No usable memory for this controller\n");
 974         } else {
 975                 PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
 976
 977                 spd_set_row_attributes(ctrl, dimm_mask);
 978                 spd_set_dram_controller_mode(ctrl, dimm_mask);
 979                 spd_set_dram_timing(ctrl, dimm_mask);
 980                 spd_set_dram_size(ctrl, dimm_mask);
 981                 spd_set_dram_pwr_management(ctrl);
 982                 spd_set_dram_throttle_control(ctrl);
 983                 spd_set_undocumented_registers(ctrl);
 984         }
 985
 986         /* Setup Initial Northbridge Registers */
 987         northbridge_set_registers();
 988 }
 989