2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Ronald G. Minnich
5 * Copyright (C) 2003-2004 Eric W. Biederman
6 * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
32 #include <cpu/x86/cache.h>
36 static void northbridge_init(device_t dev)
38 printk(BIOS_SPEW, "Northbridge init\n");
41 static struct device_operations northbridge_operations = {
42 .read_resources = pci_dev_read_resources,
43 .set_resources = pci_dev_set_resources,
44 .enable_resources = pci_dev_enable_resources,
45 .init = northbridge_init,
50 static const struct pci_driver northbridge_driver __pci_driver = {
51 .ops = &northbridge_operations,
52 .vendor = PCI_VENDOR_ID_INTEL,
56 static void ram_resource(device_t dev, unsigned long index,
57 unsigned long basek, unsigned long sizek)
59 struct resource *resource;
64 resource = new_resource(dev, index);
65 resource->base = ((resource_t)basek) << 10;
66 resource->size = ((resource_t)sizek) << 10;
67 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
68 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
71 static void tolm_test(void *gp, struct device *dev, struct resource *new)
73 struct resource **best_p = gp;
74 struct resource *best;
76 if (!best || (best->base > new->base)) {
82 static uint32_t find_pci_tolm(struct bus *bus)
87 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
89 if (min && tolm > min->base) {
95 #if CONFIG_WRITE_HIGH_TABLES==1
96 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
97 extern uint64_t high_tables_base, high_tables_size;
99 static void pci_domain_set_resources(device_t dev)
104 printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
105 printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
107 pci_tolm = find_pci_tolm(dev->link_list);
108 mc_dev = dev->link_list->children->sibling;
109 printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
110 printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
113 /* Figure out which areas are/should be occupied by RAM.
114 * This is all computed in kilobytes and converted to/from
115 * the memory controller right at the edges.
116 * Having different variables in different units is
117 * too confusing to get right. Kilobytes are good up to
118 * 4 Terabytes of RAM...
120 unsigned long tomk, tolmk;
123 /* Get the value of the highest DRB. This tells the end of
124 * the physical memory. The units are ticks of 32MB
127 tomk = (unsigned long)pci_read_config8(mc_dev, 0x43);
128 tomk = tomk * 32 * 1024;
129 /* add vga_mem detection */
130 tomk = tomk - 16 * 1024;
131 /* Compute the top of Low memory */
132 tolmk = pci_tolm >> 10;
134 /* The PCI hole does not overlap memory
138 /* Write the ram configuration registers,
139 * preserving the reserved bits.
142 /* Report the memory regions */
143 printk(BIOS_DEBUG, "tomk = %ld\n", tomk);
144 printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk);
147 /* avoid pam region */
148 ram_resource(dev, idx++, 0, 640);
149 /* ram_resource(dev, idx++, 1024, tolmk - 1024); */
150 ram_resource(dev, idx++, 768, tolmk - 768);
152 #if CONFIG_WRITE_HIGH_TABLES==1
153 /* Leave some space for ACPI, PIRQ and MP tables */
154 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
155 high_tables_size = HIGH_TABLES_SIZE * 1024;
158 assign_resources(dev->link_list);
161 static struct device_operations pci_domain_ops = {
162 .read_resources = pci_domain_read_resources,
163 .set_resources = pci_domain_set_resources,
164 .enable_resources = NULL,
166 .scan_bus = pci_domain_scan_bus,
169 static void cpu_bus_init(device_t dev)
171 initialize_cpus(dev->link_list);
174 static void cpu_bus_noop(device_t dev)
178 static struct device_operations cpu_bus_ops = {
179 .read_resources = cpu_bus_noop,
180 .set_resources = cpu_bus_noop,
181 .enable_resources = cpu_bus_noop,
182 .init = cpu_bus_init,
186 static void enable_dev(struct device *dev)
188 /* Set the operations if it is a special bus type */
189 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
190 dev->ops = &pci_domain_ops;
193 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
194 dev->ops = &cpu_bus_ops;
198 struct chip_operations northbridge_intel_i855_ops = {
199 CHIP_NAME("Intel 855 Northbridge")
200 .enable_dev = enable_dev,