2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
31 #include <boot/tables.h>
35 static void northbridge_init(device_t dev)
37 printk(BIOS_SPEW, "Northbridge init\n");
40 static struct device_operations northbridge_operations = {
41 .read_resources = pci_dev_read_resources,
42 .set_resources = pci_dev_set_resources,
43 .enable_resources = pci_dev_enable_resources,
44 .init = northbridge_init,
49 static const struct pci_driver northbridge_driver __pci_driver = {
50 .ops = &northbridge_operations,
51 .vendor = PCI_VENDOR_ID_INTEL,
56 uint64_t uma_memory_base=0, uma_memory_size=0;
58 int add_northbridge_resources(struct lb_memory *mem)
60 printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
61 lb_add_memory_range(mem, LB_MEM_RESERVED,
62 uma_memory_base, uma_memory_size);
67 #if CONFIG_WRITE_HIGH_TABLES==1
68 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
69 extern uint64_t high_tables_base, high_tables_size;
71 static void pci_domain_set_resources(device_t dev)
77 pci_tolm = find_pci_tolm(dev->link_list);
78 mc_dev = dev->link_list->children;
82 unsigned long tomk, tolmk;
85 if (CONFIG_VIDEO_MB == 512) {
86 igd_memory = (CONFIG_VIDEO_MB);
87 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
89 igd_memory = (CONFIG_VIDEO_MB * 1024);
90 printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
93 /* Get the value of the highest DRB. This tells the end of
94 * the physical memory. The units are ticks of 32MB
97 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
100 /* For reserving UMA memory in the memory map */
101 uma_memory_base = tomk * 1024ULL;
102 uma_memory_size = igd_memory * 1024ULL;
103 printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
105 /* Compute the top of low memory. */
106 tolmk = pci_tolm >> 10;
108 /* The PCI hole does does not overlap the memory. */
112 /* Report the memory regions. */
114 ram_resource(dev, idx++, 0, 640);
115 ram_resource(dev, idx++, 768, 256);
116 ram_resource(dev, idx++, 1024, tolmk - 1024);
118 assign_resources(dev->link_list);
120 #if CONFIG_WRITE_HIGH_TABLES==1
121 /* Leave some space for ACPI, PIRQ and MP tables */
122 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
123 high_tables_size = HIGH_TABLES_SIZE * 1024;
127 static struct device_operations pci_domain_ops = {
128 .read_resources = pci_domain_read_resources,
129 .set_resources = pci_domain_set_resources,
130 .enable_resources = NULL,
132 .scan_bus = pci_domain_scan_bus,
135 static void cpu_bus_init(device_t dev)
137 initialize_cpus(dev->link_list);
140 static void cpu_bus_noop(device_t dev)
144 static struct device_operations cpu_bus_ops = {
145 .read_resources = cpu_bus_noop,
146 .set_resources = cpu_bus_noop,
147 .enable_resources = cpu_bus_noop,
148 .init = cpu_bus_init,
152 static void enable_dev(struct device *dev)
156 /* Set the operations if it is a special bus type. */
157 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
158 dev->ops = &pci_domain_ops;
160 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
161 dev->ops = &cpu_bus_ops;
165 struct chip_operations northbridge_intel_i82830_ops = {
166 CHIP_NAME("Intel 82830 Northbridge")
167 .enable_dev = enable_dev,