2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
31 #include <boot/tables.h>
35 static void northbridge_init(device_t dev)
37 printk(BIOS_SPEW, "Northbridge init\n");
40 static struct device_operations northbridge_operations = {
41 .read_resources = pci_dev_read_resources,
42 .set_resources = pci_dev_set_resources,
43 .enable_resources = pci_dev_enable_resources,
44 .init = northbridge_init,
49 static const struct pci_driver northbridge_driver __pci_driver = {
50 .ops = &northbridge_operations,
51 .vendor = PCI_VENDOR_ID_INTEL,
56 uint64_t uma_memory_base=0, uma_memory_size=0;
58 int add_northbridge_resources(struct lb_memory *mem)
60 printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
61 lb_add_memory_range(mem, LB_MEM_RESERVED,
62 uma_memory_base, uma_memory_size);
67 #if CONFIG_WRITE_HIGH_TABLES==1
70 static void pci_domain_set_resources(device_t dev)
76 pci_tolm = find_pci_tolm(dev->link_list);
77 mc_dev = dev->link_list->children;
81 unsigned long tomk, tolmk;
84 if (CONFIG_VIDEO_MB == 512) {
85 igd_memory = (CONFIG_VIDEO_MB);
86 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
88 igd_memory = (CONFIG_VIDEO_MB * 1024);
89 printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
92 /* Get the value of the highest DRB. This tells the end of
93 * the physical memory. The units are ticks of 32MB
96 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
99 /* For reserving UMA memory in the memory map */
100 uma_memory_base = tomk * 1024ULL;
101 uma_memory_size = igd_memory * 1024ULL;
102 printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
104 /* Compute the top of low memory. */
105 tolmk = pci_tolm >> 10;
107 /* The PCI hole does does not overlap the memory. */
111 /* Report the memory regions. */
113 ram_resource(dev, idx++, 0, 640);
114 ram_resource(dev, idx++, 768, 256);
115 ram_resource(dev, idx++, 1024, tolmk - 1024);
117 assign_resources(dev->link_list);
119 #if CONFIG_WRITE_HIGH_TABLES==1
120 /* Leave some space for ACPI, PIRQ and MP tables */
121 high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
122 high_tables_size = HIGH_MEMORY_SIZE;
126 static struct device_operations pci_domain_ops = {
127 .read_resources = pci_domain_read_resources,
128 .set_resources = pci_domain_set_resources,
129 .enable_resources = NULL,
131 .scan_bus = pci_domain_scan_bus,
134 static void cpu_bus_init(device_t dev)
136 initialize_cpus(dev->link_list);
139 static void cpu_bus_noop(device_t dev)
143 static struct device_operations cpu_bus_ops = {
144 .read_resources = cpu_bus_noop,
145 .set_resources = cpu_bus_noop,
146 .enable_resources = cpu_bus_noop,
147 .init = cpu_bus_init,
151 static void enable_dev(struct device *dev)
155 /* Set the operations if it is a special bus type. */
156 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
157 dev->ops = &pci_domain_ops;
159 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
160 dev->ops = &cpu_bus_ops;
164 struct chip_operations northbridge_intel_i82830_ops = {
165 CHIP_NAME("Intel 82830 Northbridge")
166 .enable_dev = enable_dev,