2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
31 #include <boot/tables.h>
32 #include <arch/coreboot_tables.h>
36 static void northbridge_init(device_t dev)
38 printk_spew("Northbridge init\n");
41 static struct device_operations northbridge_operations = {
42 .read_resources = pci_dev_read_resources,
43 .set_resources = pci_dev_set_resources,
44 .enable_resources = pci_dev_enable_resources,
45 .init = northbridge_init,
50 static const struct pci_driver northbridge_driver __pci_driver = {
51 .ops = &northbridge_operations,
52 .vendor = PCI_VENDOR_ID_INTEL,
56 static void ram_resource(device_t dev, unsigned long index,
57 unsigned long basek, unsigned long sizek)
59 struct resource *resource;
63 resource = new_resource(dev, index);
64 resource->base = ((resource_t) basek) << 10;
65 resource->size = ((resource_t) sizek) << 10;
66 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
67 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
70 static void tolm_test(void *gp, struct device *dev, struct resource *new)
72 struct resource **best_p = gp;
73 struct resource *best;
75 if (!best || (best->base > new->base))
80 static uint32_t find_pci_tolm(struct bus *bus)
85 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
88 if (min && tolm > min->base)
94 uint64_t uma_memory_base=0, uma_memory_size=0;
96 int add_northbridge_resources(struct lb_memory *mem)
98 printk_debug("Adding IGD UMA memory area\n");
99 lb_add_memory_range(mem, LB_MEM_RESERVED,
100 uma_memory_base, uma_memory_size);
105 #if CONFIG_WRITE_HIGH_TABLES==1
106 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
107 extern uint64_t high_tables_base, high_tables_size;
109 static void pci_domain_set_resources(device_t dev)
115 pci_tolm = find_pci_tolm(&dev->link[0]);
116 mc_dev = dev->link[0].children;
118 unsigned long tomk, tolmk;
121 if (CONFIG_VIDEO_MB == 512) {
122 igd_memory = (CONFIG_VIDEO_MB);
123 printk_debug("%dKB IGD UMA\n", igd_memory >> 10);
125 igd_memory = (CONFIG_VIDEO_MB * 1024);
126 printk_debug("%dMB IGD UMA\n", igd_memory >> 10);
129 /* Get the value of the highest DRB. This tells the end of
130 * the physical memory. The units are ticks of 32MB
133 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
136 /* For reserving UMA memory in the memory map */
137 uma_memory_base = tomk * 1024ULL;
138 uma_memory_size = igd_memory * 1024ULL;
139 printk_debug("Available memory: %ldKB\n", tomk);
141 /* Compute the top of low memory. */
142 tolmk = pci_tolm >> 10;
144 /* The PCI hole does does not overlap the memory. */
148 /* Report the memory regions. */
150 ram_resource(dev, idx++, 0, 640);
151 ram_resource(dev, idx++, 1024, tolmk - 1024);
153 #if CONFIG_WRITE_HIGH_TABLES==1
154 /* Leave some space for ACPI, PIRQ and MP tables */
155 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
156 high_tables_size = HIGH_TABLES_SIZE * 1024;
159 assign_resources(&dev->link[0]);
162 static struct device_operations pci_domain_ops = {
163 .read_resources = pci_domain_read_resources,
164 .set_resources = pci_domain_set_resources,
165 .enable_resources = enable_childrens_resources,
167 .scan_bus = pci_domain_scan_bus,
170 static void cpu_bus_init(device_t dev)
172 initialize_cpus(&dev->link[0]);
175 static void cpu_bus_noop(device_t dev)
179 static struct device_operations cpu_bus_ops = {
180 .read_resources = cpu_bus_noop,
181 .set_resources = cpu_bus_noop,
182 .enable_resources = cpu_bus_noop,
183 .init = cpu_bus_init,
187 static void enable_dev(struct device *dev)
191 /* Set the operations if it is a special bus type. */
192 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
193 dev->ops = &pci_domain_ops;
195 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
196 dev->ops = &cpu_bus_ops;
200 struct chip_operations northbridge_intel_i82830_ops = {
201 CHIP_NAME("Intel 82830 Northbridge")
202 .enable_dev = enable_dev,