2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
34 static void northbridge_init(device_t dev)
36 printk_spew("Northbridge init\n");
39 static struct device_operations northbridge_operations = {
40 .read_resources = pci_dev_read_resources,
41 .set_resources = pci_dev_set_resources,
42 .enable_resources = pci_dev_enable_resources,
43 .init = northbridge_init,
48 static struct pci_driver northbridge_driver __pci_driver = {
49 .ops = &northbridge_operations,
50 .vendor = PCI_VENDOR_ID_INTEL,
54 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
56 static void pci_domain_read_resources(device_t dev)
58 struct resource *resource;
60 /* Initialize the system wide I/O space constraints. */
61 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
62 resource->limit = 0xffffUL;
64 IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
66 /* Initialize the system wide memory resources constraints. */
67 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
68 resource->limit = 0xffffffffULL;
70 IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
73 static void ram_resource(device_t dev, unsigned long index,
74 unsigned long basek, unsigned long sizek)
76 struct resource *resource;
80 resource = new_resource(dev, index);
81 resource->base = ((resource_t) basek) << 10;
82 resource->size = ((resource_t) sizek) << 10;
83 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
84 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
87 static void tolm_test(void *gp, struct device *dev, struct resource *new)
89 struct resource **best_p = gp;
90 struct resource *best;
92 if (!best || (best->base > new->base))
97 static uint32_t find_pci_tolm(struct bus *bus)
102 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
105 if (min && tolm > min->base)
110 #if HAVE_HIGH_TABLES==1
111 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
112 extern uint64_t high_tables_base, high_tables_size;
114 static void pci_domain_set_resources(device_t dev)
120 pci_tolm = find_pci_tolm(&dev->link[0]);
121 mc_dev = dev->link[0].children;
123 unsigned long tomk, tolmk;
126 if (CONFIG_VIDEO_MB == 512) {
127 igd_memory = (CONFIG_VIDEO_MB);
129 igd_memory = (CONFIG_VIDEO_MB * 1024);
132 /* Get the value of the highest DRB. This tells the end of
133 * the physical memory. The units are ticks of 32MB
136 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
138 printk_debug("Setting RAM size to %d\n", tomk);
140 /* Compute the top of low memory. */
141 tolmk = pci_tolm >> 10;
143 /* The PCI hole does does not overlap the memory. */
147 /* Report the memory regions. */
149 ram_resource(dev, idx++, 0, 640);
150 ram_resource(dev, idx++, 1024, tolmk - 1024);
152 #if HAVE_HIGH_TABLES==1
153 /* Leave some space for ACPI, PIRQ and MP tables */
154 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
155 high_tables_size = HIGH_TABLES_SIZE * 1024;
158 assign_resources(&dev->link[0]);
161 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
163 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
167 static struct device_operations pci_domain_ops = {
168 .read_resources = pci_domain_read_resources,
169 .set_resources = pci_domain_set_resources,
170 .enable_resources = enable_childrens_resources,
172 .scan_bus = pci_domain_scan_bus,
175 static void cpu_bus_init(device_t dev)
177 initialize_cpus(&dev->link[0]);
180 static void cpu_bus_noop(device_t dev)
184 static struct device_operations cpu_bus_ops = {
185 .read_resources = cpu_bus_noop,
186 .set_resources = cpu_bus_noop,
187 .enable_resources = cpu_bus_noop,
188 .init = cpu_bus_init,
192 static void enable_dev(struct device *dev)
196 /* Set the operations if it is a special bus type. */
197 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
198 dev->ops = &pci_domain_ops;
200 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
201 dev->ops = &cpu_bus_ops;
205 struct chip_operations northbridge_intel_i82830_ops = {
206 CHIP_NAME("Intel 82830 Northbridge")
207 .enable_dev = enable_dev,