2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
33 static void northbridge_init(device_t dev)
35 printk_spew("Northbridge init\n");
38 static struct device_operations northbridge_operations = {
39 .read_resources = pci_dev_read_resources,
40 .set_resources = pci_dev_set_resources,
41 .enable_resources = pci_dev_enable_resources,
42 .init = northbridge_init,
47 static struct pci_driver northbridge_driver __pci_driver = {
48 .ops = &northbridge_operations,
49 .vendor = PCI_VENDOR_ID_INTEL,
53 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
55 static void pci_domain_read_resources(device_t dev)
57 struct resource *resource;
59 /* Initialize the system wide I/O space constraints. */
60 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
61 resource->limit = 0xffffUL;
63 IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
65 /* Initialize the system wide memory resources constraints. */
66 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
67 resource->limit = 0xffffffffULL;
69 IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
72 static void ram_resource(device_t dev, unsigned long index,
73 unsigned long basek, unsigned long sizek)
75 struct resource *resource;
79 resource = new_resource(dev, index);
80 resource->base = ((resource_t) basek) << 10;
81 resource->size = ((resource_t) sizek) << 10;
82 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
83 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
86 static void tolm_test(void *gp, struct device *dev, struct resource *new)
88 struct resource **best_p = gp;
89 struct resource *best;
91 if (!best || (best->base > new->base))
96 static uint32_t find_pci_tolm(struct bus *bus)
101 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
104 if (min && tolm > min->base)
109 static void pci_domain_set_resources(device_t dev)
115 pci_tolm = find_pci_tolm(&dev->link[0]);
116 mc_dev = dev->link[0].children;
118 unsigned long tomk, tolmk;
121 if (CONFIG_VIDEO_MB == 512) {
122 igd_memory = (CONFIG_VIDEO_MB);
124 igd_memory = (CONFIG_VIDEO_MB * 1024);
127 /* Get the value of the highest DRB. This tells the end of
128 * the physical memory. The units are ticks of 32MB
131 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
133 printk_debug("Setting RAM size to %d\n", tomk);
135 /* Compute the top of low memory. */
136 tolmk = pci_tolm >> 10;
138 /* The PCI hole does does not overlap the memory. */
142 /* Report the memory regions. */
144 ram_resource(dev, idx++, 0, 640);
145 ram_resource(dev, idx++, 1024, tolmk - 1024);
147 assign_resources(&dev->link[0]);
150 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
152 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
156 static struct device_operations pci_domain_ops = {
157 .read_resources = pci_domain_read_resources,
158 .set_resources = pci_domain_set_resources,
159 .enable_resources = enable_childrens_resources,
161 .scan_bus = pci_domain_scan_bus,
164 static void cpu_bus_init(device_t dev)
166 initialize_cpus(&dev->link[0]);
169 static void cpu_bus_noop(device_t dev)
173 static struct device_operations cpu_bus_ops = {
174 .read_resources = cpu_bus_noop,
175 .set_resources = cpu_bus_noop,
176 .enable_resources = cpu_bus_noop,
177 .init = cpu_bus_init,
181 static void enable_dev(struct device *dev)
185 /* Set the operations if it is a special bus type. */
186 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
187 dev->ops = &pci_domain_ops;
189 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
190 dev->ops = &cpu_bus_ops;
194 struct chip_operations northbridge_intel_i82830_ops = {
195 CHIP_NAME("Intel 82830 Northbridge")
196 .enable_dev = enable_dev,