2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
5 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
33 #include <boot/tables.h>
34 #include "northbridge.h"
37 static void northbridge_init(device_t dev)
39 printk(BIOS_SPEW, "Northbridge init\n");
42 static struct device_operations northbridge_operations = {
43 .read_resources = pci_dev_read_resources,
44 .set_resources = pci_dev_set_resources,
45 .enable_resources = pci_dev_enable_resources,
46 .init = northbridge_init,
51 /* Intel 82810/82810-DC100 */
52 static const struct pci_driver i810_northbridge_driver __pci_driver = {
53 .ops = &northbridge_operations,
54 .vendor = PCI_VENDOR_ID_INTEL,
59 static const struct pci_driver i810e_northbridge_driver __pci_driver = {
60 .ops = &northbridge_operations,
61 .vendor = PCI_VENDOR_ID_INTEL,
65 static void ram_resource(device_t dev, unsigned long index,
66 unsigned long basek, unsigned long sizek)
68 struct resource *resource;
73 resource = new_resource(dev, index);
74 resource->base = ((resource_t) basek) << 10;
75 resource->size = ((resource_t) sizek) << 10;
76 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
77 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
80 static void tolm_test(void *gp, struct device *dev, struct resource *new)
82 struct resource **best_p = gp;
83 struct resource *best;
85 if (!best || (best->base > new->base)) {
91 static uint32_t find_pci_tolm(struct bus *bus)
96 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
99 if (min && tolm > min->base) {
106 uint64_t uma_memory_base=0, uma_memory_size=0;
108 int add_northbridge_resources(struct lb_memory *mem)
110 printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
111 lb_add_memory_range(mem, LB_MEM_RESERVED,
112 uma_memory_base, uma_memory_size);
117 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
118 * Note that 2 is a value which the DRP should never be programmed to.
119 * Some size values appear twice, due to single-sided vs dual-sided banks.
121 static int translate_i82810_to_mb[] = {
122 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
123 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
126 #if CONFIG_WRITE_HIGH_TABLES==1
127 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
128 extern uint64_t high_tables_base, high_tables_size;
131 static void pci_domain_set_resources(device_t dev)
137 pci_tolm = find_pci_tolm(dev->link_list);
138 mc_dev = dev->link_list->children;
142 unsigned long tomk, tolmk;
146 reg8 = pci_read_config8(mc_dev, SMRAM);
152 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
156 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
160 printk(BIOS_DEBUG, "No IGD UMA Memory\n");
164 /* Get the value for DIMM 0 and translate it to MB. */
165 drp_value = pci_read_config8(mc_dev, DRP);
166 tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0x0f]);
167 /* Get the value for DIMM 1 and translate it to MB. */
168 drp_value = drp_value >> 4;
169 tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
170 /* Convert tomk from MB to KB. */
174 /* For reserving UMA memory in the memory map */
175 uma_memory_base = tomk * 1024ULL;
176 uma_memory_size = igd_memory * 1024ULL;
177 printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
179 /* Compute the top of low memory. */
180 tolmk = pci_tolm >> 10;
182 /* The PCI hole does does not overlap the memory. */
186 /* Report the memory regions. */
188 ram_resource(dev, idx++, 0, 640);
189 ram_resource(dev, idx++, 768, tolmk - 768);
191 #if CONFIG_WRITE_HIGH_TABLES==1
192 /* Leave some space for ACPI, PIRQ and MP tables */
193 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
194 high_tables_size = HIGH_TABLES_SIZE * 1024;
196 assign_resources(dev->link_list);
199 static struct device_operations pci_domain_ops = {
200 .read_resources = pci_domain_read_resources,
201 .set_resources = pci_domain_set_resources,
202 .enable_resources = NULL,
204 .scan_bus = pci_domain_scan_bus,
207 static void cpu_bus_init(device_t dev)
209 initialize_cpus(dev->link_list);
212 static void cpu_bus_noop(device_t dev)
216 static struct device_operations cpu_bus_ops = {
217 .read_resources = cpu_bus_noop,
218 .set_resources = cpu_bus_noop,
219 .enable_resources = cpu_bus_noop,
220 .init = cpu_bus_init,
224 static void enable_dev(struct device *dev)
226 /* Set the operations if it is a special bus type */
227 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
228 dev->ops = &pci_domain_ops;
230 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
231 dev->ops = &cpu_bus_ops;
235 struct chip_operations northbridge_intel_i82810_ops = {
236 CHIP_NAME("Intel 82810 Northbridge")
237 .enable_dev = enable_dev,