2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
5 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
33 #include <boot/tables.h>
34 #include "northbridge.h"
37 static void northbridge_init(device_t dev)
39 printk(BIOS_SPEW, "Northbridge init\n");
42 static struct device_operations northbridge_operations = {
43 .read_resources = pci_dev_read_resources,
44 .set_resources = pci_dev_set_resources,
45 .enable_resources = pci_dev_enable_resources,
46 .init = northbridge_init,
51 /* Intel 82810/82810-DC100 */
52 static const struct pci_driver i810_northbridge_driver __pci_driver = {
53 .ops = &northbridge_operations,
54 .vendor = PCI_VENDOR_ID_INTEL,
59 static const struct pci_driver i810e_northbridge_driver __pci_driver = {
60 .ops = &northbridge_operations,
61 .vendor = PCI_VENDOR_ID_INTEL,
66 uint64_t uma_memory_base=0, uma_memory_size=0;
68 int add_northbridge_resources(struct lb_memory *mem)
70 printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
71 lb_add_memory_range(mem, LB_MEM_RESERVED,
72 uma_memory_base, uma_memory_size);
77 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
78 * Note that 2 is a value which the DRP should never be programmed to.
79 * Some size values appear twice, due to single-sided vs dual-sided banks.
81 static int translate_i82810_to_mb[] = {
82 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
83 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
86 #if CONFIG_WRITE_HIGH_TABLES==1
87 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
88 extern uint64_t high_tables_base, high_tables_size;
91 static void pci_domain_set_resources(device_t dev)
97 pci_tolm = find_pci_tolm(dev->link_list);
98 mc_dev = dev->link_list->children;
102 unsigned long tomk, tolmk;
106 reg8 = pci_read_config8(mc_dev, SMRAM);
112 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
116 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
120 printk(BIOS_DEBUG, "No IGD UMA Memory\n");
124 /* Get the value for DIMM 0 and translate it to MB. */
125 drp_value = pci_read_config8(mc_dev, DRP);
126 tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0x0f]);
127 /* Get the value for DIMM 1 and translate it to MB. */
128 drp_value = drp_value >> 4;
129 tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
130 /* Convert tomk from MB to KB. */
134 /* For reserving UMA memory in the memory map */
135 uma_memory_base = tomk * 1024ULL;
136 uma_memory_size = igd_memory * 1024ULL;
137 printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
139 /* Compute the top of low memory. */
140 tolmk = pci_tolm >> 10;
142 /* The PCI hole does does not overlap the memory. */
146 /* Report the memory regions. */
148 ram_resource(dev, idx++, 0, 640);
149 ram_resource(dev, idx++, 768, tolmk - 768);
151 #if CONFIG_WRITE_HIGH_TABLES==1
152 /* Leave some space for ACPI, PIRQ and MP tables */
153 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
154 high_tables_size = HIGH_TABLES_SIZE * 1024;
156 assign_resources(dev->link_list);
159 static struct device_operations pci_domain_ops = {
160 .read_resources = pci_domain_read_resources,
161 .set_resources = pci_domain_set_resources,
162 .enable_resources = NULL,
164 .scan_bus = pci_domain_scan_bus,
167 static void cpu_bus_init(device_t dev)
169 initialize_cpus(dev->link_list);
172 static void cpu_bus_noop(device_t dev)
176 static struct device_operations cpu_bus_ops = {
177 .read_resources = cpu_bus_noop,
178 .set_resources = cpu_bus_noop,
179 .enable_resources = cpu_bus_noop,
180 .init = cpu_bus_init,
184 static void enable_dev(struct device *dev)
186 /* Set the operations if it is a special bus type */
187 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
188 dev->ops = &pci_domain_ops;
190 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
191 dev->ops = &cpu_bus_ops;
195 struct chip_operations northbridge_intel_i82810_ops = {
196 CHIP_NAME("Intel 82810 Northbridge")
197 .enable_dev = enable_dev,