src/northbridge/intel/i5000/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 #include "raminit.h"
  23 #include <arch/io.h>
  24 #include <arch/romcc_io.h>
  25 #include <device/pci_def.h>
  26 #include <device/pnp_def.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <console/console.h>
  29 #include <spd.h>
  30 #include <types.h>
  31 #include <southbridge/intel/i63xx/early_smbus.c>
  32 #include <string.h>
  33 #include <cbmem.h>
  34 #include <stdlib.h>
  35 #include <lib.h>
  36 #include <delay.h>
  37
  38 static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
  39                                   int (*cb)(struct i5000_fbd_channel *))
  40 {
  41         struct i5000_fbd_channel *c;
  42         int ret;
  43
  44         for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
  45                 if (c->used && (ret = cb(c)))
  46                         return ret;
  47         return 0;
  48 }
  49
  50 static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
  51                                  int (*cb)(struct i5000_fbd_branch *))
  52 {
  53         struct i5000_fbd_branch *b;
  54         int ret;
  55
  56         for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
  57                 if (b->used && (ret = cb(b)))
  58                         return ret;
  59         return 0;
  60 }
  61
  62 static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
  63                                int (*cb)(struct i5000_fbdimm *))
  64 {
  65         struct i5000_fbdimm *d;
  66         int ret, i;
  67
  68         for(i = 0; i < I5000_MAX_DIMMS; i++) {
  69                 d = setup->dimms[i];
  70                 if ((ret = cb(d))) {
  71                         return ret;
  72                 }
  73         }
  74         return 0;
  75 }
  76
  77 static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
  78                                        int (*cb)(struct i5000_fbdimm *))
  79 {
  80         struct i5000_fbdimm *d;
  81         int ret, i;
  82
  83         for(i = 0; i < I5000_MAX_DIMMS; i++) {
  84                 d = setup->dimms[i];
  85                 if (d->present && (ret = cb(d)))
  86                         return ret;
  87         }
  88         return 0;
  89 }
  90
  91 static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
  92 {
  93         u16 status;
  94         device_t dev = d->branch->branchdev;
  95
  96         int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
  97         int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
  98
  99         while(count-- > 0) {
 100                 pci_write_config32(dev, cmdreg, 0xa8000000 |    \
 101                                    (d->num & 0x03) << 24 | addr++ << 16);
 102
 103                 int timeout = 1000;
 104                 while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--)
 105                         udelay(10);
 106
 107                 if (status & I5000_SPD_SBE || !timeout)
 108                         return -1;
 109
 110                 if (status & I5000_SPD_RDO) {
 111                         *out = status & 0xff;
 112                         out++;
 113                 }
 114         }
 115         return 0;
 116 }
 117
 118 static void i5000_clear_fbd_errors(void)
 119 {
 120         device_t dev16_1, dev16_2;
 121
 122         dev16_1 = PCI_ADDR(0, 16, 1, 0);
 123         dev16_2 = PCI_ADDR(0, 16, 2, 0);
 124
 125         pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
 126                                 pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
 127
 128         pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
 129                                 pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
 130
 131         pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
 132                                 pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
 133
 134         pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
 135                                 pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
 136
 137         pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
 138                                 pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
 139
 140         pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
 141                                 pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
 142
 143         pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
 144                                 pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
 145 }
 146
 147 static int i5000_branch_reset(struct i5000_fbd_branch *b)
 148 {
 149         device_t dev = b->branchdev;
 150
 151         pci_write_config8(dev, I5000_FBDRST, 0x00);
 152
 153         udelay(5000);
 154
 155         pci_write_config8(dev, I5000_FBDRST, 0x05);
 156         udelay(1);
 157         pci_write_config8(dev, I5000_FBDRST, 0x04);
 158         udelay(2);
 159         pci_write_config8(dev, I5000_FBDRST, 0x05);
 160         pci_write_config8(dev, I5000_FBDRST, 0x07);
 161         return 0;
 162 }
 163
 164 static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
 165 {
 166         int div;
 167
 168         switch (d->setup->ddr_speed) {
 169         case DDR_533MHZ:
 170                 div = 375;
 171                 break;
 172
 173         default:
 174                 printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
 175                        d->setup->ddr_speed);
 176
 177         case DDR_667MHZ:
 178                 div = 300;
 179                 break;
 180         }
 181
 182         return (del * 100) / div;
 183 }
 184
 185 static int mtb2clks(struct i5000_fbdimm *d, int del)
 186 {
 187         int val, div;
 188
 189         switch (d->setup->ddr_speed) {
 190         case DDR_533MHZ:
 191                 div = 375;
 192                 break;
 193         default:
 194                 printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
 195                        d->setup->ddr_speed);
 196
 197         case DDR_667MHZ:
 198                 div = 300;
 199                 break;
 200         }
 201
 202         val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div);
 203         if ((val % 10) > 0)
 204                 val += 10;
 205         return val / 10;
 206 }
 207
 208 static int i5000_read_spd_data(struct i5000_fbdimm *d)
 209 {
 210         struct i5000_fbd_setup *s = d->setup;
 211         u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
 212         u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
 213         u8 cmd2data_addr;
 214         int t_ck_min, dimmsize;
 215
 216         if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
 217                 printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
 218                        d->branch->num, d->channel->num, d->num);
 219                 return 0; // No FBDIMM present
 220         }
 221
 222         if (val != 0x09)
 223                 return -1; // SDRAM type not FBDIMM
 224
 225         if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
 226                 return -1;
 227
 228         switch(s->ddr_speed) {
 229         case DDR_533MHZ:
 230                 cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
 231                 break;
 232
 233         case DDR_667MHZ:
 234                 cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
 235                 break;
 236
 237         default:
 238                 printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
 239                 return -1;
 240         }
 241
 242         if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
 243             spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
 244             spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
 245             spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
 246             spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
 247             spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
 248             spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
 249             spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
 250             spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
 251             spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
 252             spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
 253             spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
 254             spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
 255             spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
 256             spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
 257             spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
 258             spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
 259             spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
 260             spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
 261             spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
 262             spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
 263             spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
 264             spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
 265             spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
 266                 printk(BIOS_ERR, "failed to read data from SPD\n");
 267                 return 0;
 268         }
 269
 270
 271         t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
 272         if (t_ck_min <= 300)
 273                 d->speed = DDR_667MHZ;
 274         else if (t_ck_min <= 375)
 275                 d->speed = DDR_533MHZ;
 276         else {
 277                 printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
 278                 return -1;
 279         }
 280
 281         d->sdram_width = org & 0x07;
 282         if (d->sdram_width > 1) {
 283                 printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
 284                 return -1;
 285         }
 286
 287         if (s->ddr_speed == DDR_667MHZ && d->speed == DDR_533MHZ)
 288                 s->ddr_speed = DDR_533MHZ;
 289
 290         d->banks = 4 << (addr & 0x03);
 291         d->columns = 9 + ((addr >> 2) & 0x03);
 292         d->rows = 12 + ((addr >> 5) & 0x03);
 293         d->ranks = (org >> 3) & 0x03;
 294         d->min_cas_latency = cas & 0x0f;
 295
 296         s->bl &= bl;
 297
 298         if (!s->bl) {
 299                 printk(BIOS_ERR, "no compatible burst length found\n");
 300                 return -1;
 301         }
 302
 303         s->t_rc = MAX(s->t_rc, mtb2clks(d,
 304                       t_rc | ((t_ras_rc_h & 0xf0) << 4)));
 305         s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
 306         s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
 307         s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
 308         s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
 309         s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
 310         s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
 311         s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
 312         s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
 313         s->t_ras = MAX(s->t_ras, mtb2clks(d,
 314                                           t_ras | ((t_ras_rc_h & 0x0f) << 8)));
 315         s->t_r2r = MAX(s->t_r2r, bb & 3);
 316         s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
 317         s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3);
 318
 319         d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20;
 320         dimmsize = d->ranksize * d->ranks;
 321         d->branch->totalmem += dimmsize;
 322         s->totalmem += dimmsize;
 323
 324         d->channel->columns = d->columns;
 325         d->channel->rows = d->rows;
 326         d->channel->ranks = d->ranks;
 327         d->channel->banks = d->banks;
 328         d->channel->width = d->sdram_width;
 329
 330         printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, "
 331                "%d columns, %d rows, %d ranks\n",
 332                d->branch->num, d->channel->num, d->num, dimmsize,
 333                d->banks, d->columns, d->rows, d->ranks);
 334
 335         d->present = 1;
 336         d->branch->used |= 1;
 337         d->channel->used |= 1;
 338         d->channel->highest_amb = d->num;
 339         return 0;
 340 }
 341
 342 static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
 343 {
 344         u16 status;
 345         device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
 346         int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
 347         int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
 348         int timeout = 1000;
 349
 350         pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
 351                            (byte1 << 16) | (byte2 << 8) | 1);
 352
 353         while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
 354                 udelay(10);
 355
 356         if (status & I5000_SPD_WOD && timeout)
 357                 return 0;
 358
 359         printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
 360                d->branch->num, d->channel->num, d->num, byte1, byte2, status);
 361         for(;;);
 362         return -1;
 363 }
 364
 365 static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
 366 {
 367         u16 status;
 368         device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
 369         int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
 370         int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
 371         int timeout = 1000;
 372
 373         pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
 374                            (byte1 << 16));
 375
 376         while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
 377                 udelay(10);
 378
 379         if ((status & I5000_SPD_RDO) && timeout)
 380                 *out = status & 0xff;
 381
 382         if (status & I5000_SPD_SBE || !timeout) {
 383                 printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n",
 384                        d->branch->num, d->channel->num, d->num, byte1, status);
 385                 return -1;
 386         }
 387         return 0;
 388
 389 }
 390
 391 static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
 392                                          int fn, int reg, u8 val)
 393 {
 394         if (i5000_amb_smbus_write(d, 0x84, 00) ||
 395             i5000_amb_smbus_write(d, 0x04, fn) ||
 396             i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
 397             i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
 398             i5000_amb_smbus_write(d, 0x44, val)) {
 399                 printk(BIOS_ERR, "AMB SMBUS write failed\n");
 400                 return 1;
 401         }
 402         return 0;
 403 }
 404
 405 static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
 406                                           int fn, int reg, u16 val)
 407 {
 408         if (i5000_amb_smbus_write(d, 0x88, 00) ||
 409             i5000_amb_smbus_write(d, 0x08, fn) ||
 410             i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
 411             i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
 412             i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
 413             i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
 414                 printk(BIOS_ERR, "AMB SMBUS write failed\n");
 415                 return 1;
 416         }
 417         return 0;
 418 }
 419
 420 static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
 421                                           int fn, int reg, u32 val)
 422 {
 423         if (i5000_amb_smbus_write(d, 0x8c, 00) ||
 424             i5000_amb_smbus_write(d, 0x0c, fn) ||
 425             i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
 426             i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
 427             i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
 428             i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
 429             i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
 430             i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
 431                 printk(BIOS_ERR, "AMB SMBUS write failed\n");
 432                 return 1;
 433         }
 434         return 0;
 435 }
 436
 437 static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
 438                                          int fn, int reg, u32 *val)
 439 {
 440         u8 byte3, byte2, byte1, byte0;
 441
 442         if (i5000_amb_smbus_write(d, 0x80, 00) ||
 443             i5000_amb_smbus_write(d, 0x00, fn) ||
 444             i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
 445             i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
 446             i5000_amb_smbus_read(d, 0x80, &byte3) ||
 447             i5000_amb_smbus_read(d, 0x00, &byte3) ||
 448             i5000_amb_smbus_read(d, 0x00, &byte2) ||
 449             i5000_amb_smbus_read(d, 0x00, &byte1) ||
 450             i5000_amb_smbus_read(d, 0x40, &byte0)) {
 451                 printk(BIOS_ERR, "AMB SMBUS read failed\n");
 452                 return 1;
 453         }
 454         *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
 455         return 0;
 456 }
 457
 458 static void i5000_amb_write_config8(struct i5000_fbdimm *d,
 459                                     int fn, int reg, u32 val)
 460 {
 461         write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
 462 }
 463
 464 static void i5000_amb_write_config16(struct i5000_fbdimm *d,
 465                                      int fn, int reg, u32 val)
 466 {
 467         write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
 468 }
 469
 470 static void i5000_amb_write_config32(struct i5000_fbdimm *d,
 471                                      int fn, int reg, u32 val)
 472 {
 473         write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
 474 }
 475
 476 static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
 477                                    int fn, int reg)
 478 {
 479         return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
 480 }
 481
 482 static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
 483 {
 484         u32 drc, status;
 485
 486         printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
 487                d->branch->num, d->channel->num, d->num, rank, command, addr);
 488
 489         drc = i5000_amb_read_config32(d, 3, AMB_DRC);
 490         drc &= ~((3 << 9) | (1 << 12));
 491         drc |= (rank << 9);
 492
 493         command &= 0x0f;
 494         command |= AMB_DCALCSR_START | (rank << 21);
 495
 496         printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command);
 497         i5000_amb_write_config32(d, 3, AMB_DRC, drc);
 498         i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
 499         i5000_amb_write_config32(d, 4, AMB_DCALCSR, command);
 500
 501         udelay(1000);
 502         while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
 503               & (1 << 31));
 504
 505         if (status & (1 << 30)) {
 506                 printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
 507                 return -1;
 508         }
 509
 510         printk(BIOS_SPEW, "done\n");
 511         return 0;
 512 }
 513
 514 static int i5000_ddr_calibration(struct i5000_fbdimm *d)
 515 {
 516         u32 status;
 517
 518         i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
 519         i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
 520         while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
 521
 522         i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
 523         while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
 524
 525         if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
 526             ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
 527                 return -1;
 528         return 0;
 529 }
 530
 531 static int i5000_ddr_init(struct i5000_fbdimm *d)
 532 {
 533
 534         int rank;
 535         u32 val;
 536         u8 odt;
 537
 538         for(rank = 0; rank < d->ranks; rank++) {
 539                 printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
 540                        d->branch->num, d->channel->num, d->num, rank);
 541
 542                 if (ddr_command(d, 1 << rank,
 543                                 0, AMB_DCALCSR_OPCODE_NOP))
 544                         return -1;
 545
 546                 if (ddr_command(d, 1 << rank,
 547                                 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
 548                         return -1;
 549
 550                 /* EMRS(2) */
 551                 if (ddr_command(d, 1 << rank,
 552                                 2, AMB_DCALCSR_OPCODE_MRS_EMRS))
 553                         return -1;
 554
 555                 /* EMRS(3) */
 556                 if (ddr_command(d, 1 << rank,
 557                                 3, AMB_DCALCSR_OPCODE_MRS_EMRS))
 558                         return -1;
 559
 560                 /* EMRS(1) */
 561                 if (ddr_command(d, 1 << rank,
 562                                 1, AMB_DCALCSR_OPCODE_MRS_EMRS))
 563                         return -1;
 564
 565                 /* MRS: DLL reset */
 566                 if (ddr_command(d, 1 << rank,
 567                                 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
 568                         return -1;
 569
 570                 udelay(20);
 571
 572                 if (ddr_command(d, 1 << rank,
 573                                 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
 574                         return -1;
 575
 576                 if (ddr_command(d, 1 << rank,
 577                                 0, AMB_DCALCSR_OPCODE_REFRESH))
 578                         return -1;
 579
 580                 if (ddr_command(d, 1 << rank, 0,
 581                                 AMB_DCALCSR_OPCODE_REFRESH))
 582                         return -1;
 583
 584                 /* burst length + cas latency */
 585                 val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
 586                         (1 << 19) /* interleaved burst */ |
 587                         (d->setup->t_cl << 20) |
 588                         (((d->setup->t_wr - 1) & 7) << 25);
 589
 590                 printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
 591                 if (ddr_command(d, 1 << rank,
 592                                 val, AMB_DCALCSR_OPCODE_MRS_EMRS))
 593                         return -1;
 594
 595                 /* OCD calibration default */
 596                 if (ddr_command(d, 1 << rank, 0x03800001,
 597                                 AMB_DCALCSR_OPCODE_MRS_EMRS))
 598                         return -1;
 599
 600
 601                 odt = d->odt;
 602                 if (rank)
 603                         odt >>= 4;
 604
 605                 val = (d->setup->t_al << 19) |
 606                         ((odt & 1) << 18) |
 607                         ((odt & 2) << 21) | 1;
 608
 609                 printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
 610
 611                 /* ODT, OCD exit, additive latency */
 612                 if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
 613                         return -1;
 614         }
 615         return 0;
 616 }
 617
 618 static int i5000_amb_preinit(struct i5000_fbdimm *d)
 619 {
 620         u32 *p32 = (u32 *)d->amb_personality_bytes;
 621         u16 *p16 = (u16 *)d->amb_personality_bytes;
 622         u32 id, drc, fbdsbcfg = 0x0909;
 623
 624         printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
 625                d->branch->num, d->channel->num, d->num);
 626
 627         i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
 628         i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
 629
 630         drc = (d->setup->t_al << 4) | (d->setup->t_cl);
 631         printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
 632                d->cmd2datanxt[d->setup->ddr_speed]);
 633
 634         switch(d->setup->ddr_speed) {
 635         case DDR_533MHZ:
 636                 fbdsbcfg |= (1 << 16);
 637                 break;
 638         case DDR_667MHZ:
 639                 fbdsbcfg |= (2 << 16);
 640                 break;
 641         default:
 642                 return -1;
 643         }
 644
 645         printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg);
 646         i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg);
 647         i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
 648         i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
 649                 d->cmd2datanxt[d->setup->ddr_speed]);
 650
 651         i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
 652
 653         if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
 654                 d->vendor = id & 0xffff;
 655                 d->device = id >> 16;
 656         }
 657
 658         pci_mmio_write_config8(d->branch->branchdev,
 659                                d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
 660         return 0;
 661 }
 662
 663 static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
 664 {
 665         int timeout = 10000;
 666         device_t dev = b->branchdev;
 667
 668         printk(BIOS_DEBUG, "  FBD state branch %d: %02x,", b->num, state);
 669
 670         pci_mmio_write_config8(dev, I5000_FBDHPC, state);
 671
 672         printk(BIOS_DEBUG, "waiting for new state...");
 673
 674         while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--)
 675                 udelay(10);
 676
 677         if (timeout) {
 678                 printk(BIOS_DEBUG, "done\n");
 679                 return;
 680         }
 681
 682         printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n",
 683                state, b->num);
 684 }
 685
 686 static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
 687 {
 688         int i = 10;
 689         device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
 690                                 c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
 691
 692         printk(BIOS_DEBUG, "      waiting for pattern recognition...");
 693         while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
 694                 udelay(5000);
 695
 696         printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
 697         printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,
 698                pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
 699         return !i;
 700 }
 701
 702 static const char *pattern_names[16] = {
 703         "EI", "EI", "EI", "EI",
 704         "EI", "EI", "EI", "EI",
 705         "TS0", "TS1", "TS2", "TS3",
 706         "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
 707 };
 708
 709 static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
 710 {
 711         device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
 712                                 c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
 713
 714         printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
 715                c->branch->num, c->num,
 716                pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
 717         pci_mmio_write_config8(dev, 0, pattern);
 718
 719         if (!wait)
 720                 return 0;
 721
 722         return i5000_wait_pattern_recognized(c);
 723 }
 724
 725 static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
 726 {
 727         int i;
 728         device_t branchdev = c->branch->branchdev;
 729         u16 ambpresent = 0x8000;
 730
 731         for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
 732                 if (c->dimm[i].present)
 733                         ambpresent |= (1 << i);
 734         }
 735
 736         printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
 737         pci_write_config16(branchdev,
 738                            c->num ?
 739                            I5000_AMBPRESENT1 :          \
 740                            I5000_AMBPRESENT0, ambpresent);
 741
 742         return 0;
 743 }
 744
 745
 746 static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
 747 {
 748         device_t branchdev = c->branch->branchdev;
 749         int off = c->num ? 0x100 : 0;
 750         u32 portctl;
 751         int i, cnt = 1000;
 752
 753         portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
 754         portctl &= ~0x01000020;
 755         if (mchpad)
 756                 portctl |= 0x00800000;
 757         else
 758                 portctl &= ~0x00800000;
 759         portctl &= ~0x01000020;
 760         pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
 761
 762         /* drive calibration patterns */
 763         if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
 764                 return -1;
 765
 766         if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
 767                 return -1;
 768
 769         while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
 770                 udelay(10);
 771
 772         if (!cnt) {
 773                 printk(BIOS_ERR, "IBIST timeout\n");
 774                 return -1;
 775         }
 776
 777         if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
 778                 return -1;
 779
 780         for(i = 0; i < highest_amb; i++) {
 781                 if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
 782                         return -1;
 783         }
 784
 785         if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
 786                 return -1;
 787
 788         if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
 789                 return -1;
 790
 791         if (i5000_set_ambpresent(c))
 792                 return -1;
 793         return 0;
 794 }
 795
 796 static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
 797 {
 798         int i;
 799         u32 fbdsbcfg = 0x0b1b;
 800
 801         switch(c->setup->ddr_speed) {
 802         case DDR_533MHZ:
 803                 fbdsbcfg |= (1 << 16);
 804                 break;
 805         case DDR_667MHZ:
 806                 fbdsbcfg |= (2 << 16);
 807                 break;
 808         default:
 809                 return -1;
 810         }
 811
 812         pci_mmio_write_config8(c->branch->branchdev,
 813                                c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
 814
 815         for(i = 0; i < 4; i++) {
 816                 if (c->dimm[i].present)
 817                         i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg);
 818         }
 819
 820         return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
 821 }
 822
 823 static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
 824 {
 825         if (i5000_train_channel_idle(c))
 826                 return -1;
 827
 828         return i5000_drive_test_patterns(c, c->highest_amb, 0);
 829 }
 830
 831 static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
 832 {
 833         if (i5000_train_channel_idle(c))
 834                 return -1;
 835
 836         return i5000_drive_test_patterns(c, c->highest_amb, 1);
 837 }
 838
 839 static int i5000_setup_channel(struct i5000_fbd_channel *c)
 840 {
 841         device_t branchdev = c->branch->branchdev;
 842         int off = c->branch->num ? 0x100 : 0;
 843         u32 val;
 844
 845         pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
 846         pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
 847         pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
 848         pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
 849
 850         pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
 851
 852         /* unknown */
 853         val = pci_mmio_read_config32(branchdev, off + 0x0164);
 854         val &= 0xfffbcffc;
 855         val |= 0x4004;
 856         pci_mmio_write_config32(branchdev, off + 0x164, val);
 857
 858         pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
 859         i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
 860         return 0;
 861 }
 862
 863 static int i5000_link_training0(struct i5000_fbd_branch *b)
 864 {
 865         device_t branchdev = b->branchdev;
 866
 867         pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
 868
 869         if (i5000_for_each_channel(b, i5000_setup_channel))
 870                 return -1;
 871
 872         if (i5000_for_each_channel(b, i5000_train_channel_idle))
 873                 return -1;
 874
 875         i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
 876
 877         if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
 878                 return -1;
 879
 880         i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
 881         return 0;
 882 }
 883
 884 static int i5000_link_training1(struct i5000_fbd_branch *b)
 885 {
 886         if (i5000_for_each_channel(b, i5000_train_channel_idle))
 887                 return -1;
 888
 889         i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
 890
 891         if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
 892                 return -1;
 893
 894         i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
 895         return 0;
 896 }
 897
 898
 899 static int i5000_amb_check(struct i5000_fbdimm *d)
 900 {
 901         u32 id = i5000_amb_read_config32(d, 0, 0);
 902
 903         printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n",
 904                d->branch->num, d->channel->num, d->num,
 905                id & 0xffff, id >> 16);
 906
 907         if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
 908                 printk(BIOS_ERR, "AMB mapping failed\n");
 909                 return -1;
 910         }
 911         return 0;
 912 }
 913
 914 static int i5000_amb_postinit(struct i5000_fbdimm *d)
 915 {
 916         u32 *p32 = (u32 *)d->amb_personality_bytes;
 917         u16 *p16 = (u16 *)d->amb_personality_bytes;
 918
 919         i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
 920         i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
 921         i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
 922         return 0;
 923 }
 924
 925 static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
 926 {
 927         struct i5000_fbd_setup *s;
 928         u32 val, tref;
 929         int refi;
 930
 931         s = d->setup;
 932
 933         printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
 934                d->branch->num, d->channel->num, d->num);
 935
 936         val = 0x44;
 937         printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
 938         i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
 939
 940         val = (0x0c << 24) | /* CLK control */
 941                 (1 << 18) | /* ODTZ enabled */
 942                 (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
 943                 ((d->setup->t_al & 0x0f) << 4) | /* additive latency */
 944                 (d->setup->t_cl & 0x0f); /* CAS latency */
 945
 946         if (d->ranks > 1) {
 947                 val |= (0x03 << 9);
 948         } else {
 949                 val |= (0x01 << 9);
 950         }
 951
 952         printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val);
 953         i5000_amb_write_config32(d, 3, AMB_DRC, val);
 954
 955         val = (d->sdram_width << 30) |
 956                 ((d->ranks == 2 ? 1 : 0) << 29) |
 957                 ((d->banks == 8 ? 1 : 0) << 28) |
 958                 ((d->rows - 13) << 26) |
 959                 ((d->columns - 10) << 24) |
 960                 (1 << 16) | /* Auto refresh exit */
 961                 (0x27 << 8) | /* t_xsnr */
 962                 (d->setup->t_rp << 4) |
 963                 (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
 964
 965         printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
 966         i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
 967
 968         tref = 15;
 969
 970         switch(d->t_refi & 0x0f) {
 971         case 0:
 972                 refi = 15625;
 973                 break;
 974         case 1:
 975                 refi = 3900;
 976                 tref = 3;
 977                 break;
 978         case 2:
 979                 refi = 7800;
 980                 tref = 7;
 981                 break;
 982         case 3:
 983                 refi = 31250;
 984                 break;
 985         case 4:
 986                 refi = 62500;
 987                 break;
 988         case 5:
 989                 refi = 125000;
 990                 break;
 991         default:
 992                 printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n",
 993                        d->t_refi & 0x0f);
 994                 refi = 7800;
 995                 break;
 996         }
 997
 998         s->t_ref = tref;
 999         val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
1000
1001         printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val);
1002         i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
1003
1004         u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
1005                 (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
1006         u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
1007
1008         val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
1009                 ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
1010                 ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
1011                 ((s->t_rtp - 2) << 27);
1012
1013         switch(s->t_ras) {
1014         case 15:
1015                 val |= (1 << 29);
1016                 break;
1017         case 12:
1018                 val |= (2 << 29);
1019                 break;
1020         default:
1021                 break;
1022         }
1023
1024         printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val);
1025         i5000_amb_write_config32(d, 3, AMB_DRT, val);
1026         return 0;
1027 }
1028
1029 static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
1030 {
1031         printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
1032                d->branch->num, d->channel->num, d->num, rank, pattern);
1033
1034         i5000_amb_write_config32(d, 3, AMB_DAREFTC,
1035                                  i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
1036
1037         i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
1038         i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
1039         i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
1040         return 0;
1041 }
1042
1043 static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
1044 {
1045         int cnt = 1000;
1046         u32 res;
1047
1048         while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
1049                 udelay(1000);
1050
1051         if (cnt && !(res & (1 << 30)))
1052                 return 0;
1053
1054         printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
1055                d->branch->num, d->channel->num, d->num, rank);
1056         return -1;
1057 }
1058
1059 static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
1060 {
1061         if (i5000_do_amb_membist_start(d, 1, 0))
1062                 return -1;
1063         return 0;
1064 }
1065
1066 static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
1067 {
1068
1069         if (d->ranks < 2)
1070                 return 0;
1071         if (i5000_do_amb_membist_start(d, 2, 0))
1072                 return -1;
1073         return 0;
1074 }
1075
1076 static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
1077 {
1078         if (i5000_do_amb_membist_status(d, 1))
1079                 return -1;
1080         return 0;
1081 }
1082
1083 static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
1084 {
1085         if (d->ranks < 2)
1086                 return 0;
1087
1088         if (i5000_do_amb_membist_status(d, 2))
1089                 return -1;
1090         return 0;
1091 }
1092
1093 static int i5000_amb_membist_end(struct i5000_fbdimm *d)
1094 {
1095         printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
1096         return 0;
1097 }
1098
1099 static int i5000_membist(struct i5000_fbd_setup *setup)
1100 {
1101         return  i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
1102                 i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
1103                 i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
1104                 i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
1105                 i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
1106 }
1107
1108 static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
1109 {
1110         u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
1111         tmp &= ~(1 << 16);
1112         printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
1113         i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
1114         return 0;
1115 }
1116
1117 static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
1118 {
1119         i5000_amb_write_config32(d, 1, AMB_FERR, 9);
1120         i5000_amb_write_config32(d, 1, AMB_NERR, 9);
1121         i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
1122         i5000_amb_write_config8(d, 3, 0x80, 0xcf);
1123         i5000_amb_write_config8(d, 3, 0x81, 0xd3);
1124         i5000_amb_write_config8(d, 3, 0x82, 0xf8);
1125         return 0;
1126 }
1127
1128 static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
1129 {
1130         u32 val;
1131
1132         if (c->dimm[0].present || c->dimm[1].present) {
1133                 val = (((c->columns - 10) & 3) |
1134                        (((c->rows - 13) & 3) << 2) |
1135                        (((c->ranks == 2) ? 1 : 0) << 4) |
1136                        (((c->banks == 8) ? 1 : 0) << 5) |
1137                        ((c->width ? 1 : 0) << 6) |
1138                        (1 << 7) | /* Electrical Throttling enabled */
1139                        (1 << 8)); /* DIMM present and compatible */
1140                 printk(BIOS_DEBUG, "MTR0: %04x\n", val);
1141                 pci_mmio_write_config16(c->branch->branchdev, mtr, val);
1142         }
1143
1144         if (c->dimm[2].present || c->dimm[3].present) {
1145                 val = (((c->columns - 10) & 3) |
1146                        (((c->rows - 13) & 3) << 4) |
1147                        ((c->ranks ? 1 : 0) << 4) |
1148                        (((c->banks == 8) ? 1 : 0) << 5) |
1149                        ((c->width ? 1 : 0) << 6) |
1150                        (1 << 7) | /* Electrical Throttling enabled */
1151                        (1 << 8)); /* DIMM present and compatible */
1152                 printk(BIOS_DEBUG, "MTR1: %04x\n", val);
1153                 pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
1154         }
1155 }
1156
1157 static int get_dmir(u8 *rankmap, int *_set, int limit)
1158 {
1159         int i, dmir = 0, set = 0;
1160
1161         for(i = 7; set < limit && i >= 0; i--) {
1162                 if (!(*rankmap & (1 << i)))
1163                         continue;
1164
1165                 *rankmap &= ~(1 << i);
1166
1167                 switch(limit) {
1168                 case 1:
1169                         dmir |= (i |
1170                                  (i << 3) |
1171                                  (i << 6) |
1172                                  (i << 9));
1173                         break;
1174                 case 2:
1175                         dmir |= (i << (set * 3)) |
1176                                 (i << (6 + set * 3));
1177                         break;
1178                 case 4:
1179                         dmir |= (i << (set * 3));
1180                         break;
1181
1182                 default:
1183                         break;
1184                 }
1185                 set++;
1186         }
1187         *_set = set;
1188         return dmir;
1189 }
1190
1191 static int i5000_setup_dmir(struct i5000_fbd_branch *b)
1192 {
1193         struct i5000_fbdimm *d;
1194         device_t dev = b->branchdev;
1195         u8 rankmap = 0, dmir = 0;
1196         u32 dmirval = 0;
1197         int i, set, rankoffset = 0, ranksize = 0, ranks = 0;
1198
1199         if (!b->used)
1200                 return 0;
1201
1202         for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
1203                 rankmap >>= 2;
1204                 d = b->channel[0].dimm + i;
1205
1206                 if (!d->present)
1207                         continue;
1208
1209                 if (d->ranks == 2) {
1210                         rankmap |= 0xc0;
1211                         ranks += 2;
1212                 } else {
1213                         rankmap |= 0x40;
1214                         ranks++;
1215                 }
1216         }
1217
1218         printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);
1219
1220         dmir = I5000_DMIR0;
1221
1222         ranksize = b->channel[0].dimm[0].ranksize << 8;
1223
1224         if (!b->setup->single_channel)
1225                 ranksize <<= 1;
1226
1227         while(ranks) {
1228
1229                 if (ranks >= 4)
1230                         dmirval = get_dmir(&rankmap, &set, 4);
1231                 else if (ranks >= 2)
1232                         dmirval = get_dmir(&rankmap, &set, 2);
1233                 else
1234                         dmirval = get_dmir(&rankmap, &set, 1);
1235
1236                 ranks -= set;
1237
1238                 dmirval |= rankoffset + (set * ranksize);
1239
1240                 rankoffset += (set * ranksize);
1241
1242                 printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
1243                        dmirval);
1244                 pci_mmio_write_config32(dev, dmir, dmirval);
1245                 dmir += 4;
1246         }
1247
1248         for(; dmir <= I5000_DMIR4; dmir += 4) {
1249                 printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
1250                        dmirval);
1251                 pci_mmio_write_config32(dev, dmir, dmirval);
1252         }
1253         return rankoffset;
1254 }
1255
1256 static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
1257 {
1258         device_t dev16 = PCI_ADDR(0, 16, 1, 0);
1259         u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
1260
1261         size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;
1262         size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;
1263
1264         minsize = MIN(size0, size1);
1265
1266         if (size0 > size1) {
1267                 tmp = size1;
1268                 size1 = size0;
1269                 size0 = tmp;
1270         }
1271
1272         if (size0 == size1) {
1273                 mir0 = (size0 << 1) | 3;
1274                 mir1 = (size0 << 1);
1275                 mir2 = (size0 << 1);
1276         } else if (!size0) {
1277                 mir0 = size1 | 1;
1278                 mir1 = size1;
1279                 mir2 = size1;
1280         } else {
1281                 mir0 = (size0 << 1) | 3;
1282                 mir1 = (size1 + size0) | 1;
1283                 mir2 = size1 + size0;
1284         }
1285
1286         printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
1287         printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
1288         printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
1289
1290         pci_mmio_write_config16(dev16, I5000_MIR0, mir0);
1291         pci_mmio_write_config16(dev16, I5000_MIR1, mir1);
1292         pci_mmio_write_config16(dev16, I5000_MIR2, mir2);
1293 }
1294
1295 static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
1296 {
1297         device_t dev16 = PCI_ADDR(0, 16, 1, 0);
1298         u32 tolm, drta, drtb, mc, mca;
1299         int t_wrc, bl2;
1300
1301         bl2 = (setup->bl & BL_BL8) ? 4 :2;
1302         t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
1303                 setup->t_wr + setup->t_rp;
1304
1305         drta = (setup->t_ref & 0x0f) |
1306                 ((setup->t_rrd & 0x0f) << 4) |
1307                 ((setup->t_rfc & 0xff) << 8) |
1308                 ((setup->t_rc & 0x3f) << 16) |
1309                 ((t_wrc & 0x3f) << 22) |
1310                 (setup->t_al & 0x07) << 28;
1311
1312         drtb = (bl2) |
1313                 (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
1314                 (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
1315                 (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
1316                 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
1317
1318         mc = (1 << 30) | /* enable retry */
1319                 (3 << 25) | /* bad RAM threshold */
1320                 (1 << 21) | /* INITDONE */
1321                 (1 << 20) | /* FSB enable */
1322                 /* Electrical throttling: 20 clocks */
1323                 ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |
1324                 (1 << 8) | /* enhanced scrub mode */
1325                 (1 << 7) | /* enable patrol scrub */
1326                 (1 << 6) | /* enable demand scrubing */
1327                 (1 << 5); /* enable northbound error detection */
1328
1329         printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
1330         pci_mmio_write_config32(dev16, I5000_DRTA, drta);
1331         pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
1332         pci_mmio_write_config32(dev16, I5000_MC, mc);
1333
1334         mca = pci_mmio_read_config32(dev16, I5000_MCA);
1335
1336         mca |= (7 << 28);
1337         if (setup->single_channel)
1338                 mca |= (1 << 14);
1339         else
1340                 mca &= ~(1 << 14);
1341         printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
1342         pci_mmio_write_config32(dev16, I5000_MCA, mca);
1343
1344         pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
1345
1346         i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
1347         i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
1348         i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
1349         i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
1350
1351         i5000_setup_interleave(setup);
1352
1353         if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
1354                 tolm = 0xe00;
1355
1356         tolm <<= 4;
1357         printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
1358         pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
1359         return 0;
1360 }
1361
1362 static void i5000_init_setup(struct i5000_fbd_setup *setup)
1363 {
1364         int branch, channel, dimm, i = 0;
1365         struct i5000_fbdimm *d;
1366         struct i5000_fbd_channel *c;
1367         struct i5000_fbd_branch *b;
1368
1369         setup->bl = 3;
1370         /* default to highest memory frequency. If a module doesn't
1371            support it, it will decrease this setting in spd_read */
1372         setup->ddr_speed = DDR_667MHZ;
1373
1374         for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
1375                 b = setup->branch + branch;
1376                 b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
1377                 b->setup = setup;
1378                 b->num = branch;
1379
1380                 for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
1381                         c = b->channel + channel;
1382                         c->branch = b;
1383                         c->setup = setup;
1384                         c->num = channel;
1385
1386                         for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
1387                                 d = c->dimm + dimm;
1388                                 setup->dimms[i++] = d;
1389                                 d->channel = c;
1390                                 d->branch = b;
1391                                 d->setup = setup;
1392                                 d->num = dimm;
1393                                 d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
1394                         }
1395                 }
1396         }
1397 }
1398
1399 static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
1400 {
1401         /* register write captured from vendor BIOS, but undocument by Intel */
1402         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
1403
1404         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
1405         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
1406         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
1407         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
1408         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
1409
1410         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
1411         pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
1412         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
1413         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
1414         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
1415
1416         pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
1417         pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
1418         pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
1419         pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
1420
1421         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
1422         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
1423         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
1424         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
1425         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
1426
1427         pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
1428         pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
1429
1430         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
1431         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
1432
1433         pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
1434         pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
1435         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
1436         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
1437         pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
1438         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
1439         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
1440         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
1441         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
1442         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
1443         pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
1444         pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
1445         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
1446
1447         if (setup->branch[0].channel[0].used)
1448                 pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
1449
1450         if (setup->branch[0].channel[1].used)
1451                 pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
1452
1453         if (setup->branch[1].channel[0].used)
1454                 pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
1455
1456         if (setup->branch[1].channel[1].used)
1457                 pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
1458 }
1459 static void i5000_dump_error_registers(void)
1460 {
1461         device_t dev = PCI_ADDR(0, 16, 1, 0);
1462
1463         printk(BIOS_ERR, "Dump of FBD error registers:\n"
1464                "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
1465                "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
1466                "EMASK_FBD:    0x%08x\n"
1467                "ERR0_FBD:     0x%08x\n"
1468                "ERR1_FBD:     0x%08x\n"
1469                "ERR2_FBD:     0x%08x\n"
1470                "MC_ERR_FBD:   0x%08x\n",
1471                pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
1472                pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
1473                pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
1474                pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
1475                pci_mmio_read_config32(dev, I5000_EMASK_FBD),
1476                pci_mmio_read_config32(dev, I5000_ERR0_FBD),
1477                pci_mmio_read_config32(dev, I5000_ERR1_FBD),
1478                pci_mmio_read_config32(dev, I5000_ERR2_FBD),
1479                pci_mmio_read_config32(dev, I5000_MCERR_FBD));
1480
1481         printk(BIOS_ERR, "Non recoverable error registers:\n"
1482                "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
1483                "NRECFGLOG:    0x%08x\n",
1484                pci_mmio_read_config32(dev, I5000_NRECMEMA),
1485                pci_mmio_read_config32(dev, I5000_NRECMEMB),
1486                pci_mmio_read_config32(dev, I5000_NRECFGLOG));
1487
1488         printk(BIOS_ERR, "Packet data:\n"
1489                "NRECFBDA: 0x%08x\n"
1490                "NRECFBDB: 0x%08x\n"
1491                "NRECFBDC: 0x%08x\n"
1492                "NRECFBDD: 0x%08x\n"
1493                "NRECFBDE: 0x%08x\n",
1494                pci_mmio_read_config32(dev, I5000_NRECFBDA),
1495                pci_mmio_read_config32(dev, I5000_NRECFBDB),
1496                pci_mmio_read_config32(dev, I5000_NRECFBDC),
1497                pci_mmio_read_config32(dev, I5000_NRECFBDD),
1498                pci_mmio_read_config32(dev, I5000_NRECFBDE));
1499
1500         printk(BIOS_ERR, "recoverable error registers:\n"
1501                "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
1502                "RECFGLOG:    0x%08x\n",
1503                pci_mmio_read_config32(dev, I5000_RECMEMA),
1504                pci_mmio_read_config32(dev, I5000_RECMEMB),
1505                pci_mmio_read_config32(dev, I5000_RECFGLOG));
1506
1507         printk(BIOS_ERR, "Packet data:\n"
1508                "RECFBDA: 0x%08x\n"
1509                "RECFBDB: 0x%08x\n"
1510                "RECFBDC: 0x%08x\n"
1511                "RECFBDD: 0x%08x\n"
1512                "RECFBDE: 0x%08x\n",
1513                pci_mmio_read_config32(dev, I5000_RECFBDA),
1514                pci_mmio_read_config32(dev, I5000_RECFBDB),
1515                pci_mmio_read_config32(dev, I5000_RECFBDC),
1516                pci_mmio_read_config32(dev, I5000_RECFBDD),
1517                pci_mmio_read_config32(dev, I5000_RECFBDE));
1518
1519 }
1520
1521 static void i5000_try_restart(const char *msg)
1522 {
1523         printk(BIOS_INFO, msg);
1524         i5000_dump_error_registers();
1525 //      outb(0x06, 0xcf9);
1526         for(;;) asm volatile("hlt");
1527 }
1528
1529 static void i5000_pam_setup(void)
1530 {
1531         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
1532         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
1533         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
1534         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
1535         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
1536         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
1537         pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
1538 }
1539
1540 static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
1541 {
1542         int fbd, fsb, ddrfrq, ddrfrqnow;
1543         msr_t msr;
1544         device_t dev = PCI_ADDR(0, 16, 1, 0);
1545
1546         switch(setup->ddr_speed) {
1547         case DDR_667MHZ:
1548                 fbd = 667;
1549                 break;
1550         case DDR_533MHZ:
1551                 fbd = 533;
1552                 break;
1553         default:
1554                 printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__);
1555                 return 1;
1556         }
1557
1558         /* mainboard specific callback */
1559         if (mainboard_set_fbd_clock(fbd)) {
1560                 printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__);
1561                 return 1;
1562         }
1563
1564         msr = rdmsr(0xcd);
1565
1566         switch(msr.lo & 7) {
1567         case 1:
1568                 fsb = 533;
1569                 break;
1570         case 4:
1571                 fsb = 667;
1572                 break;
1573         default:
1574                 printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7);
1575                 return 1;
1576         }
1577
1578
1579         ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56);
1580         ddrfrqnow = ddrfrq;
1581         ddrfrq &= ~0x3;
1582
1583         if (fsb < fbd)
1584                 ddrfrq |= 2;
1585         else if (fsb > fbd)
1586                 ddrfrq |= 3;
1587
1588         switch((ddrfrq >> 4) & 3) {
1589         case 0: /* 1:1 mapping */
1590                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff);
1591                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
1592                 pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff);
1593                 pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
1594                 pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00);
1595                 pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
1596                 pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
1597                 break;
1598         case 2: /* 4:5 mapping */
1599                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323);
1600                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400);
1601                 pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023);
1602                 pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04);
1603                 pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08);
1604                 pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
1605                 pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04);
1606                 break;
1607         case 3:
1608                 /* 5:4 mapping */
1609                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230);
1610                 pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
1611                 pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323);
1612                 pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
1613                 pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02);
1614                 pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10);
1615                 pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
1616                 break;
1617         default:
1618                 printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq);
1619                 return -1;
1620         }
1621
1622         if (ddrfrq != ddrfrqnow) {
1623                 printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n",
1624                        ddrfrqnow, ddrfrq);
1625                 pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
1626                 /* FSB:FBD mapping changed, needs hard reset */
1627                 outb(0x06, 0xcf9);
1628                 for(;;) asm volatile("hlt");
1629         }
1630         return 0;
1631 }
1632
1633 void i5000_fbdimm_init(void)
1634 {
1635         struct i5000_fbd_setup setup;
1636         u32 mca, mc;
1637
1638         memset(&setup, 0, sizeof(setup));
1639
1640         pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
1641
1642         i5000_init_setup(&setup);
1643
1644         pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
1645                            pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
1646
1647         i5000_clear_fbd_errors();
1648
1649         printk(BIOS_INFO, "detecting memory modules\n");
1650         if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
1651                 printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
1652                 return;
1653         }
1654
1655         if (i5000_setup_clocking(&setup)) {
1656                 printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__);
1657                 return;
1658         }
1659
1660         /* posted CAS requires t_AL = t_RCD - 1 */
1661         setup.t_al = setup.t_rcd - 1;
1662
1663         printk(BIOS_DEBUG, "global timing parameters:\n"
1664                "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
1665                "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
1666                setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
1667                setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
1668                setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
1669                setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
1670
1671         setup.single_channel = (!(setup.branch[0].channel[1].used ||
1672                                   setup.branch[1].channel[0].used ||
1673                                   setup.branch[1].channel[1].used));
1674
1675         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
1676         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
1677
1678         /* enable or disable single channel mode */
1679         mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
1680         if (setup.single_channel)
1681                 mca |= (1 << 14);
1682         else
1683                 mca &= ~(1 << 14);
1684         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
1685
1686         /*
1687          * i5000 supports burst length 8 only in single channel mode
1688          * so strip BL_BL8 if we're operating in multichannel mode
1689          */
1690
1691         if (!setup.single_channel)
1692                 setup.bl &= ~BL_BL8;
1693
1694         if (!setup.bl)
1695                 die("No supported burst length found\n");
1696
1697         mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
1698         /* disable error checking for training */
1699         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
1700
1701         printk(BIOS_INFO, "performing fbd link initialization...");
1702         if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
1703             i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
1704             i5000_for_each_branch(&setup, i5000_link_training0) ||
1705             i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
1706             i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
1707             i5000_for_each_branch(&setup, i5000_link_training1)) {
1708                 i5000_try_restart("failed\n");
1709         }
1710         printk(BIOS_INFO, "done\n");
1711         printk(BIOS_INFO, "initializing memory...");
1712
1713         if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
1714             i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
1715             i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
1716                 i5000_try_restart("failed\n");
1717         }
1718         printk(BIOS_INFO,"done\n");
1719         printk(BIOS_INFO, "clearing memory...");
1720
1721         if (i5000_membist(&setup))
1722                 i5000_try_restart("failed\n");
1723         else
1724                 printk(BIOS_INFO, "done\n");
1725
1726         if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
1727                 i5000_try_restart("failed to enable auto refresh\n");
1728
1729         i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT);
1730         i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT);
1731
1732         if (i5000_for_each_branch(&setup, i5000_link_training0))
1733                 i5000_try_restart("Channel training failed\n");
1734
1735         if (setup.branch[0].used)
1736                 i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY);
1737
1738         if (setup.branch[1].used)
1739                 i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY);
1740
1741         i5000_clear_fbd_errors();
1742
1743         /* enable error checking */
1744         pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
1745
1746         i5000_dram_timing_init(&setup);
1747
1748         i5000_reserved_register_init(&setup);
1749
1750         i5000_pam_setup();
1751
1752         if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
1753                 i5000_try_restart("failed to clear error status\n");
1754
1755         if (setup.branch[0].used)
1756                 i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
1757
1758         if (setup.branch[1].used)
1759                 i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
1760
1761 #if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
1762         if (ram_check_nodie(0x000000, 0x0a0000) ||
1763             ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
1764                 i5000_try_restart("RAM verification failed");
1765
1766         }
1767 #endif
1768
1769         printk(BIOS_INFO, "Memory initialization finished\n");
1770 }