src/northbridge/intel/i440lx/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
   5  * Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #include <console/console.h>
  23 #include <arch/io.h>
  24 #include <stdint.h>
  25 #include <device/device.h>
  26 #include <device/pci.h>
  27 #include <device/pci_ids.h>
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <bitops.h>
  31 #include <cpu/cpu.h>
  32 #include <pc80/keyboard.h>
  33 #include "chip.h"
  34 #include "northbridge.h"
  35 #include "i440lx.h"
  36
  37 /* This code is mostly same as 440BX created by Uwe Hermann,
  38  * i done only very minor changes like renamed functions to 440lx etc
  39  * Maciej
  40  */
  41
  42 /* TODO:
  43  * - maybe this could print Northbridge i440LX Init?
  44  */
  45 static void northbridge_init(device_t dev)
  46 {
  47         printk(BIOS_SPEW, "Northbridge Init\n");
  48 }
  49
  50 static struct device_operations northbridge_operations = {
  51         .read_resources   = pci_dev_read_resources,
  52         .set_resources    = pci_dev_set_resources,
  53         .enable_resources = pci_dev_enable_resources,
  54         .init             = northbridge_init,
  55         .enable           = 0,
  56         .ops_pci          = 0,
  57 };
  58
  59 static const struct pci_driver northbridge_driver __pci_driver = {
  60         .ops = &northbridge_operations,
  61         .vendor = PCI_VENDOR_ID_INTEL,
  62         .device = 0x7180,
  63 };
  64
  65 #if CONFIG_WRITE_HIGH_TABLES==1
  66 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  67 extern uint64_t high_tables_base, high_tables_size;
  68 #endif
  69
  70 static void i440lx_domain_set_resources(device_t dev)
  71 {
  72         device_t mc_dev;
  73         uint32_t pci_tolm;
  74
  75         pci_tolm = find_pci_tolm(dev->link_list);
  76         mc_dev = dev->link_list->children;
  77         if (mc_dev) {
  78                 unsigned long tomk, tolmk;
  79                 int idx;
  80
  81                 /* Figure out which areas are/should be occupied by RAM. The
  82                  * value of the highest DRB denotes the end of the physical
  83                  * memory (in units of 8MB).
  84                  */
  85                 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
  86
  87                 /* Convert to KB. */
  88                 tomk *= (8 * 1024);
  89
  90                 printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
  91
  92                 /* Compute the top of low memory. */
  93                 tolmk = pci_tolm / 1024;
  94
  95                 if (tolmk >= tomk) {
  96                         /* The PCI hole does not overlap the memory. */
  97                         tolmk = tomk;
  98                 }
  99
 100                 /* Report the memory regions. */
 101                 idx = 10;
 102                 ram_resource(dev, idx++, 0, 640);
 103                 ram_resource(dev, idx++, 768, tolmk - 768);
 104
 105 #if CONFIG_WRITE_HIGH_TABLES==1
 106                 /* Leave some space for ACPI, PIRQ and MP tables */
 107                 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
 108                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 109 #endif
 110         }
 111         assign_resources(dev->link_list);
 112 }
 113
 114 static struct device_operations pci_domain_ops = {
 115         .read_resources         = pci_domain_read_resources,
 116         .set_resources          = i440lx_domain_set_resources,
 117         .enable_resources       = NULL,
 118         .init                   = NULL,
 119         .scan_bus               = pci_domain_scan_bus,
 120 };
 121
 122 static void cpu_bus_init(device_t dev)
 123 {
 124         initialize_cpus(dev->link_list);
 125 }
 126
 127 static void cpu_bus_noop(device_t dev)
 128 {
 129 }
 130
 131 static struct device_operations cpu_bus_ops = {
 132         .read_resources   = cpu_bus_noop,
 133         .set_resources    = cpu_bus_noop,
 134         .enable_resources = cpu_bus_noop,
 135         .init             = cpu_bus_init,
 136         .scan_bus         = 0,
 137 };
 138
 139 static void enable_dev(struct device *dev)
 140 {
 141         /* Set the operations if it is a special bus type */
 142         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 143                 dev->ops = &pci_domain_ops;
 144                 pci_set_method(dev);
 145         }
 146         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 147                 dev->ops = &cpu_bus_ops;
 148         }
 149 }
 150
 151 struct chip_operations northbridge_intel_i440lx_ops = {
 152         CHIP_NAME("Intel 82443LX (440LX) Northbridge")
 153         .enable_dev = enable_dev,
 154 };