1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include <pc80/keyboard.h>
13 #include "northbridge.h"
16 static void northbridge_init(device_t dev)
18 printk(BIOS_SPEW, "Northbridge Init\n");
21 static struct device_operations northbridge_operations = {
22 .read_resources = pci_dev_read_resources,
23 .set_resources = pci_dev_set_resources,
24 .enable_resources = pci_dev_enable_resources,
25 .init = northbridge_init,
30 static const struct pci_driver northbridge_driver __pci_driver = {
31 .ops = &northbridge_operations,
32 .vendor = PCI_VENDOR_ID_INTEL,
36 static void ram_resource(device_t dev, unsigned long index,
37 unsigned long basek, unsigned long sizek)
39 struct resource *resource;
44 resource = new_resource(dev, index);
45 resource->base = ((resource_t)basek) << 10;
46 resource->size = ((resource_t)sizek) << 10;
47 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
48 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
51 static void tolm_test(void *gp, struct device *dev, struct resource *new)
53 struct resource **best_p = gp;
54 struct resource *best;
56 if (!best || (best->base > new->base)) {
62 static uint32_t find_pci_tolm(struct bus *bus)
67 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
69 if (min && tolm > min->base) {
75 #if CONFIG_WRITE_HIGH_TABLES==1
76 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
77 extern uint64_t high_tables_base, high_tables_size;
80 static void i440bx_domain_set_resources(device_t dev)
85 pci_tolm = find_pci_tolm(dev->link_list);
86 mc_dev = dev->link_list->children;
88 unsigned long tomk, tolmk;
91 /* Figure out which areas are/should be occupied by RAM. The
92 * value of the highest DRB denotes the end of the physical
93 * memory (in units of 8MB).
95 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
100 printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
102 /* Compute the top of low memory. */
103 tolmk = pci_tolm / 1024;
106 /* The PCI hole does not overlap the memory. */
110 /* Report the memory regions. */
112 ram_resource(dev, idx++, 0, 640);
113 ram_resource(dev, idx++, 768, tolmk - 768);
115 #if CONFIG_WRITE_HIGH_TABLES==1
116 /* Leave some space for ACPI, PIRQ and MP tables */
117 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
118 high_tables_size = HIGH_TABLES_SIZE * 1024;
121 assign_resources(dev->link_list);
124 static struct device_operations pci_domain_ops = {
125 .read_resources = pci_domain_read_resources,
126 .set_resources = i440bx_domain_set_resources,
127 .enable_resources = NULL,
129 .scan_bus = pci_domain_scan_bus,
132 static void cpu_bus_init(device_t dev)
134 initialize_cpus(dev->link_list);
137 static void cpu_bus_noop(device_t dev)
141 static struct device_operations cpu_bus_ops = {
142 .read_resources = cpu_bus_noop,
143 .set_resources = cpu_bus_noop,
144 .enable_resources = cpu_bus_noop,
145 .init = cpu_bus_init,
149 static void enable_dev(struct device *dev)
151 /* Set the operations if it is a special bus type */
152 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
153 dev->ops = &pci_domain_ops;
156 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
157 dev->ops = &cpu_bus_ops;
161 struct chip_operations northbridge_intel_i440bx_ops = {
162 CHIP_NAME("Intel 82443BX (440BX) Northbridge")
163 .enable_dev = enable_dev,