src/northbridge/intel/i440bx/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include <cpu/cpu.h>
  11 #include <pc80/keyboard.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14 #include "i440bx.h"
  15
  16 static void northbridge_init(device_t dev)
  17 {
  18         printk(BIOS_SPEW, "Northbridge Init\n");
  19 }
  20
  21 static struct device_operations northbridge_operations = {
  22         .read_resources   = pci_dev_read_resources,
  23         .set_resources    = pci_dev_set_resources,
  24         .enable_resources = pci_dev_enable_resources,
  25         .init             = northbridge_init,
  26         .enable           = 0,
  27         .ops_pci          = 0,
  28 };
  29
  30 static const struct pci_driver northbridge_driver __pci_driver = {
  31         .ops = &northbridge_operations,
  32         .vendor = PCI_VENDOR_ID_INTEL,
  33         .device = 0x7190,
  34 };
  35
  36 #if CONFIG_WRITE_HIGH_TABLES==1
  37 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  38 extern uint64_t high_tables_base, high_tables_size;
  39 #endif
  40
  41 static void i440bx_domain_set_resources(device_t dev)
  42 {
  43         device_t mc_dev;
  44         uint32_t pci_tolm;
  45
  46         pci_tolm = find_pci_tolm(dev->link_list);
  47         mc_dev = dev->link_list->children;
  48         if (mc_dev) {
  49                 unsigned long tomk, tolmk;
  50                 int idx;
  51
  52                 /* Figure out which areas are/should be occupied by RAM. The
  53                  * value of the highest DRB denotes the end of the physical
  54                  * memory (in units of 8MB).
  55                  */
  56                 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
  57
  58                 /* Convert to KB. */
  59                 tomk *= (8 * 1024);
  60
  61                 printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
  62
  63                 /* Compute the top of low memory. */
  64                 tolmk = pci_tolm / 1024;
  65
  66                 if (tolmk >= tomk) {
  67                         /* The PCI hole does not overlap the memory. */
  68                         tolmk = tomk;
  69                 }
  70
  71                 /* Report the memory regions. */
  72                 idx = 10;
  73                 ram_resource(dev, idx++, 0, 640);
  74                 ram_resource(dev, idx++, 768, tolmk - 768);
  75
  76 #if CONFIG_WRITE_HIGH_TABLES==1
  77                 /* Leave some space for ACPI, PIRQ and MP tables */
  78                 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
  79                 high_tables_size = HIGH_TABLES_SIZE * 1024;
  80 #endif
  81         }
  82         assign_resources(dev->link_list);
  83 }
  84
  85 static struct device_operations pci_domain_ops = {
  86         .read_resources         = pci_domain_read_resources,
  87         .set_resources          = i440bx_domain_set_resources,
  88         .enable_resources       = NULL,
  89         .init                   = NULL,
  90         .scan_bus               = pci_domain_scan_bus,
  91 };
  92
  93 static void cpu_bus_init(device_t dev)
  94 {
  95         initialize_cpus(dev->link_list);
  96 }
  97
  98 static void cpu_bus_noop(device_t dev)
  99 {
 100 }
 101
 102 static struct device_operations cpu_bus_ops = {
 103         .read_resources   = cpu_bus_noop,
 104         .set_resources    = cpu_bus_noop,
 105         .enable_resources = cpu_bus_noop,
 106         .init             = cpu_bus_init,
 107         .scan_bus         = 0,
 108 };
 109
 110 static void enable_dev(struct device *dev)
 111 {
 112         /* Set the operations if it is a special bus type */
 113         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 114                 dev->ops = &pci_domain_ops;
 115                 pci_set_method(dev);
 116         }
 117         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 118                 dev->ops = &cpu_bus_ops;
 119         }
 120 }
 121
 122 struct chip_operations northbridge_intel_i440bx_ops = {
 123         CHIP_NAME("Intel 82443BX (440BX) Northbridge")
 124         .enable_dev = enable_dev,
 125 };