src/northbridge/intel/i440bx/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include <cpu/cpu.h>
  11 #include <pc80/keyboard.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14 #include "i440bx.h"
  15
  16 static void northbridge_init(device_t dev)
  17 {
  18         printk_spew("Northbridge Init\n");
  19 }
  20
  21 static struct device_operations northbridge_operations = {
  22         .read_resources   = pci_dev_read_resources,
  23         .set_resources    = pci_dev_set_resources,
  24         .enable_resources = pci_dev_enable_resources,
  25         .init             = northbridge_init,
  26         .enable           = 0,
  27         .ops_pci          = 0,
  28 };
  29
  30 static const struct pci_driver northbridge_driver __pci_driver = {
  31         .ops = &northbridge_operations,
  32         .vendor = PCI_VENDOR_ID_INTEL,
  33         .device = 0x7190,
  34 };
  35
  36 static void ram_resource(device_t dev, unsigned long index,
  37         unsigned long basek, unsigned long sizek)
  38 {
  39         struct resource *resource;
  40
  41         if (!sizek) {
  42                 return;
  43         }
  44         resource = new_resource(dev, index);
  45         resource->base  = ((resource_t)basek) << 10;
  46         resource->size  = ((resource_t)sizek) << 10;
  47         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  48                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  49 }
  50
  51 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  52 {
  53         struct resource **best_p = gp;
  54         struct resource *best;
  55         best = *best_p;
  56         if (!best || (best->base > new->base)) {
  57                 best = new;
  58         }
  59         *best_p = best;
  60 }
  61
  62 static uint32_t find_pci_tolm(struct bus *bus)
  63 {
  64         struct resource *min;
  65         uint32_t tolm;
  66         min = 0;
  67         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  68         tolm = 0xffffffffUL;
  69         if (min && tolm > min->base) {
  70                 tolm = min->base;
  71         }
  72         return tolm;
  73 }
  74
  75 #if CONFIG_WRITE_HIGH_TABLES==1
  76 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  77 extern uint64_t high_tables_base, high_tables_size;
  78 #endif
  79
  80 static void i440bx_domain_set_resources(device_t dev)
  81 {
  82         device_t mc_dev;
  83         uint32_t pci_tolm;
  84
  85         pci_tolm = find_pci_tolm(&dev->link[0]);
  86         mc_dev = dev->link[0].children;
  87         if (mc_dev) {
  88                 uint16_t tolm_r;
  89                 unsigned long tomk, tolmk;
  90                 int idx;
  91
  92                 /* Figure out which areas are/should be occupied by RAM. The
  93                  * value of the highest DRB denotes the end of the physical
  94                  * memory (in units of 8MB).
  95                  */
  96                 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
  97
  98                 /* Convert to KB. */
  99                 tomk *= (8 * 1024);
 100
 101                 printk_debug("Setting RAM size to %d MB\n", tomk / 1024);
 102
 103                 /* Compute the top of low memory. */
 104                 tolmk = pci_tolm / 1024;
 105
 106                 if (tolmk >= tomk) {
 107                         /* The PCI hole does not overlap the memory. */
 108                         tolmk = tomk;
 109                 }
 110
 111                 /* Report the memory regions. */
 112                 idx = 10;
 113                 ram_resource(dev, idx++, 0, 640);
 114                 ram_resource(dev, idx++, 768, tolmk - 768);
 115
 116 #if CONFIG_WRITE_HIGH_TABLES==1
 117                 /* Leave some space for ACPI, PIRQ and MP tables */
 118                 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
 119                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 120 #endif
 121         }
 122         assign_resources(&dev->link[0]);
 123 }
 124
 125 static struct device_operations pci_domain_ops = {
 126         .read_resources         = pci_domain_read_resources,
 127         .set_resources          = i440bx_domain_set_resources,
 128         .enable_resources       = enable_childrens_resources,
 129         .init                   = 0,
 130         .scan_bus               = pci_domain_scan_bus,
 131 };
 132
 133 static void cpu_bus_init(device_t dev)
 134 {
 135         initialize_cpus(&dev->link[0]);
 136 }
 137
 138 static void cpu_bus_noop(device_t dev)
 139 {
 140 }
 141
 142 static struct device_operations cpu_bus_ops = {
 143         .read_resources   = cpu_bus_noop,
 144         .set_resources    = cpu_bus_noop,
 145         .enable_resources = cpu_bus_noop,
 146         .init             = cpu_bus_init,
 147         .scan_bus         = 0,
 148 };
 149
 150 static void enable_dev(struct device *dev)
 151 {
 152         /* Set the operations if it is a special bus type */
 153         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 154                 dev->ops = &pci_domain_ops;
 155                 pci_set_method(dev);
 156         }
 157         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 158                 dev->ops = &cpu_bus_ops;
 159         }
 160 }
 161
 162 struct chip_operations northbridge_intel_i440bx_ops = {
 163         CHIP_NAME("Intel 82443BX (440BX) Northbridge")
 164         .enable_dev = enable_dev,
 165 };