src/northbridge/intel/i3100/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 /* This code is based on src/northbridge/intel/e7520/northbridge.c */
  22
  23 #include <console/console.h>
  24 #include <arch/io.h>
  25 #include <stdint.h>
  26 #include <device/device.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/hypertransport.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <bitops.h>
  33 #include <cpu/cpu.h>
  34 #include "chip.h"
  35 #include "i3100.h"
  36
  37
  38 static u32 max_bus;
  39
  40 #if CONFIG_WRITE_HIGH_TABLES==1
  41 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  42 extern uint64_t high_tables_base, high_tables_size;
  43 #endif
  44
  45 static void pci_domain_set_resources(device_t dev)
  46 {
  47         device_t mc_dev;
  48         u32 pci_tolm;
  49
  50         pci_tolm = find_pci_tolm(dev->link_list);
  51
  52 #if 1
  53         printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
  54 #endif
  55         /* FIXME Me temporary hack */
  56         if(pci_tolm > 0xe0000000)
  57                 pci_tolm = 0xe0000000;
  58         /* Ensure pci_tolm is 128M aligned */
  59         pci_tolm &= 0xf8000000;
  60         mc_dev = dev->link_list->children;
  61         if (mc_dev) {
  62                 /* Figure out which areas are/should be occupied by RAM.
  63                  * This is all computed in kilobytes and converted to/from
  64                  * the memory controller right at the edges.
  65                  * Having different variables in different units is
  66                  * too confusing to get right.  Kilobytes are good up to
  67                  * 4 Terabytes of RAM...
  68                  */
  69                 u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
  70                 u32 tomk, tolmk;
  71                 u32 remapbasek, remaplimitk, remapoffsetk;
  72
  73                 /* Get the Top of Memory address, units are 128M */
  74                 tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
  75                 /* Compute the Top of Low Memory */
  76                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
  77
  78                 if (tolmk >= tomk) {
  79                         /* The PCI hole does not overlap memory
  80                          * we won't use the remap window.
  81                          */
  82                         tolmk = tomk;
  83                         remapbasek   = 0x3ff << 16;
  84                         remaplimitk  = 0 << 16;
  85                         remapoffsetk = 0 << 16;
  86                 }
  87                 else {
  88                         /* The PCI memory hole overlaps memory
  89                          * setup the remap window.
  90                          */
  91                         /* Find the bottom of the remap window
  92                          * is it above 4G?
  93                          */
  94                         remapbasek = 4*1024*1024;
  95                         if (tomk > remapbasek) {
  96                                 remapbasek = tomk;
  97                         }
  98                         /* Find the limit of the remap window */
  99                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 100                         /* Find the offset of the remap window from tolm */
 101                         remapoffsetk = remapbasek - tolmk;
 102                 }
 103                 /* Write the ram configruation registers,
 104                  * preserving the reserved bits.
 105                  */
 106                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 107                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 108                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 109
 110                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 111                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 112                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 113
 114                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 115                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 116                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 117
 118                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
 119                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
 120                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 121
 122                 /* Report the memory regions */
 123                 ram_resource(dev, 3,   0, 640);
 124                 ram_resource(dev, 4, 768, (tolmk - 768));
 125                 if (tomk > 4*1024*1024) {
 126                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 127                 }
 128                 if (remaplimitk >= remapbasek) {
 129                         ram_resource(dev, 6, remapbasek,
 130                                 (remaplimitk + 64*1024) - remapbasek);
 131                 }
 132
 133 #if CONFIG_WRITE_HIGH_TABLES==1
 134                 /* Leave some space for ACPI, PIRQ and MP tables */
 135                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 136                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 137 #endif
 138         }
 139         assign_resources(dev->link_list);
 140 }
 141
 142 static u32 i3100_domain_scan_bus(device_t dev, u32 max)
 143 {
 144         max_bus = pci_domain_scan_bus(dev, max);
 145         return max_bus;
 146 }
 147
 148 static struct device_operations pci_domain_ops = {
 149         .read_resources   = pci_domain_read_resources,
 150         .set_resources    = pci_domain_set_resources,
 151         .enable_resources = NULL,
 152         .init             = NULL,
 153         .scan_bus         = i3100_domain_scan_bus,
 154         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 155 };
 156
 157 static void mc_read_resources(device_t dev)
 158 {
 159         struct resource *resource;
 160
 161         pci_dev_read_resources(dev);
 162
 163         resource = new_resource(dev, 0xcf);
 164         resource->base = 0xe0000000;
 165         resource->size = max_bus * 4096*256;
 166         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 167 }
 168
 169 static void mc_set_resources(device_t dev)
 170 {
 171         struct resource *resource;
 172
 173         resource = find_resource(dev, 0xcf);
 174         if (resource) {
 175                 report_resource_stored(dev, resource, "<mmconfig>");
 176         }
 177         pci_dev_set_resources(dev);
 178 }
 179
 180 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 181 {
 182         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 183                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 184 }
 185
 186 static struct pci_operations intel_pci_ops = {
 187         .set_subsystem = intel_set_subsystem,
 188 };
 189
 190 static struct device_operations mc_ops = {
 191         .read_resources   = mc_read_resources,
 192         .set_resources    = mc_set_resources,
 193         .enable_resources = pci_dev_enable_resources,
 194         .init             = 0,
 195         .scan_bus         = 0,
 196         .ops_pci          = &intel_pci_ops,
 197 };
 198
 199 static const struct pci_driver mc_driver __pci_driver = {
 200         .ops = &mc_ops,
 201         .vendor = PCI_VENDOR_ID_INTEL,
 202         .device = PCI_DEVICE_ID_INTEL_3100_MC,
 203 };
 204
 205 static void cpu_bus_init(device_t dev)
 206 {
 207         initialize_cpus(dev->link_list);
 208 }
 209
 210 static void cpu_bus_noop(device_t dev)
 211 {
 212 }
 213
 214 static struct device_operations cpu_bus_ops = {
 215         .read_resources   = cpu_bus_noop,
 216         .set_resources    = cpu_bus_noop,
 217         .enable_resources = cpu_bus_noop,
 218         .init             = cpu_bus_init,
 219         .scan_bus         = 0,
 220 };
 221
 222
 223 static void enable_dev(device_t dev)
 224 {
 225         /* Set the operations if it is a special bus type */
 226         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 227                 dev->ops = &pci_domain_ops;
 228         }
 229         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 230                 dev->ops = &cpu_bus_ops;
 231         }
 232 }
 233
 234 struct chip_operations northbridge_intel_i3100_ops = {
 235         CHIP_NAME("Intel 3100 Northbridge")
 236         .enable_dev = enable_dev,
 237 };