src/northbridge/intel/i3100/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 /* This code is based on src/northbridge/intel/e7520/northbridge.c */
  22
  23 #include <console/console.h>
  24 #include <arch/io.h>
  25 #include <stdint.h>
  26 #include <device/device.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/hypertransport.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <bitops.h>
  33 #include <cpu/cpu.h>
  34 #include "chip.h"
  35 #include "i3100.h"
  36
  37
  38 static u32 max_bus;
  39
  40 static void ram_resource(device_t dev, u32 index,
  41         u32 basek, u32 sizek)
  42 {
  43         struct resource *resource;
  44
  45         resource = new_resource(dev, index);
  46         resource->base  = ((resource_t)basek) << 10;
  47         resource->size  = ((resource_t)sizek) << 10;
  48         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  49                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  50 }
  51
  52 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  53 {
  54         struct resource **best_p = gp;
  55         struct resource *best;
  56         best = *best_p;
  57         if (!best || (best->base > new->base)) {
  58                 best = new;
  59         }
  60         *best_p = best;
  61 }
  62
  63 static u32 find_pci_tolm(struct bus *bus)
  64 {
  65         struct resource *min;
  66         u32 tolm;
  67         min = 0;
  68         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  69         tolm = 0xffffffffUL;
  70         if (min && tolm > min->base) {
  71                 tolm = min->base;
  72         }
  73         return tolm;
  74 }
  75
  76 #if CONFIG_WRITE_HIGH_TABLES==1
  77 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  78 extern uint64_t high_tables_base, high_tables_size;
  79 #endif
  80
  81 static void pci_domain_set_resources(device_t dev)
  82 {
  83         device_t mc_dev;
  84         u32 pci_tolm;
  85
  86         pci_tolm = find_pci_tolm(dev->link_list);
  87
  88 #if 1
  89         printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
  90 #endif
  91         /* FIXME Me temporary hack */
  92         if(pci_tolm > 0xe0000000)
  93                 pci_tolm = 0xe0000000;
  94         /* Ensure pci_tolm is 128M aligned */
  95         pci_tolm &= 0xf8000000;
  96         mc_dev = dev->link_list->children;
  97         if (mc_dev) {
  98                 /* Figure out which areas are/should be occupied by RAM.
  99                  * This is all computed in kilobytes and converted to/from
 100                  * the memory controller right at the edges.
 101                  * Having different variables in different units is
 102                  * too confusing to get right.  Kilobytes are good up to
 103                  * 4 Terabytes of RAM...
 104                  */
 105                 u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
 106                 u32 tomk, tolmk;
 107                 u32 remapbasek, remaplimitk, remapoffsetk;
 108
 109                 /* Get the Top of Memory address, units are 128M */
 110                 tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
 111                 /* Compute the Top of Low Memory */
 112                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
 113
 114                 if (tolmk >= tomk) {
 115                         /* The PCI hole does not overlap memory
 116                          * we won't use the remap window.
 117                          */
 118                         tolmk = tomk;
 119                         remapbasek   = 0x3ff << 16;
 120                         remaplimitk  = 0 << 16;
 121                         remapoffsetk = 0 << 16;
 122                 }
 123                 else {
 124                         /* The PCI memory hole overlaps memory
 125                          * setup the remap window.
 126                          */
 127                         /* Find the bottom of the remap window
 128                          * is it above 4G?
 129                          */
 130                         remapbasek = 4*1024*1024;
 131                         if (tomk > remapbasek) {
 132                                 remapbasek = tomk;
 133                         }
 134                         /* Find the limit of the remap window */
 135                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 136                         /* Find the offset of the remap window from tolm */
 137                         remapoffsetk = remapbasek - tolmk;
 138                 }
 139                 /* Write the ram configruation registers,
 140                  * preserving the reserved bits.
 141                  */
 142                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 143                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 144                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 145
 146                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 147                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 148                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 149
 150                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 151                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 152                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 153
 154                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
 155                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
 156                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 157
 158                 /* Report the memory regions */
 159                 ram_resource(dev, 3,   0, 640);
 160                 ram_resource(dev, 4, 768, (tolmk - 768));
 161                 if (tomk > 4*1024*1024) {
 162                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 163                 }
 164                 if (remaplimitk >= remapbasek) {
 165                         ram_resource(dev, 6, remapbasek,
 166                                 (remaplimitk + 64*1024) - remapbasek);
 167                 }
 168
 169 #if CONFIG_WRITE_HIGH_TABLES==1
 170                 /* Leave some space for ACPI, PIRQ and MP tables */
 171                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 172                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 173 #endif
 174         }
 175         assign_resources(dev->link_list);
 176 }
 177
 178 static u32 i3100_domain_scan_bus(device_t dev, u32 max)
 179 {
 180         max_bus = pci_domain_scan_bus(dev, max);
 181         return max_bus;
 182 }
 183
 184 static struct device_operations pci_domain_ops = {
 185         .read_resources   = pci_domain_read_resources,
 186         .set_resources    = pci_domain_set_resources,
 187         .enable_resources = NULL,
 188         .init             = NULL,
 189         .scan_bus         = i3100_domain_scan_bus,
 190         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 191 };
 192
 193 static void mc_read_resources(device_t dev)
 194 {
 195         struct resource *resource;
 196
 197         pci_dev_read_resources(dev);
 198
 199         resource = new_resource(dev, 0xcf);
 200         resource->base = 0xe0000000;
 201         resource->size = max_bus * 4096*256;
 202         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 203 }
 204
 205 static void mc_set_resources(device_t dev)
 206 {
 207         struct resource *resource;
 208
 209         resource = find_resource(dev, 0xcf);
 210         if (resource) {
 211                 report_resource_stored(dev, resource, "<mmconfig>");
 212         }
 213         pci_dev_set_resources(dev);
 214 }
 215
 216 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 217 {
 218         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 219                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 220 }
 221
 222 static struct pci_operations intel_pci_ops = {
 223         .set_subsystem = intel_set_subsystem,
 224 };
 225
 226 static struct device_operations mc_ops = {
 227         .read_resources   = mc_read_resources,
 228         .set_resources    = mc_set_resources,
 229         .enable_resources = pci_dev_enable_resources,
 230         .init             = 0,
 231         .scan_bus         = 0,
 232         .ops_pci          = &intel_pci_ops,
 233 };
 234
 235 static const struct pci_driver mc_driver __pci_driver = {
 236         .ops = &mc_ops,
 237         .vendor = PCI_VENDOR_ID_INTEL,
 238         .device = PCI_DEVICE_ID_INTEL_3100_MC,
 239 };
 240
 241 static void cpu_bus_init(device_t dev)
 242 {
 243         initialize_cpus(dev->link_list);
 244 }
 245
 246 static void cpu_bus_noop(device_t dev)
 247 {
 248 }
 249
 250 static struct device_operations cpu_bus_ops = {
 251         .read_resources   = cpu_bus_noop,
 252         .set_resources    = cpu_bus_noop,
 253         .enable_resources = cpu_bus_noop,
 254         .init             = cpu_bus_init,
 255         .scan_bus         = 0,
 256 };
 257
 258
 259 static void enable_dev(device_t dev)
 260 {
 261         /* Set the operations if it is a special bus type */
 262         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 263                 dev->ops = &pci_domain_ops;
 264         }
 265         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 266                 dev->ops = &cpu_bus_ops;
 267         }
 268 }
 269
 270 struct chip_operations northbridge_intel_i3100_ops = {
 271         CHIP_NAME("Intel 3100 Northbridge")
 272         .enable_dev = enable_dev,
 273 };