src/northbridge/intel/e7525/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <stdlib.h>
  24 #include "raminit.h"
  25 #include "e7525.h"
  26
  27 #define BAR 0x40000000
  28
  29 static void sdram_set_registers(const struct mem_controller *ctrl)
  30 {
  31         static const unsigned int register_values[] = {
  32
  33                 /* CKDIS 0x8c disable clocks */
  34         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  35
  36                 /* 0x9c Device present and extended RAM control
  37                  * DEVPRES is very touchy, hard code the initialization
  38                  * of PCI-E ports here.
  39                  */
  40         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  41
  42                 /* 0xc8 Remap RAM base and limit off */
  43         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  44
  45                 /* ??? */
  46         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  47         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  48
  49                 /* 0x50 scrub */
  50         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  51
  52                 /* 0x58 0x5c PAM */
  53         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  54         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  55
  56                 /* 0xf4 */
  57         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  58
  59                 /* 0x14 */
  60         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
  61         };
  62         int i;
  63         int max;
  64
  65         max = ARRAY_SIZE(register_values);
  66         for(i = 0; i < max; i += 3) {
  67                 device_t dev;
  68                 unsigned where;
  69                 unsigned long reg;
  70                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  71                 where = register_values[i] & 0xff;
  72                 reg = pci_read_config32(dev, where);
  73                 reg &= register_values[i+1];
  74                 reg |= register_values[i+2];
  75                 pci_write_config32(dev, where, reg);
  76         }
  77         print_spew("done.\n");
  78 }
  79
  80
  81
  82 struct dimm_size {
  83         unsigned long side1;
  84         unsigned long side2;
  85 };
  86
  87 static struct dimm_size spd_get_dimm_size(unsigned device)
  88 {
  89         /* Calculate the log base 2 size of a DIMM in bits */
  90         struct dimm_size sz;
  91         int value, low, ddr2;
  92         sz.side1 = 0;
  93         sz.side2 = 0;
  94
  95         /* test for ddr2 */
  96         ddr2=0;
  97         value = spd_read_byte(device, 2);       /* type */
  98         if (value < 0) goto hw_err;
  99         if (value == 8) ddr2 = 1;
 100
 101         /* Note it might be easier to use byte 31 here, it has the DIMM size as
 102          * a multiple of 4MB.  The way we do it now we can size both
 103          * sides of an assymetric dimm.
 104          */
 105         value = spd_read_byte(device, 3);       /* rows */
 106         if (value < 0) goto hw_err;
 107         if ((value & 0xf) == 0) goto val_err;
 108         sz.side1 += value & 0xf;
 109
 110         value = spd_read_byte(device, 4);       /* columns */
 111         if (value < 0) goto hw_err;
 112         if ((value & 0xf) == 0) goto val_err;
 113         sz.side1 += value & 0xf;
 114
 115         value = spd_read_byte(device, 17);      /* banks */
 116         if (value < 0) goto hw_err;
 117         if ((value & 0xff) == 0) goto val_err;
 118         sz.side1 += log2(value & 0xff);
 119
 120         /* Get the module data width and convert it to a power of two */
 121         value = spd_read_byte(device, 7);       /* (high byte) */
 122         if (value < 0) goto hw_err;
 123         value &= 0xff;
 124         value <<= 8;
 125
 126         low = spd_read_byte(device, 6); /* (low byte) */
 127         if (low < 0) goto hw_err;
 128         value = value | (low & 0xff);
 129         if ((value != 72) && (value != 64)) goto val_err;
 130         sz.side1 += log2(value);
 131
 132         /* side 2 */
 133         value = spd_read_byte(device, 5);       /* number of physical banks */
 134
 135         if (value < 0) goto hw_err;
 136         value &= 7;
 137         if(ddr2) value++;
 138         if (value == 1) goto out;
 139         if (value != 2) goto val_err;
 140
 141         /* Start with the symmetrical case */
 142         sz.side2 = sz.side1;
 143
 144         value = spd_read_byte(device, 3);       /* rows */
 145         if (value < 0) goto hw_err;
 146         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 147         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 148         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 149
 150         value = spd_read_byte(device, 4);       /* columns */
 151         if (value < 0) goto hw_err;
 152         if ((value & 0xff) == 0) goto val_err;
 153         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 154         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columsn on side 2 */
 155         goto out;
 156
 157  val_err:
 158         die("Bad SPD value\n");
 159         /* If an hw_error occurs report that I have no memory */
 160 hw_err:
 161         sz.side1 = 0;
 162         sz.side2 = 0;
 163  out:
 164         return sz;
 165
 166 }
 167
 168 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 169 {
 170         int i;
 171         int cum;
 172
 173         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 174                 struct dimm_size sz;
 175                 if (dimm_mask & (1 << i)) {
 176                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 177                         if (sz.side1 < 29) {
 178                                 return -1; /* Report SPD error */
 179                         }
 180                         /* convert bits to multiples of 64MB */
 181                         sz.side1 -= 29;
 182                         cum += (1 << sz.side1);
 183                         /* DRB = 0x60 */
 184                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 185                         if( sz.side2 > 28) {
 186                                 sz.side2 -= 29;
 187                                 cum += (1 << sz.side2);
 188                         }
 189                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 190                 }
 191                 else {
 192                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 193                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 194                 }
 195         }
 196         /* set TOM top of memory 0xcc */
 197         pci_write_config16(ctrl->f0, TOM, cum);
 198         /* set TOLM top of low memory */
 199         if(cum > 0x18) {
 200                 cum = 0x18;
 201         }
 202         cum <<= 11;
 203         /* 0xc4 TOLM */
 204         pci_write_config16(ctrl->f0, TOLM, cum);
 205         return 0;
 206 }
 207
 208
 209 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 210 {
 211         unsigned dimm_mask;
 212         int i;
 213         dimm_mask = 0;
 214         for(i = 0; i < DIMM_SOCKETS; i++) {
 215                 int byte;
 216                 unsigned device;
 217                 device = ctrl->channel0[i];
 218                 if (device) {
 219                         byte = spd_read_byte(device, 2);  /* Type */
 220                         if ((byte == 7) || (byte == 8)) {
 221                                 dimm_mask |= (1 << i);
 222                         }
 223                 }
 224                 device = ctrl->channel1[i];
 225                 if (device) {
 226                         byte = spd_read_byte(device, 2);
 227                         if ((byte == 7) || (byte == 8)) {
 228                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 229                         }
 230                 }
 231         }
 232         return dimm_mask;
 233 }
 234
 235
 236 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 237                 long dimm_mask)
 238 {
 239
 240         int value;
 241         int reg;
 242         int dra;
 243         int cnt;
 244
 245         dra = 0;
 246         for(cnt=0; cnt < 4; cnt++) {
 247                 if (!(dimm_mask & (1 << cnt))) {
 248                         continue;
 249                 }
 250                 reg =0;
 251                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 252                 if (value < 0) goto hw_err;
 253                 if ((value & 0xf) == 0) goto val_err;
 254                 reg += value & 0xf;
 255
 256                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 257                 if (value < 0) goto hw_err;
 258                 if ((value & 0xf) == 0) goto val_err;
 259                 reg += value & 0xf;
 260
 261                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 262                 if (value < 0) goto hw_err;
 263                 if ((value & 0xff) == 0) goto val_err;
 264                 reg += log2(value & 0xff);
 265
 266                 /* Get the device width and convert it to a power of two */
 267                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 268                 if (value < 0) goto hw_err;
 269                 value = log2(value & 0xff);
 270                 reg += value;
 271                 if(reg < 27) goto hw_err;
 272                 reg -= 27;
 273                 reg += (value << 2);
 274
 275                 dra += reg << (cnt*8);
 276                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 277                 if (value & 2)
 278                         dra += reg << ((cnt*8)+4);
 279         }
 280
 281         /* 0x70 DRA */
 282         pci_write_config32(ctrl->f0, DRA, dra);
 283         goto out;
 284
 285  val_err:
 286         die("Bad SPD value\n");
 287         /* If an hw_error occurs report that I have no memory */
 288 hw_err:
 289         dra = 0;
 290  out:
 291         return dra;
 292
 293 }
 294
 295
 296 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 297                 long dimm_mask, uint32_t drc)
 298 {
 299         int value;
 300         int reg;
 301         uint32_t drt;
 302         int cnt;
 303         int first_dimm;
 304         int cas_latency=0;
 305         int latency;
 306         uint32_t index = 0;
 307         uint32_t index2 = 0;
 308         static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
 309         static const int latency_indicies[] = { 26, 23, 9 };
 310
 311         /* 0x78 DRT */
 312         drt = pci_read_config32(ctrl->f0, DRT);
 313         drt &= 3;  /* save bits 1:0 */
 314
 315         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 316                 if (dimm_mask & (1 << first_dimm))
 317                         break;
 318         }
 319
 320         /* get dimm type */
 321         value = spd_read_byte(ctrl->channel0[first_dimm], 2);
 322         if(value == 8) {
 323                 drt |= (3<<5); /* back to bark write turn around & cycle add */
 324         }
 325
 326         drt |= (3<<18);  /* Trasmax */
 327
 328         for(cnt=0; cnt < 4; cnt++) {
 329                 if (!(dimm_mask & (1 << cnt))) {
 330                         continue;
 331                 }
 332                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 333                 /* Compute the lowest cas latency supported */
 334                 latency = log2(reg) -2;
 335
 336                 /* Loop through and find a fast clock with a low latency */
 337                 for(index = 0; index < 3; index++, latency++) {
 338                         if ((latency < 2) || (latency > 4) ||
 339                                 (!(reg & (1 << latency)))) {
 340                                 continue;
 341                         }
 342                         value = spd_read_byte(ctrl->channel0[cnt],
 343                                         latency_indicies[index]);
 344
 345                         if(value <= cycle_time[drc&3]) {
 346                                 if( latency > cas_latency) {
 347                                         cas_latency = latency;
 348                                 }
 349                                 break;
 350                         }
 351                 }
 352         }
 353         index = (cas_latency-2);
 354         if((index)==0) cas_latency = 20;
 355         else if((index)==1) cas_latency = 25;
 356         else cas_latency = 30;
 357
 358         for(cnt=0;cnt<4;cnt++) {
 359                 if (!(dimm_mask & (1 << cnt))) {
 360                         continue;
 361                 }
 362                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 363                 if(((index>>8)&0x0ff)<reg) {
 364                         index &= ~(0x0ff << 8);
 365                         index |= (reg << 8);
 366                 }
 367                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 368                 if(((index>>16)&0x0ff)<reg) {
 369                         index &= ~(0x0ff << 16);
 370                         index |= (reg<<16);
 371                 }
 372                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 373                 if(((index2>>0)&0x0ff)<reg) {
 374                         index2 &= ~(0x0ff << 0);
 375                         index2 |= (reg<<0);
 376                 }
 377                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 378                 if(((index2>>8)&0x0ff)<reg) {
 379                         index2 &= ~(0x0ff << 8);
 380                         index2 |= (reg<<8);
 381                 }
 382                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 383                 if(((index2>>16)&0x0ff)<reg) {
 384                         index2 &= ~(0x0ff << 16);
 385                         index2 |= (reg<<16);
 386                 }
 387         }
 388
 389         /* get dimm speed */
 390         value = cycle_time[drc&3];
 391         if(value <= 0x50) {  /* 200 MHz */
 392                 if((index&7) > 2) {
 393                         drt |= (2<<2);  /* CAS latency 4 */
 394                         cas_latency = 40;
 395                 } else {
 396                         drt |= (1<<2);  /* CAS latency 3 */
 397                         cas_latency = 30;
 398                 }
 399                 if((index&0x0ff00)<=0x03c00) {
 400                         drt |= (1<<8);  /* Trp RAS Precharg */
 401                 } else {
 402                         drt |= (2<<8);  /* Trp RAS Precharg */
 403                 }
 404
 405                 /* Trcd RAS to CAS delay */
 406                 if((index2&0x0ff)<=0x03c) {
 407                         drt |= (0<<10);
 408                 } else {
 409                         drt |= (1<<10);
 410                 }
 411
 412                 /* Tdal Write auto precharge recovery delay */
 413                 drt |= (1<<12);
 414
 415                 /* Trc TRS min */
 416                 if((index2&0x0ff00)<=0x03700)
 417                         drt |= (0<<14);
 418                 else if((index2&0xff00)<=0x03c00)
 419                         drt |= (1<<14);
 420                 else
 421                         drt |= (2<<14); /* spd 41 */
 422
 423                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 424
 425                 /* Trrd Row Delay */
 426                 if((index&0x0ff0000)<=0x0140000) {
 427                         drt |= (0<<20);
 428                 } else if((index&0x0ff0000)<=0x0280000) {
 429                         drt |= (1<<20);
 430                 } else if((index&0x0ff0000)<=0x03c0000) {
 431                         drt |= (2<<20);
 432                 } else {
 433                         drt |= (3<<20);
 434                 }
 435
 436                 /* Trfc Auto refresh cycle time */
 437                 if((index2&0x0ff0000)<=0x04b0000) {
 438                         drt |= (0<<22);
 439                 } else if((index2&0x0ff0000)<=0x0690000) {
 440                         drt |= (1<<22);
 441                 } else {
 442                         drt |= (2<<22);
 443                 }
 444                 /* Docs say use 55 for all 200Mhz */
 445                 drt |= (0x055<<24);
 446         }
 447         else if(value <= 0x60) { /* 167 Mhz */
 448                 /* according to new documentation CAS latency is 00
 449                  * for bits 3:2 for all 167 Mhz
 450                 drt |= ((index&3)<<2); */  /* set CAS latency */
 451                 if((index&0x0ff00)<=0x03000) {
 452                         drt |= (1<<8);  /* Trp RAS Precharg */
 453                 } else {
 454                         drt |= (2<<8);  /* Trp RAS Precharg */
 455                 }
 456
 457                 /* Trcd RAS to CAS delay */
 458                 if((index2&0x0ff)<=0x030) {
 459                         drt |= (0<<10);
 460                 } else {
 461                         drt |= (1<<10);
 462                 }
 463
 464                 /* Tdal Write auto precharge recovery delay */
 465                 drt |= (2<<12);
 466
 467                 /* Trc TRS min */
 468                 drt |= (2<<14); /* spd 41, but only one choice */
 469
 470                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 471
 472                 /* Trrd Row Delay */
 473                 if((index&0x0ff0000)<=0x0180000) {
 474                         drt |= (0<<20);
 475                 } else if((index&0x0ff0000)<=0x0300000) {
 476                         drt |= (1<<20);
 477                 } else {
 478                         drt |= (2<<20);
 479                 }
 480
 481                 /* Trfc Auto refresh cycle time */
 482                 if((index2&0x0ff0000)<=0x0480000) {
 483                         drt |= (0<<22);
 484                 } else if((index2&0x0ff0000)<=0x0780000) {
 485                         drt |= (2<<22);
 486                 } else {
 487                         drt |= (2<<22);
 488                 }
 489                 /* Docs state to use 99 for all 167 Mhz */
 490                 drt |= (0x099<<24);
 491         }
 492         else if(value <= 0x75) { /* 133 Mhz */
 493                 drt |= ((index&3)<<2);  /* set CAS latency */
 494                 if((index&0x0ff00)<=0x03c00) {
 495                         drt |= (1<<8);  /* Trp RAS Precharg */
 496                 } else {
 497                         drt |= (2<<8);  /* Trp RAS Precharg */
 498                 }
 499
 500                 /* Trcd RAS to CAS delay */
 501                 if((index2&0x0ff)<=0x03c) {
 502                         drt |= (0<<10);
 503                 } else {
 504                         drt |= (1<<10);
 505                 }
 506
 507                 /* Tdal Write auto precharge recovery delay */
 508                 drt |= (1<<12);
 509
 510                 /* Trc TRS min */
 511                 drt |= (2<<14); /* spd 41, but only one choice */
 512
 513                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 514
 515                 /* Trrd Row Delay */
 516                 if((index&0x0ff0000)<=0x01e0000) {
 517                         drt |= (0<<20);
 518                 } else if((index&0x0ff0000)<=0x03c0000) {
 519                         drt |= (1<<20);
 520                 } else {
 521                         drt |= (2<<20);
 522                 }
 523
 524                 /* Trfc Auto refresh cycle time */
 525                 if((index2&0x0ff0000)<=0x04b0000) {
 526                         drt |= (0<<22);
 527                 } else if((index2&0x0ff0000)<=0x0780000) {
 528                         drt |= (2<<22);
 529                 } else {
 530                         drt |= (2<<22);
 531                 }
 532
 533                 /* Based on CAS latency */
 534                 if(index&7)
 535                         drt |= (0x099<<24);
 536                 else
 537                         drt |= (0x055<<24);
 538
 539         }
 540         else {
 541                 die("Invalid SPD 9 bus speed.\n");
 542         }
 543
 544         /* 0x78 DRT */
 545         pci_write_config32(ctrl->f0, DRT, drt);
 546
 547         return(cas_latency);
 548 }
 549
 550 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 551                 long dimm_mask)
 552 {
 553         int value;
 554         int reg;
 555         int drc;
 556         int cnt;
 557         msr_t msr;
 558         unsigned char dram_type = 0xff;
 559         unsigned char ecc = 0xff;
 560         unsigned char rate = 62;
 561         static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
 562         static const unsigned char drc_rates[5] = {0,15,7,62,3};
 563         static const unsigned char fsb_conversion[4] = {3,1,3,2};
 564
 565         /* 0x7c DRC */
 566         drc = pci_read_config32(ctrl->f0, DRC);
 567         for(cnt=0; cnt < 4; cnt++) {
 568                 if (!(dimm_mask & (1 << cnt))) {
 569                         continue;
 570                 }
 571                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 572                 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
 573                 if (value == 2) {    /* RAM is ECC capable */
 574                         if (reg == 8) {
 575                                 if ( ecc == 0xff ) {
 576                                         ecc = 2;
 577                                 }
 578                                 else if (ecc == 1) {
 579                                         die("ERROR - Mixed DDR & DDR2 RAM\n");
 580                                 }
 581                         }
 582                         else if ( reg == 7 ) {
 583                                 if ( ecc == 0xff) {
 584                                         ecc = 1;
 585                                 }
 586                                 else if ( ecc > 1 ) {
 587                                         die("ERROR - Mixed DDR & DDR2 RAM\n");
 588                                 }
 589                         }
 590                         else {
 591                                 die("ERROR - RAM not DDR\n");
 592                         }
 593                 }
 594                 else {
 595                         die("ERROR - Non ECC memory dimm\n");
 596                 }
 597
 598                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 599                 value &= 0x0f;    /* clip self refresh bit */
 600                 if (value > 5) goto hw_err;
 601                 if (rate > spd_rates[value])
 602                         rate = spd_rates[value];
 603
 604                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 605                 if (value > 0x75) goto hw_err;
 606                 if (value <= 0x50) {
 607                         if (dram_type >= 2) {
 608                                 if (reg == 8) { /*speed is good, is this ddr2?*/
 609                                         dram_type = 2;
 610                                 } else { /* not ddr2 so use ddr333 */
 611                                         dram_type = 1;
 612                                 }
 613                         }
 614                 }
 615                 else if (value <= 0x60) {
 616                         if (dram_type >= 1)  dram_type = 1;
 617                 }
 618                 else dram_type = 0; /* ddr266 */
 619
 620         }
 621         ecc = 2;
 622         if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 623                 ecc = 0;  /* ECC off in CMOS so disable it */
 624                 print_debug("ECC off\n");
 625         }
 626         else {
 627                 print_debug("ECC on\n");
 628         }
 629         drc &= ~(3 << 20); /* clear the ecc bits */
 630         drc |= (ecc << 20);  /* or in the calculated ecc bits */
 631         for ( cnt = 1; cnt < 5; cnt++)
 632                 if (drc_rates[cnt] == rate)
 633                         break;
 634         if (cnt < 5) {
 635                 drc &= ~(7 << 8);  /* clear the rate bits */
 636                 drc |= (cnt << 8);
 637         }
 638
 639         if (reg == 8) { /* independant clocks */
 640                 drc |= (1 << 4);
 641         }
 642
 643         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 644         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 645         /* front side bus */
 646         msr = rdmsr(0x2c);
 647         value = msr.lo >> 16;
 648         value &= 0x03;
 649         drc &= ~(3 << 2); /* set the front side bus */
 650         drc |= (fsb_conversion[value] << 2);
 651         drc &= ~(3 << 0); /* set the dram type */
 652         drc |= (dram_type << 0);
 653
 654         goto out;
 655
 656  val_err:
 657         die("Bad SPD value\n");
 658         /* If an hw_error occurs report that I have no memory */
 659 hw_err:
 660         drc = 0;
 661  out:
 662         return drc;
 663 }
 664
 665 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 666 {
 667         long dimm_mask;
 668
 669         /* Test if we can read the spd and if ram is ddr or ddr2 */
 670         dimm_mask = spd_detect_dimms(ctrl);
 671         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 672                 print_err("No memory for this cpu\n");
 673                 return;
 674         }
 675         return;
 676 }
 677
 678 static void do_delay(void)
 679 {
 680         int i;
 681         unsigned char b;
 682         for(i=0;i<16;i++)
 683                 b=inb(0x80);
 684 }
 685
 686 #define TIMEOUT_LOOPS 300000
 687
 688 #define DCALCSR  0x100
 689 #define DCALADDR 0x104
 690 #define DCALDATA 0x108
 691
 692 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 693 {
 694         unsigned char c1,c2;
 695         unsigned int dimm,i;
 696         unsigned int data32;
 697         unsigned int t4;
 698
 699         /* Set up northbridge values */
 700         /* ODT enable */
 701         pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
 702         /* Figure out which slots are Empty, Single, or Double sided */
 703         for(i=0,t4=0,c2=0;i<8;i+=2) {
 704                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 705                 if(c1 == c2) continue;
 706                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 707                 if(c1 == c2)
 708                         t4 |= (1 << (i*4));
 709                 else
 710                         t4 |= (2 << (i*4));
 711         }
 712         for(i=0;i<1;i++) {
 713             if((t4&0x0f) == 1) {
 714                 if( ((t4>>8)&0x0f) == 0 ) {
 715                         data32 = 0x00000010; /* EEES */
 716                         break;
 717                 }
 718                 if ( ((t4>>16)&0x0f) == 0 ) {
 719                         data32 = 0x00003132; /* EESS */
 720                         break;
 721                 }
 722                 if ( ((t4>>24)&0x0f)  == 0 ) {
 723                         data32 = 0x00335566; /* ESSS */
 724                         break;
 725                 }
 726                 data32 = 0x77bbddee; /* SSSS */
 727                 break;
 728             }
 729             if((t4&0x0f) == 2) {
 730                 if( ((t4>>8)&0x0f) == 0 ) {
 731                         data32 = 0x00003132; /* EEED */
 732                         break;
 733                 }
 734                 if ( ((t4>>8)&0x0f) == 2 ) {
 735                         data32 = 0xb373ecdc; /* EEDD */
 736                         break;
 737                 }
 738                 if ( ((t4>>16)&0x0f) == 0 ) {
 739                         data32 = 0x00b3a898; /* EESD */
 740                         break;
 741                 }
 742                 data32 = 0x777becdc; /* ESSD */
 743                 break;
 744             }
 745             die("Error - First dimm slot empty\n");
 746         }
 747
 748         print_debug("ODT Value = ");
 749         print_debug_hex32(data32);
 750         print_debug("\n");
 751
 752         pci_write_config32(ctrl->f0, 0xb0, data32);
 753
 754         for(dimm=0;dimm<8;dimm+=1) {
 755
 756                 write32(BAR+DCALADDR, 0x0b840001);
 757                 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
 758
 759                 for(i=0;i<1001;i++) {
 760                         data32 = read32(BAR+DCALCSR);
 761                         if(!(data32 & (1<<31)))
 762                                 break;
 763                 }
 764         }
 765 }
 766 static void set_receive_enable(const struct mem_controller *ctrl)
 767 {
 768         unsigned int i;
 769         unsigned int cnt,bit;
 770         uint32_t recena=0;
 771         uint32_t recenb=0;
 772
 773         {
 774         unsigned int dimm;
 775         unsigned int edge;
 776         int32_t data32;
 777         uint32_t data32_dram;
 778         uint32_t dcal_data32_0;
 779         uint32_t dcal_data32_1;
 780         uint32_t dcal_data32_2;
 781         uint32_t dcal_data32_3;
 782         uint32_t work32l;
 783         uint32_t work32h;
 784         uint32_t data32r;
 785         int32_t recen;
 786         for(dimm=0;dimm<8;dimm+=1) {
 787
 788                 if(!(dimm&1)) {
 789                         write32(BAR+DCALDATA+(17*4), 0x04020000);
 790                         write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
 791
 792                         for(i=0;i<1001;i++) {
 793                                 data32 = read32(BAR+DCALCSR);
 794                                 if(!(data32 & (1<<31)))
 795                                         break;
 796                         }
 797                         if(i>=1000)
 798                                 continue;
 799
 800                         dcal_data32_0 = read32(BAR+DCALDATA + 0);
 801                         dcal_data32_1 = read32(BAR+DCALDATA + 4);
 802                         dcal_data32_2 = read32(BAR+DCALDATA + 8);
 803                         dcal_data32_3 = read32(BAR+DCALDATA + 12);
 804                 }
 805                 else {
 806                         dcal_data32_0 = read32(BAR+DCALDATA + 16);
 807                         dcal_data32_1 = read32(BAR+DCALDATA + 20);
 808                         dcal_data32_2 = read32(BAR+DCALDATA + 24);
 809                         dcal_data32_3 = read32(BAR+DCALDATA + 28);
 810                 }
 811
 812                 /* check if bank is installed */
 813                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 814                         continue;
 815                 /* Calculate the timing value */
 816                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 817                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 818                                 (i<4) && bit; i++) {
 819                         for(;;bit--,cnt--) {
 820                                 if(work32l & (1<<cnt))
 821                                         break;
 822                                 if(!cnt) {
 823                                         work32l = dcal_data32_0;
 824                                         work32h = dcal_data32_2;
 825                                         cnt = 32;
 826                                 }
 827                                 if(!bit) break;
 828                         }
 829                         for(;;bit--,cnt--) {
 830                                 if(!(work32l & (1<<cnt)))
 831                                         break;
 832                                 if(!cnt) {
 833                                         work32l = dcal_data32_0;
 834                                         work32h = dcal_data32_2;
 835                                         cnt = 32;
 836                                 }
 837                                 if(!bit) break;
 838                         }
 839                         if(!bit) {
 840                                 break;
 841                         }
 842                         data32 = ((bit%8) << 1);
 843                         if(work32h & (1<<cnt))
 844                                 data32 += 1;
 845                         if(data32 < 4) {
 846                                 if(!edge) {
 847                                         edge = 1;
 848                                 }
 849                                 else {
 850                                         if(edge != 1) {
 851                                                 data32 = 0x0f;
 852                                         }
 853                                 }
 854                         }
 855                         if(data32 > 12) {
 856                                 if(!edge) {
 857                                         edge = 2;
 858                                 }
 859                                 else {
 860                                         if(edge != 2) {
 861                                                 data32 = 0x00;
 862                                         }
 863                                 }
 864                         }
 865                         data32r += data32;
 866                 }
 867
 868                 work32l = dcal_data32_0;
 869                 work32h = dcal_data32_2;
 870                 recen = data32r;
 871                 recen += 3;
 872                 recen = recen>>2;
 873                 for(cnt=5;cnt<24;) {
 874                         for(;;cnt++)
 875                                 if(!(work32l & (1<<cnt)))
 876                                         break;
 877                         for(;;cnt++) {
 878                                 if(work32l & (1<<cnt))
 879                                         break;
 880                         }
 881                         data32 = (((cnt-1)%8)<<1);
 882                         if(work32h & (1<<(cnt-1))) {
 883                                 data32++;
 884                         }
 885                         /* test for frame edge cross overs */
 886                         if((edge == 1) && (data32 > 12) &&
 887                             (((recen+16)-data32) < 3)) {
 888                                 data32 = 0;
 889                                 cnt += 2;
 890                         }
 891                         if((edge == 2) && (data32 < 4) &&
 892                             ((recen - data32) > 12))  {
 893                                 data32 = 0x0f;
 894                                 cnt -= 2;
 895                         }
 896                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 897                                 break;
 898                 }
 899                 cnt--;
 900                 cnt /= 8;
 901                 cnt--;
 902                 if(recen&1)
 903                         recen+=2;
 904                 recen >>= 1;
 905                 recen += (cnt*8);
 906         recen+=2;
 907                 recen <<= (dimm/2) * 8;
 908                 if(!(dimm&1)) {
 909                         recena |= recen;
 910                 }
 911                 else {
 912                         recenb |= recen;
 913                 }
 914         }
 915         }
 916         /* Check for Eratta problem */
 917         for(i=cnt=bit=0;i<4;i++) {
 918                 if (((recena>>(i*8))&0x0f)>7) {
 919                         cnt++; bit++;
 920                 }
 921                 else {
 922                         if((recena>>(i*8))&0x0f) {
 923                                 cnt++;
 924                         }
 925                 }
 926         }
 927         if(bit) {
 928                 cnt-=bit;
 929                 if(cnt>1) {
 930                         for(i=0;i<4;i++) {
 931                                 if(((recena>>(i*8))&0x0f)>7) {
 932                                         recena &= ~(0x0f<<(i*8));
 933                                         recena |= (7<<(i*8));
 934                                 }
 935                         }
 936                 }
 937                 else {
 938                         for(i=0;i<4;i++) {
 939                                 if(((recena>>(i*8))&0x0f)<8) {
 940                                         recena &= ~(0x0f<<(i*8));
 941                                         recena |= (8<<(i*8));
 942                                 }
 943                         }
 944                 }
 945         }
 946         for(i=cnt=bit=0;i<4;i++) {
 947                 if (((recenb>>(i*8))&0x0f)>7) {
 948                         cnt++; bit++;
 949                 }
 950                 else {
 951                         if((recenb>>(i*8))&0x0f) {
 952                                 cnt++;
 953                         }
 954                 }
 955         }
 956         if(bit) {
 957                 cnt-=bit;
 958                 if(cnt>1) {
 959                         for(i=0;i<4;i++) {
 960                                 if(((recenb>>(i*8))&0x0f)>7) {
 961                                         recenb &= ~(0x0f<<(i*8));
 962                                         recenb |= (7<<(i*8));
 963                                 }
 964                         }
 965                 }
 966                 else {
 967                         for(i=0;i<4;i++) {
 968                                 if(((recenb>>(i*8))&0x0f)<8) {
 969                                         recenb &= ~(0x0f<<(i*8));
 970                                         recenb |= (8<<(i*8));
 971                                 }
 972                         }
 973                 }
 974         }
 975
 976 //  recena = 0x0000090a;
 977 //  recenb = 0x0000090a;
 978
 979         print_debug("Receive enable A = ");
 980         print_debug_hex32(recena);
 981         print_debug(",  Receive enable B = ");
 982         print_debug_hex32(recenb);
 983         print_debug("\n");
 984
 985         /* clear out the calibration area */
 986         write32(BAR+DCALDATA+(16*4), 0x00000000);
 987         write32(BAR+DCALDATA+(17*4), 0x00000000);
 988         write32(BAR+DCALDATA+(18*4), 0x00000000);
 989         write32(BAR+DCALDATA+(19*4), 0x00000000);
 990
 991         /* No command */
 992         write32(BAR+DCALCSR, 0x0000000f);
 993
 994         write32(BAR+0x150, recena);
 995         write32(BAR+0x154, recenb);
 996 }
 997
 998
 999 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1000 {
1001         int i;
1002         int cs;
1003         int cnt;
1004         int cas_latency;
1005         long mask;
1006         uint32_t drc;
1007         uint32_t data32;
1008         uint32_t mode_reg;
1009         uint32_t *iptr;
1010         volatile unsigned long *iptrv;
1011         msr_t msr;
1012         uint32_t scratch;
1013         uint8_t byte;
1014         uint16_t data16;
1015         static const struct {
1016                 uint32_t clkgr[4];
1017         } gearing [] = {
1018                 /* FSB 133 DIMM 266 */
1019         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1020                 /* FSB 133 DIMM 333 */
1021         {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1022                 /* FSB 133 DIMM 400 */
1023         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1024                 /* FSB 167 DIMM 266 */
1025         {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1026                 /* FSB 167 DIMM 333 */
1027         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1028                 /* FSB 167 DIMM 400 */
1029         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1030                 /* FSB 200 DIMM 266 */
1031         {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1032                 /* FSB 200 DIMM 333 */
1033         {{ 0x00065432, 0x00010000, 0x00054326, 0x00000000}},
1034                 /* FSB 200 DIMM 400 */
1035         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1036         };
1037
1038         static const uint32_t dqs_data[] = {
1039                 0xffffffff, 0xffffffff, 0x000000ff,
1040                 0xffffffff, 0xffffffff, 0x000000ff,
1041                 0xffffffff, 0xffffffff, 0x000000ff,
1042                 0xffffffff, 0xffffffff, 0x000000ff,
1043                 0xffffffff, 0xffffffff, 0x000000ff,
1044                 0xffffffff, 0xffffffff, 0x000000ff,
1045                 0xffffffff, 0xffffffff, 0x000000ff,
1046                 0xffffffff, 0xffffffff, 0x000000ff};
1047
1048         mask = spd_detect_dimms(ctrl);
1049         print_debug("Starting SDRAM Enable\n");
1050
1051         /* 0x80 */
1052 #ifdef DIMM_MAP_LOGICAL
1053         pci_write_config32(ctrl->f0, DRM,
1054                 0x00210000 | DIMM_MAP_LOGICAL);
1055 #else
1056         pci_write_config32(ctrl->f0, DRM, 0x00211248);
1057 #endif
1058         /* set dram type and Front Side Bus freq. */
1059         drc = spd_set_dram_controller_mode(ctrl, mask);
1060         if( drc == 0) {
1061                 die("Error calculating DRC\n");
1062         }
1063         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1064         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
1065         data32 = data32 | (1 << 5);  /* temp turn off of ODT */
1066         /* Set gearing, then dram controller mode */
1067         /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1068         for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1069                         cnt<4;cnt++) {
1070                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1071         }
1072         /* 0x7c DRC */
1073         pci_write_config32(ctrl->f0, DRC, data32);
1074
1075                 /* turn the clocks on */
1076         /* 0x8c CKDIS */
1077         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1078
1079                 /* 0x9a DDRCSR Take subsystem out of idle */
1080         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1081         data16 &= ~(7 << 12);
1082         data16 |= (3 << 12);   /* use dual channel lock step */
1083         pci_write_config16(ctrl->f0, DDRCSR, data16);
1084
1085                 /* program row size DRB */
1086         spd_set_ram_size(ctrl, mask);
1087
1088                 /* program page size DRA */
1089         spd_set_row_attributes(ctrl, mask);
1090
1091                 /* program DRT timing values */
1092         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1093
1094         for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1095                 print_debug("DIMM ");
1096                 print_debug_hex8(i);
1097                 print_debug("\n");
1098                 /* Apply NOP */
1099                 do_delay();
1100
1101                 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1102
1103                 write32(BAR+0x100, (0x83000000 | (i<<20)));
1104
1105                 data32 = read32(BAR+DCALCSR);
1106                 while(data32 & 0x80000000)
1107                         data32 = read32(BAR+DCALCSR);
1108
1109         }
1110
1111         /* Apply NOP */
1112         do_delay();
1113
1114         for(cs=0;cs<8;cs++) {
1115                 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1116                 data32 = read32(BAR+DCALCSR);
1117                 while(data32 & 0x80000000)
1118                         data32 = read32(BAR+DCALCSR);
1119         }
1120
1121         /* Precharg all banks */
1122         do_delay();
1123         for(cs=0;cs<8;cs++) {
1124                 if ((drc & 3) == 2) /* DDR2  */
1125                         write32(BAR+DCALADDR, 0x04000000);
1126                 else   /* DDR1  */
1127                         write32(BAR+DCALADDR, 0x00000000);
1128                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1129                 data32 = read32(BAR+DCALCSR);
1130                 while(data32 & 0x80000000)
1131                         data32 = read32(BAR+DCALCSR);
1132         }
1133
1134         /* EMRS dll's enabled */
1135         do_delay();
1136         for(cs=0;cs<8;cs++) {
1137                 if ((drc & 3) == 2) /* DDR2  */
1138                         /* fixme hard code AL additive latency */
1139                         write32(BAR+DCALADDR, 0x0b940001);
1140                 else   /* DDR1  */
1141                         write32(BAR+DCALADDR, 0x00000001);
1142                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1143                 data32 = read32(BAR+DCALCSR);
1144                 while(data32 & 0x80000000)
1145                         data32 = read32(BAR+DCALCSR);
1146         }
1147         /* MRS reset dll's */
1148         do_delay();
1149         if ((drc & 3) == 2) {  /* DDR2  */
1150                 if(cas_latency == 30)
1151                         mode_reg = 0x053a0000;
1152                 else
1153                         mode_reg = 0x054a0000;
1154         }
1155         else {  /* DDR1  */
1156                 if(cas_latency == 20)
1157                         mode_reg = 0x012a0000;
1158                 else  /*  CAS Latency 2.5 */
1159                         mode_reg = 0x016a0000;
1160         }
1161         for(cs=0;cs<8;cs++) {
1162                 write32(BAR+DCALADDR, mode_reg);
1163                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1164                 data32 = read32(BAR+DCALCSR);
1165                 while(data32 & 0x80000000)
1166                         data32 = read32(BAR+DCALCSR);
1167         }
1168
1169         /* Precharg all banks */
1170         do_delay();
1171         do_delay();
1172         do_delay();
1173         for(cs=0;cs<8;cs++) {
1174                 if ((drc & 3) == 2) /* DDR2  */
1175                         write32(BAR+DCALADDR, 0x04000000);
1176                 else   /* DDR1  */
1177                         write32(BAR+DCALADDR, 0x00000000);
1178                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1179                 data32 = read32(BAR+DCALCSR);
1180                 while(data32 & 0x80000000)
1181                         data32 = read32(BAR+DCALCSR);
1182         }
1183
1184         /* Do 2 refreshes */
1185         do_delay();
1186         for(cs=0;cs<8;cs++) {
1187                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1188                 data32 = read32(BAR+DCALCSR);
1189                 while(data32 & 0x80000000)
1190                         data32 = read32(BAR+DCALCSR);
1191         }
1192         do_delay();
1193         for(cs=0;cs<8;cs++) {
1194                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1195                 data32 = read32(BAR+DCALCSR);
1196                 while(data32 & 0x80000000)
1197                         data32 = read32(BAR+DCALCSR);
1198         }
1199         do_delay();
1200         /* for good luck do 6 more */
1201         for(cs=0;cs<8;cs++) {
1202                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1203         }
1204         do_delay();
1205         for(cs=0;cs<8;cs++) {
1206                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1207         }
1208         do_delay();
1209         for(cs=0;cs<8;cs++) {
1210                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1211         }
1212         do_delay();
1213         for(cs=0;cs<8;cs++) {
1214                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1215         }
1216         do_delay();
1217         for(cs=0;cs<8;cs++) {
1218                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1219         }
1220         do_delay();
1221         for(cs=0;cs<8;cs++) {
1222                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1223         }
1224         do_delay();
1225         /* MRS reset dll's normal */
1226         do_delay();
1227         for(cs=0;cs<8;cs++) {
1228                 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1229                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1230                 data32 = read32(BAR+DCALCSR);
1231                 while(data32 & 0x80000000)
1232                         data32 = read32(BAR+DCALCSR);
1233         }
1234
1235         /* Do only if DDR2  EMRS dll's enabled */
1236         if ((drc & 3) == 2) { /* DDR2  */
1237                 do_delay();
1238                 for(cs=0;cs<8;cs++) {
1239                         write32(BAR+DCALADDR, (0x0b940001));
1240                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1241                         data32 = read32(BAR+DCALCSR);
1242                         while(data32 & 0x80000000)
1243                                 data32 = read32(BAR+DCALCSR);
1244                 }
1245         }
1246
1247         do_delay();
1248         /* No command */
1249         write32(BAR+DCALCSR, 0x0000000f);
1250
1251         /* DDR1 This is test code to copy some codes in the factory setup */
1252
1253         write32(BAR, 0x00100000);
1254
1255         if ((drc & 3) == 2) { /* DDR2  */
1256         /* enable on dimm termination */
1257                 set_on_dimm_termination_enable(ctrl);
1258         }
1259
1260         /* receive enable calibration */
1261         set_receive_enable(ctrl);
1262
1263         /* DQS */
1264         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1265         for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1266                 write32(cnt, dqs_data[i]);
1267         }
1268         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1269
1270         /* Enable refresh */
1271         /* 0x7c DRC */
1272         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1273         pci_write_config32(ctrl->f0, DRC, data32);
1274         write32(BAR+DCALCSR, 0x0008000f);
1275
1276         /* clear memory and init ECC */
1277         print_debug("Clearing memory\n");
1278         for(i=0;i<64;i+=4) {
1279                 write32(BAR+DCALDATA+i, 0x00000000);
1280         }
1281
1282         for(cs=0;cs<8;cs++) {
1283                 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1284                 data32 = read32(BAR+DCALCSR);
1285                 while(data32 & 0x80000000)
1286                         data32 = read32(BAR+DCALCSR);
1287         }
1288
1289         /* Bring memory subsystem on line */
1290         data32 = pci_read_config32(ctrl->f0, 0x98);
1291         data32 |= (1 << 31);
1292         pci_write_config32(ctrl->f0, 0x98, data32);
1293         /* wait for completion */
1294         print_debug("Waiting for mem complete\n");
1295         while(1) {
1296                 data32 = pci_read_config32(ctrl->f0, 0x98);
1297                 if( (data32 & (1<<31)) == 0)
1298                         break;
1299         }
1300         print_debug("Done\n");
1301
1302         /* Set initialization complete */
1303         /* 0x7c DRC */
1304         drc |= (1 << 29);
1305         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1306         pci_write_config32(ctrl->f0, DRC, data32);
1307
1308         /* Set the ecc mode */
1309         pci_write_config32(ctrl->f0, DRC, drc);
1310
1311         /* Enable memory scrubbing */
1312         /* 0x52 MCHSCRB */
1313         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1314         data16 &= ~0x0f;
1315         data16 |= ((2 << 2) | (2 << 0));
1316         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1317
1318         /* The memory is now setup, use it */
1319         cache_lbmem(MTRR_TYPE_WRBACK);
1320 }