src/northbridge/intel/e7525/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14 #include "e7525.h"
  15
  16
  17 static unsigned int max_bus;
  18
  19 #if CONFIG_WRITE_HIGH_TABLES==1
  20 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  21 extern uint64_t high_tables_base, high_tables_size;
  22 #endif
  23
  24 static void pci_domain_set_resources(device_t dev)
  25 {
  26         device_t mc_dev;
  27         uint32_t pci_tolm;
  28
  29         pci_tolm = find_pci_tolm(dev->link_list);
  30
  31 #if 1
  32         printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
  33 #endif
  34         /* FIXME Me temporary hack */
  35         if(pci_tolm > 0xe0000000)
  36                 pci_tolm = 0xe0000000;
  37         /* Ensure pci_tolm is 128M aligned */
  38         pci_tolm &= 0xf8000000;
  39         mc_dev = dev->link_list->children;
  40         if (mc_dev) {
  41                 /* Figure out which areas are/should be occupied by RAM.
  42                  * This is all computed in kilobytes and converted to/from
  43                  * the memory controller right at the edges.
  44                  * Having different variables in different units is
  45                  * too confusing to get right.  Kilobytes are good up to
  46                  * 4 Terabytes of RAM...
  47                  */
  48                 uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
  49                 unsigned long tomk, tolmk;
  50                 unsigned long remapbasek, remaplimitk, remapoffsetk;
  51
  52                 /* Get the Top of Memory address, units are 128M */
  53                 tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
  54                 /* Compute the Top of Low Memory */
  55                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
  56
  57                 if (tolmk >= tomk) {
  58                         /* The PCI hole does not overlap memory
  59                          * we won't use the remap window.
  60                          */
  61                         tolmk = tomk;
  62                         remapbasek   = 0x3ff << 16;
  63                         remaplimitk  = 0 << 16;
  64                         remapoffsetk = 0 << 16;
  65                 }
  66                 else {
  67                         /* The PCI memory hole overlaps memory
  68                          * setup the remap window.
  69                          */
  70                         /* Find the bottom of the remap window
  71                          * is it above 4G?
  72                          */
  73                         remapbasek = 4*1024*1024;
  74                         if (tomk > remapbasek) {
  75                                 remapbasek = tomk;
  76                         }
  77                         /* Find the limit of the remap window */
  78                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
  79                         /* Find the offset of the remap window from tolm */
  80                         remapoffsetk = remapbasek - tolmk;
  81                 }
  82                 /* Write the ram configruation registers,
  83                  * preserving the reserved bits.
  84                  */
  85                 tolm_r = pci_read_config16(mc_dev, 0xc4);
  86                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
  87                 pci_write_config16(mc_dev, 0xc4, tolm_r);
  88
  89                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
  90                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
  91                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
  92
  93                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
  94                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
  95                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
  96
  97                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
  98                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
  99                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 100
 101                 /* Report the memory regions */
 102                 ram_resource(dev, 3,   0, 640);
 103                 ram_resource(dev, 4, 768, (tolmk - 768));
 104                 if (tomk > 4*1024*1024) {
 105                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 106                 }
 107                 if (remaplimitk >= remapbasek) {
 108                         ram_resource(dev, 6, remapbasek,
 109                                 (remaplimitk + 64*1024) - remapbasek);
 110                 }
 111
 112 #if CONFIG_WRITE_HIGH_TABLES==1
 113                 /* Leave some space for ACPI, PIRQ and MP tables */
 114                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 115                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 116 #endif
 117         }
 118         assign_resources(dev->link_list);
 119 }
 120
 121 static u32 e7525_domain_scan_bus(device_t dev, u32 max)
 122 {
 123         max_bus = pci_domain_scan_bus(dev, max);
 124         return max_bus;
 125 }
 126
 127 static struct device_operations pci_domain_ops = {
 128         .read_resources   = pci_domain_read_resources,
 129         .set_resources    = pci_domain_set_resources,
 130         .enable_resources = NULL,
 131         .init             = NULL,
 132         .scan_bus         = e7525_domain_scan_bus,
 133         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 134 };
 135
 136 static void mc_read_resources(device_t dev)
 137 {
 138         struct resource *resource;
 139
 140         pci_dev_read_resources(dev);
 141
 142         resource = new_resource(dev, 0xcf);
 143         resource->base = 0xe0000000;
 144         resource->size = max_bus * 4096*256;
 145         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 146 }
 147
 148 static void mc_set_resources(device_t dev)
 149 {
 150         struct resource *resource;
 151
 152         resource = find_resource(dev, 0xcf);
 153         if (resource) {
 154                 report_resource_stored(dev, resource, "<mmconfig>");
 155         }
 156         pci_dev_set_resources(dev);
 157 }
 158
 159 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 160 {
 161         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 162                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 163 }
 164
 165 static struct pci_operations intel_pci_ops = {
 166         .set_subsystem = intel_set_subsystem,
 167 };
 168
 169 static struct device_operations mc_ops = {
 170         .read_resources   = mc_read_resources,
 171         .set_resources    = mc_set_resources,
 172         .enable_resources = pci_dev_enable_resources,
 173         .init             = 0,
 174         .scan_bus         = 0,
 175         .ops_pci          = &intel_pci_ops,
 176 };
 177
 178 static const struct pci_driver mc_driver __pci_driver = {
 179         .ops = &mc_ops,
 180         .vendor = PCI_VENDOR_ID_INTEL,
 181         .device = 0x359e,
 182 };
 183
 184 static void cpu_bus_init(device_t dev)
 185 {
 186         initialize_cpus(dev->link_list);
 187 }
 188
 189 static void cpu_bus_noop(device_t dev)
 190 {
 191 }
 192
 193 static struct device_operations cpu_bus_ops = {
 194         .read_resources   = cpu_bus_noop,
 195         .set_resources    = cpu_bus_noop,
 196         .enable_resources = cpu_bus_noop,
 197         .init             = cpu_bus_init,
 198         .scan_bus         = 0,
 199 };
 200
 201
 202 static void enable_dev(device_t dev)
 203 {
 204         /* Set the operations if it is a special bus type */
 205         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 206                 dev->ops = &pci_domain_ops;
 207         }
 208         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 209                 dev->ops = &cpu_bus_ops;
 210         }
 211 }
 212
 213 struct chip_operations northbridge_intel_e7525_ops = {
 214         CHIP_NAME("Intel E7525 Northbridge")
 215         .enable_dev = enable_dev,
 216 };