src/northbridge/intel/e7505/raminit.c

   1 /* This was originally for the e7500, modified for e7501
   2  * The primary differences are that 7501 apparently can
   3  * support single channel RAM (i haven't tested),
   4  * CAS1.5 is no longer supported, The ECC scrubber
   5  * now supports a mode to zero RAM and init ECC in one step
   6  * and the undocumented registers at 0x80 require new
   7  * (undocumented) values determined by guesswork and
   8  * comparison w/ OEM BIOS values.
   9  * Steven James 02/06/2003
  10  */
  11
  12 /* converted to C 6/2004 yhlu */
  13
  14 #include <assert.h>
  15 #include <spd.h>
  16 #include <sdram_mode.h>
  17 #include <stdlib.h>
  18 #include "e7505.h"
  19
  20 /*-----------------------------------------------------------------------------
  21 Definitions:
  22 -----------------------------------------------------------------------------*/
  23
  24 // Uncomment this to enable run-time checking of DIMM parameters
  25 // for dual-channel operation
  26 // Unfortunately the code seems to chew up several K of space.
  27 //#define VALIDATE_DIMM_COMPATIBILITY
  28
  29 #if CONFIG_DEBUG_RAM_SETUP
  30 #define RAM_DEBUG_MESSAGE(x)    print_debug(x)
  31 #define RAM_DEBUG_HEX32(x)      print_debug_hex32(x)
  32 #define RAM_DEBUG_HEX8(x)       print_debug_hex8(x)
  33 #define DUMPNORTH()             dump_pci_device(PCI_DEV(0, 0, 0))
  34 #else
  35 #define RAM_DEBUG_MESSAGE(x)
  36 #define RAM_DEBUG_HEX32(x)
  37 #define RAM_DEBUG_HEX8(x)
  38 #define DUMPNORTH()
  39 #endif
  40
  41 #define E7501_SDRAM_MODE        (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
  42 #define SPD_ERROR               "Error reading SPD info\n"
  43
  44 // NOTE: This used to be 0x100000.
  45 //       That doesn't work on systems where A20M# is asserted, because
  46 //       attempts to access 0x1000NN end up accessing 0x0000NN.
  47 #define RCOMP_MMIO 0x200000
  48
  49 struct dimm_size {
  50         unsigned long side1;
  51         unsigned long side2;
  52 };
  53
  54 static const uint32_t refresh_frequency[] = {
  55         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  56          * (RMS) value (array index)
  57          * 0 == least frequent refresh (longest interval between refreshes)
  58          * [0] disabled  -> 0
  59          * [1] 15.6 usec -> 2
  60          * [2]  7.8 usec -> 3
  61          * [3] 64   usec -> 1
  62          * [4] reserved  -> 0
  63          * [5] reserved  -> 0
  64          * [6] reserved  -> 0
  65          * [7] 64 clocks -> 4
  66          */
  67         0, 2, 3, 1, 0, 0, 0, 4
  68 };
  69
  70 static const uint32_t refresh_rate_map[] = {
  71         /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
  72          * Select values (array value)
  73          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  74          * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
  75          * 64 clock (481 ns) (7) refresh.
  76          * [0] ==  15.625 us -> 15.6 us
  77          * [1] ==   3.9   us -> 481  ns
  78          * [2] ==   7.8   us ->  7.8 us
  79          * [3] ==  31.3   us -> 15.6 us
  80          * [4] ==  62.5   us -> 15.6 us
  81          * [5] == 125     us -> 64   us
  82          */
  83         1, 7, 2, 1, 1, 3
  84 };
  85
  86 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
  87
  88 // SPD parameters that must match for dual-channel operation
  89 static const uint8_t dual_channel_parameters[] = {
  90         SPD_MEMORY_TYPE,
  91         SPD_MODULE_VOLTAGE,
  92         SPD_NUM_COLUMNS,
  93         SPD_NUM_ROWS,
  94         SPD_NUM_DIMM_BANKS,
  95         SPD_PRIMARY_SDRAM_WIDTH,
  96         SPD_NUM_BANKS_PER_SDRAM
  97 };
  98
  99         /*
 100          * Table:       constant_register_values
 101          */
 102 static const long constant_register_values[] = {
 103         /* SVID - Subsystem Vendor Identification Register
 104          * 0x2c - 0x2d
 105          * [15:00] Subsytem Vendor ID (Indicates system board vendor)
 106          */
 107         /* SID - Subsystem Identification Register
 108          * 0x2e - 0x2f
 109          * [15:00] Subsystem ID
 110          */
 111         // Not everyone wants to be Super Micro Computer, Inc.
 112         // The mainboard should set this if desired.
 113         // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
 114
 115         /* Undocumented
 116          * (DRAM Read Timing Control, if similar to 855PM?)
 117          * 0x80 - 0x81
 118          * This register has something to do with CAS latencies,
 119          * possibily this is the real chipset control.
 120          * At 0x00 CAS latency 1.5 works.
 121          * At 0x06 CAS latency 2.5 works.
 122          * At 0x01 CAS latency 2.0 works.
 123          */
 124         /* This is still undocumented in e7501, but with different values
 125          * CAS 2.0 values taken from Intel BIOS settings, others are a guess
 126          * and may be terribly wrong. Old values preserved as comments until I
 127          * figure this out for sure.
 128          * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
 129          * work at all.
 130          * Steven James 02/06/2003
 131          */
 132         /* NOTE: values now configured in configure_e7501_cas_latency() based
 133          *       on SPD info and total number of DIMMs (per Intel)
 134          */
 135
 136         /* FDHC - Fixed DRAM Hole Control
 137          * 0x58
 138          * [7:7] Hole_Enable
 139          *       0 == No memory Hole
 140          *       1 == Memory Hole from 15MB to 16MB
 141          * [6:0] Reserved
 142          *
 143          * PAM - Programmable Attribute Map
 144          * 0x59 [1:0] Reserved
 145          * 0x59 [5:4] 0xF0000 - 0xFFFFF
 146          * 0x5A [1:0] 0xC0000 - 0xC3FFF
 147          * 0x5A [5:4] 0xC4000 - 0xC7FFF
 148          * 0x5B [1:0] 0xC8000 - 0xCBFFF
 149          * 0x5B [5:4] 0xCC000 - 0xCFFFF
 150          * 0x5C [1:0] 0xD0000 - 0xD3FFF
 151          * 0x5C [5:4] 0xD4000 - 0xD7FFF
 152          * 0x5D [1:0] 0xD8000 - 0xDBFFF
 153          * 0x5D [5:4] 0xDC000 - 0xDFFFF
 154          * 0x5E [1:0] 0xE0000 - 0xE3FFF
 155          * 0x5E [5:4] 0xE4000 - 0xE7FFF
 156          * 0x5F [1:0] 0xE8000 - 0xEBFFF
 157          * 0x5F [5:4] 0xEC000 - 0xEFFFF
 158          *       00 == DRAM Disabled (All Access go to memory mapped I/O space)
 159          *       01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
 160          *       10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
 161          *       11 == Normal (All Access go to DRAM)
 162          */
 163
 164         // Map all legacy ranges to DRAM
 165         0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
 166         0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
 167
 168         /* DRB - DRAM Row Boundary Registers
 169          * 0x60 - 0x6F
 170          *     An array of 8 byte registers, which hold the ending
 171          *     memory address assigned  to each pair of DIMMS, in 64MB
 172          *     granularity.
 173          */
 174         // Conservatively say each row has 64MB of ram, we will fix this up later
 175         // NOTE: These defaults allow us to prime all of the DIMMs on the board
 176         //               without jumping through 36-bit adddressing hoops, even if the
 177         //               total memory is > 4 GB. Changing these values may break do_ram_command()!
 178         0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
 179 //      0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
 180         0x64, 0x00000000, (0x04 << 0) | (0x04 << 8) | (0x04 << 16) | (0x04 << 24),
 181
 182         /* DRA - DRAM Row Attribute Register
 183          * 0x70 Row 0,1
 184          * 0x71 Row 2,3
 185          * 0x72 Row 4,5
 186          * 0x73 Row 6,7
 187          * [7:7] Device width for Odd numbered rows
 188          *       0 == 8 bits wide x8
 189          *       1 == 4 bits wide x4
 190          * [6:4] Row Attributes for Odd numbered rows
 191          *       010 == 8KB (for dual-channel)
 192          *       011 == 16KB (for dual-channel)
 193          *       100 == 32KB (for dual-channel)
 194          *       101 == 64KB (for dual-channel)
 195          *       Others == Reserved
 196          * [3:3] Device width for Even numbered rows
 197          *       0 == 8 bits wide x8
 198          *       1 == 4 bits wide x4
 199          * [2:0] Row Attributes for Even numbered rows
 200          *       010 == 8KB (for dual-channel)
 201          *       011 == 16KB (for dual-channel)
 202          *       100 == 32KB (for dual-channel)
 203          *       101 == 64KB (This page size appears broken)
 204          *       Others == Reserved
 205          */
 206         // NOTE: overridden by configure_e7501_row_attributes(), later
 207         0x70, 0x00000000, 0,
 208
 209         /* DRT - DRAM Timing Register
 210          * 0x78
 211          * [31:30] Reserved
 212          * [29:29] Back to Back Write-Read Turn Around
 213          *         0 == 3 clocks between WR-RD commands
 214          *         1 == 2 clocks between WR-RD commands
 215          * [28:28] Back to Back Read-Write Turn Around
 216          *         0 == 5 clocks between RD-WR commands
 217          *         1 == 4 clocks between RD-WR commands
 218          * [27:27] Back to Back Read Turn Around
 219          *         0 == 4 clocks between RD commands
 220          *         1 == 3 clocks between RD commands
 221          * [26:24] Read Delay (tRD)
 222          *         000 == 7 clocks
 223          *         001 == 6 clocks
 224          *         010 == 5 clocks
 225          *         Others == Reserved
 226          * [23:19] Reserved
 227          * [18:16] DRAM idle timer
 228          *      000 == infinite
 229          *      011 == 16 dram clocks
 230          *      001 == 0 clocks
 231          * [15:11] Reserved
 232          * [10:09] Active to Precharge (tRAS)
 233          *         00 == 7 clocks
 234          *         01 == 6 clocks
 235          *         10 == 5 clocks
 236          *         11 == Reserved
 237          * [08:06] Reserved
 238          * [05:04] Cas Latency (tCL)
 239          *         00 == 2.5 Clocks
 240          *         01 == 2.0 Clocks
 241          *         10 == Reserved (was 1.5 Clocks for E7500)
 242          *         11 == Reserved
 243          * [03:03] Write Ras# to Cas# Delay (tRCD)
 244          *         0 == 3 DRAM Clocks
 245          *         1 == 2 DRAM Clocks
 246          * [02:01] Read RAS# to CAS# Delay (tRCD)
 247          *         00 == reserved
 248          *         01 == reserved
 249          *         10 == 3 DRAM Clocks
 250          *         11 == 2 DRAM Clocks
 251          * [00:00] DRAM RAS# to Precharge (tRP)
 252          *         0 == 3 DRAM Clocks
 253          *         1 == 2 DRAM Clocks
 254          */
 255
 256         // Some earlier settings:
 257         /* Most aggressive settings possible */
 258 //      0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
 259 //      0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 260 //      0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 261
 262         // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
 263         // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
 264 //      0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16),
 265         0x78, 0xC7F8FFFF, (0x03<<16)|(0x28<<24),
 266
 267         /* FIXME why was I attempting to set a reserved bit? */
 268         /* 0x0100040f */
 269
 270         /* DRC - DRAM Contoller Mode Register
 271          * 0x7c
 272          * [31:30] Reserved
 273          * [29:29] Initialization Complete
 274          *         0 == Not Complete
 275          *         1 == Complete
 276          * [28:23] Reserved
 277          * [22:22]         Channels
 278          *              0 == Single channel
 279          *              1 == Dual Channel
 280          * [21:20] DRAM Data Integrity Mode
 281          *         00 == Disabled, no ECC
 282          *         01 == Reserved
 283          *         10 == Error checking, using chip-kill, with correction
 284          *         11 == Reserved
 285          * [19:18] DRB Granularity (Read-Only)
 286          *         00 == 32 MB quantities (single channel mode)
 287          *                 01 == 64 MB quantities (dual-channel mode)
 288          *                 10 == Reserved
 289          *                 11 == Reserved
 290          * [17:17] (Intel Undocumented) should always be set to 1       (SJM: comment inconsistent with current setting, below)
 291          * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
 292          *         0 == 2n Rule
 293          *         1 == 1n rule
 294          * [15:11] Reserved
 295          * [10:08] Refresh mode select
 296          *         000 == Refresh disabled
 297          *         001 == Refresh interval 15.6 usec
 298          *         010 == Refresh interval 7.8 usec
 299          *         011 == Refresh interval 64 usec
 300          *         111 == Refresh every 64 clocks (fast refresh)
 301          * [07:07] Reserved
 302          * [06:04] Mode Select (SMS)
 303          *         000 == Reserved (was Self Refresh Mode in E7500)
 304          *         001 == NOP Command
 305          *         010 == All Banks Precharge
 306          *         011 == Mode Register Set
 307          *         100 == Extended Mode Register Set
 308          *         101 == Reserved
 309          *         110 == CBR Refresh
 310          *         111 == Normal Operation
 311          * [03:00] Reserved
 312          */
 313 //      .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
 314 //      .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
 315 //      .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
 316
 317         // Default to dual-channel mode, ECC, 1-clock address/cmd hold
 318         // NOTE: configure_e7501_dram_controller_mode() configures further
 319 //      0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
 320         0x7c, 0xffcef8f7, 0x00210008,
 321
 322         /* Another Intel undocumented register
 323          * 0x88 - 0x8B
 324          * [31:31]      Purpose unknown
 325          * [26:26]      Master DLL Reset?
 326          *                      0 == Normal operation?
 327          *                      1 == Reset?
 328          * [07:07]      Periodic memory recalibration?
 329          *                      0 == Disabled?
 330          *                      1 == Enabled?
 331          * [04:04]      Receive FIFO RE-Sync?
 332          *                      0 == Normal operation?
 333          *                      1 == Reset?
 334          */
 335         // NOTE: Some factory BIOSs don't do this.
 336         //               Doesn't seem to matter either way.
 337         0x88, 0xffffff00, 0x80,
 338
 339         /* CLOCK_DIS - CK/CK# Disable Register
 340          * 0x8C
 341          * [7:7] DDR Frequency
 342          *               0 == 100 MHz (200 MHz data rate)
 343          *               1 == 133 MHz (266 MHz data rate)
 344          * [6:4] Reserved
 345          * [3:3] CK3
 346          *       0 == Enable
 347          *       1 == Disable
 348          * [2:2] CK2
 349          *       0 == Enable
 350          *       1 == Disable
 351          * [1:1] CK1
 352          *       0 == Enable
 353          *       1 == Disable
 354          * [0:0] CK0
 355          *       0 == Enable
 356          *       1 == Disable
 357          */
 358         // NOTE: Disable all clocks initially; turn ones we need back on
 359         //               in enable_e7501_clocks()
 360         0x8C, 0xfffffff0, 0xf,
 361
 362         /* TOLM - Top of Low Memory Register
 363          * 0xC4 - 0xC5
 364          * [15:11] Top of low memory (TOLM)
 365          *         The address below 4GB that should be treated as RAM,
 366          *         on a 128MB granularity.
 367          * [10:00] Reserved
 368          */
 369         /* REMAPBASE - Remap Base Address Regsiter
 370          * 0xC6 - 0xC7
 371          * [15:10] Reserved
 372          * [09:00] Remap Base Address [35:26] 64M aligned
 373          *         Bits [25:0] are assumed to be 0.
 374          */
 375
 376         // NOTE: TOLM overridden by configure_e7501_ram_addresses()
 377         0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
 378
 379         /* REMAPLIMIT - Remap Limit Address Register
 380          * 0xC8 - 0xC9
 381          * [15:10] Reserved
 382          * [09:00] Remap Limit Address [35:26] 64M aligned
 383          * When remaplimit < remapbase the remap window is disabled.
 384          */
 385         0xc8, 0xfffffc00, 0,
 386
 387         /* DVNP - Device Not Present Register
 388          * 0xE0 - 0xE1
 389          * [15:05] Reserved
 390          * [04:04] Device 4 Function 1 Present
 391          *         0 == Present
 392          *         1 == Absent
 393          * [03:03] Device 3 Function 1 Present
 394          *         0 == Present
 395          *         1 == Absent
 396          * [02:02] Device 2 Function 1 Present
 397          *         0 == Present
 398          *         1 == Absent
 399          * [01:01] Reserved
 400          * [00:00] Device 0 Function 1 Present
 401          *         0 == Present
 402          *         1 == Absent
 403          */
 404
 405         // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
 406 //      0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0),
 407         0xe0, 0xfffffffa, 0x0,
 408
 409         // Undocumented
 410         0xd8, 0xffff9fff, 0x00000000,
 411
 412         // Undocumented - this is pure conjecture based on similarity to 855PM
 413         /* MCHTST - MCH Test Register
 414          * 0xF4 - 0xF7
 415          * [31:31] Purpose unknown
 416          * [30:30] Purpose unknown
 417          * [29:23] Unknown - not used?
 418          * [22:22] System Memory MMR Enable
 419          *         0 == Disable: mem space and BAR at 0x14 are not accessible
 420          *         1 == Enable: mem space and BAR at 0x14 are accessible
 421          * [21:20] Purpose unknown
 422          * [19:02] Unknown - not used?
 423          * [01:01] D6EN (Device #6 enable)
 424          *         0 == Disable
 425          *         1 == Enable
 426          * [00:00] Unknown - not used?
 427          */
 428
 429 //      0xf4, 0x3f8ffffd, 0x40300002,
 430
 431 #ifdef SUSPICIOUS_LOOKING_CODE
 432         // SJM: Undocumented.
 433         //              This will access D2:F0:0x50, is this correct??
 434         0x1050, 0xffffffcf, 0x00000030,
 435 #endif
 436 };
 437
 438         /* DDR RECOMP tables */
 439 #if 0
 440 // Slew table for 1x drive?
 441 static const uint32_t maybe_1x_slew_table[] = {
 442         0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
 443         0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
 444 };
 445 #endif
 446
 447 // Slew table for 2x drive?
 448 static const uint32_t maybe_2x_slew_table[] = {
 449         0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
 450         0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
 451 };
 452
 453 // Pull Up / Pull Down offset table, if analogous to IXP2800?
 454 static const uint32_t maybe_pull_updown_offset_table[] = {
 455         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 456         0x88888888, 0x88888888, 0x88888888, 0x88888888,
 457 };
 458
 459 /*-----------------------------------------------------------------------------
 460 Delay functions:
 461 -----------------------------------------------------------------------------*/
 462
 463 #define SLOW_DOWN_IO inb(0x80)
 464 //#define SLOW_DOWN_IO udelay(40);
 465
 466         /* Estimate that SLOW_DOWN_IO takes about 50&76us */
 467         /* delay for 200us */
 468
 469 #if 1
 470 static void do_delay(void)
 471 {
 472         int i;
 473         for (i = 0; i < 16; i++) {
 474                 SLOW_DOWN_IO;
 475         }
 476 }
 477
 478 #define DO_DELAY do_delay()
 479 #else
 480 #define DO_DELAY \
 481         udelay(200)
 482 #endif
 483
 484 #define EXTRA_DELAY DO_DELAY
 485
 486 /*-----------------------------------------------------------------------------
 487 Handle (undocumented) control bits in device 0:6.0
 488 -----------------------------------------------------------------------------*/
 489
 490 /**
 491  *
 492  */
 493 static void ram_handle_d060_1(void)
 494 {
 495         uint32_t dword;
 496
 497         dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
 498         dword |= 0x02;
 499         pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
 500
 501         dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0);
 502         dword |= 0x04;
 503         pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword);
 504
 505         dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
 506         dword &= ~0x02;
 507         pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
 508 }
 509
 510 /**
 511  *
 512  */
 513 static void ram_handle_d060_2(void)
 514 {
 515         uint32_t dword;
 516         uint8_t revision;
 517
 518         revision = pci_read_config8(PCI_DEV(0,0,0), 0x08);
 519         if (revision >= 3) {
 520                 dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
 521                 dword |= 0x02;
 522                 pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
 523
 524                 dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0);
 525                 dword |= 0x18000000;
 526                 pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword);
 527
 528                 dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
 529                 dword &= ~0x02;
 530                 pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
 531         }
 532 }
 533
 534 /*-----------------------------------------------------------------------------
 535 Serial presence detect (SPD) functions:
 536 -----------------------------------------------------------------------------*/
 537
 538 static void die_on_spd_error(int spd_return_value)
 539 {
 540         if (spd_return_value < 0)
 541                 die("Error reading SPD info\n");
 542 }
 543
 544 /**
 545  * Calculate the page size for each physical bank of the DIMM:
 546  *   log2(page size) = (# columns) + log2(data width)
 547  *
 548  * NOTE: Page size is the total number of data bits in a row.
 549  *
 550  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 551  * @return log2(page size) for each side of the DIMM.
 552  */
 553 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
 554 {
 555         uint16_t module_data_width;
 556         int value;
 557         struct dimm_size pgsz;
 558
 559         pgsz.side1 = 0;
 560         pgsz.side2 = 0;
 561
 562         // Side 1
 563         value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 564         if (value < 0)
 565                 goto hw_err;
 566         pgsz.side1 = value & 0xf;       // # columns in bank 1
 567
 568         /* Get the module data width and convert it to a power of two */
 569         value =
 570             spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 571         if (value < 0)
 572                 goto hw_err;
 573         module_data_width = (value & 0xff) << 8;
 574
 575         value =
 576             spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 577         if (value < 0)
 578                 goto hw_err;
 579         module_data_width |= (value & 0xff);
 580
 581         pgsz.side1 += log2(module_data_width);
 582
 583         /* side two */
 584         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 585         if (value < 0)
 586                 goto hw_err;
 587         if (value > 2)
 588                 die("Bad SPD value\n");
 589         if (value == 2) {
 590
 591                 pgsz.side2 = pgsz.side1;        // Assume symmetric banks until we know differently
 592                 value =
 593                     spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 594                 if (value < 0)
 595                         goto hw_err;
 596                 if ((value & 0xf0) != 0) {
 597                         // Asymmetric banks
 598                         pgsz.side2 -= value & 0xf;      /* Subtract out columns on side 1 */
 599                         pgsz.side2 += (value >> 4) & 0xf;       /* Add in columns on side 2 */
 600                 }
 601         }
 602
 603         return pgsz;
 604
 605       hw_err:
 606         die(SPD_ERROR);
 607         return pgsz;            // Never reached
 608 }
 609
 610 /**
 611  * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
 612  *
 613  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 614  * @return Width in bits of each DIMM side's DRAMs.
 615  */
 616 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 617 {
 618         int value;
 619         struct dimm_size width;
 620
 621         width.side1 = 0;
 622         width.side2 = 0;
 623
 624         value =
 625             spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 626         die_on_spd_error(value);
 627
 628         width.side1 = value & 0x7f;     // Mask off bank 2 flag
 629
 630         if (value & 0x80) {
 631                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 632         } else {
 633                 // If bank 2 exists, it's the same width as bank 1
 634                 value =
 635                     spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 636                 die_on_spd_error(value);
 637
 638 #ifdef ROMCC_IF_BUG_FIXED
 639                 if (value == 2)
 640                         width.side2 = width.side1;
 641 #else
 642                 switch (value) {
 643                 case 2:
 644                         width.side2 = width.side1;
 645                         break;
 646
 647                 default:
 648                         break;
 649                 }
 650 #endif
 651         }
 652
 653         return width;
 654 }
 655
 656 /**
 657  * Calculate the log base 2 size in bits of both DIMM sides.
 658  *
 659  * log2(# bits) = (# columns) + log2(data width) +
 660  *                (# rows) + log2(banks per SDRAM)
 661  *
 662  * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
 663  * as a multiple of 4MB. The way we do it now we can size both sides of an
 664  * asymmetric DIMM.
 665  *
 666  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 667  * @return log2(number of bits) for each side of the DIMM.
 668  */
 669 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
 670 {
 671         int value;
 672
 673         // Start with log2(page size)
 674         struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
 675
 676         if (sz.side1 > 0) {
 677
 678                 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
 679                 die_on_spd_error(value);
 680
 681                 sz.side1 += value & 0xf;
 682
 683                 if (sz.side2 > 0) {
 684
 685                         // Double-sided DIMM
 686                         if (value & 0xF0)
 687                                 sz.side2 += value >> 4; // Asymmetric
 688                         else
 689                                 sz.side2 += value;      // Symmetric
 690                 }
 691
 692                 value =
 693                     spd_read_byte(dimm_socket_address,
 694                                   SPD_NUM_BANKS_PER_SDRAM);
 695                 die_on_spd_error(value);
 696
 697                 value = log2(value);
 698                 sz.side1 += value;
 699                 if (sz.side2 > 0)
 700                         sz.side2 += value;
 701         }
 702
 703         return sz;
 704 }
 705
 706 #ifdef VALIDATE_DIMM_COMPATIBILITY
 707
 708 /**
 709  * Determine whether two DIMMs have the same value for an SPD parameter.
 710  *
 711  * @param spd_byte_number The SPD byte number to compare in both DIMMs.
 712  * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.
 713  * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.
 714  * @return 1 if both DIMM sockets report the same value for the specified
 715  *         SPD parameter, 0 if the values differed or an error occurred.
 716  */
 717 static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
 718                                     uint16_t dimm0_address,
 719                                     uint16_t dimm1_address)
 720 {
 721         uint8_t bEqual = 0;
 722         int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
 723         int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
 724
 725         if ((dimm0_value >= 0) && (dimm1_value >= 0)
 726             && (dimm0_value == dimm1_value))
 727                 bEqual = 1;
 728
 729         return bEqual;
 730 }
 731 #endif
 732
 733 /**
 734  * Scan for compatible DIMMs.
 735  *
 736  * The code in this module only supports dual-channel operation, so we test
 737  * that compatible DIMMs are paired.
 738  *
 739  * @param ctrl PCI addresses of memory controller functions, and SMBus
 740  *             addresses of DIMM slots on the mainboard.
 741  * @return A bitmask indicating which of the possible sockets for each channel
 742  *         was found to contain a compatible DIMM.
 743  *         Bit 0 corresponds to the closest socket for channel 0
 744  *         Bit 1 to the next socket for channel 0
 745  *         ...
 746  *         Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0
 747  *         Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1
 748  *         ...
 749  *         Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
 750  */
 751 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 752 {
 753         int i;
 754         uint8_t dimm_mask = 0;
 755
 756         // Have to increase size of dimm_mask if this assertion is violated
 757         ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
 758
 759         // Find DIMMs we can support on channel 0.
 760         // Then see if the corresponding channel 1 DIMM has the same parameters,
 761         // since we only support dual-channel.
 762
 763         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 764
 765                 uint16_t channel0_dimm = ctrl->channel0[i];
 766                 uint16_t channel1_dimm = ctrl->channel1[i];
 767                 uint8_t bDualChannel = 1;
 768 #ifdef VALIDATE_DIMM_COMPATIBILITY
 769                 struct dimm_size page_size;
 770                 struct dimm_size sdram_width;
 771 #endif
 772                 int spd_value;
 773
 774                 if (channel0_dimm == 0)
 775                         continue;       // No such socket on this mainboard
 776
 777                 if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
 778                     SPD_MEMORY_TYPE_SDRAM_DDR)
 779                         continue;
 780
 781 #ifdef VALIDATE_DIMM_COMPATIBILITY
 782                 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
 783                     SPD_VOLTAGE_SSTL2)
 784                         continue;       // Unsupported voltage
 785
 786                 // E7501 does not support unregistered DIMMs
 787                 spd_value =
 788                     spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
 789                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
 790                         continue;
 791
 792                 // Must support burst = 4 for dual-channel operation on E7501
 793                 // NOTE: for single-channel, burst = 8 is required
 794                 spd_value =
 795                     spd_read_byte(channel0_dimm,
 796                                   SPD_SUPPORTED_BURST_LENGTHS);
 797                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 798                         continue;
 799
 800                 page_size = sdram_spd_get_page_size(channel0_dimm);
 801                 sdram_width = sdram_spd_get_width(channel0_dimm);
 802
 803                 // Validate DIMM page size
 804                 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
 805                 // NOTE: 4 KB =  32 Kb = 2^15
 806                 //              32 KB = 262 Kb = 2^18
 807
 808                 if ((page_size.side1 < 15) || (page_size.side1 > 18))
 809                         continue;
 810
 811                 // If DIMM is double-sided, verify side2 page size
 812                 if (page_size.side2 != 0) {
 813                         if ((page_size.side2 < 15)
 814                             || (page_size.side2 > 18))
 815                                 continue;
 816                 }
 817                 // Validate SDRAM width
 818                 // The E7501 only supports x4 and x8 devices
 819
 820                 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
 821                         continue;
 822
 823                 // If DIMM is double-sided, verify side2 width
 824                 if (sdram_width.side2 != 0) {
 825                         if ((sdram_width.side2 != 4)
 826                             && (sdram_width.side2 != 8))
 827                                 continue;
 828                 }
 829 #endif
 830                 // Channel 0 DIMM looks compatible.
 831                 // Now see if it is paired with the proper DIMM on channel 1.
 832
 833                 ASSERT(channel1_dimm != 0);     // No such socket on this mainboard??
 834
 835                 // NOTE: unpopulated DIMMs cause read to fail
 836                 spd_value =
 837                     spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
 838                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 839
 840                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 841                         continue;
 842                 }
 843 #ifdef VALIDATE_DIMM_COMPATIBILITY
 844                 spd_value =
 845                     spd_read_byte(channel1_dimm,
 846                                   SPD_SUPPORTED_BURST_LENGTHS);
 847                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 848                         continue;
 849
 850                 int j;
 851                 for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
 852                         if (!are_spd_values_equal
 853                             (dual_channel_parameters[j], channel0_dimm,
 854                              channel1_dimm)) {
 855
 856                                 bDualChannel = 0;
 857                                 break;
 858                         }
 859                 }
 860 #endif
 861
 862                 // Code around ROMCC bug in optimization of "if" statements
 863 #ifdef ROMCC_IF_BUG_FIXED
 864                 if (bDualChannel) {
 865                         // Made it through all the checks, this DIMM pair is usable
 866                         dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
 867                 } else
 868                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 869 #else
 870                 switch (bDualChannel) {
 871                 case 0:
 872                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 873                         break;
 874
 875                 default:
 876                         // Made it through all the checks, this DIMM pair is usable
 877                         dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i));
 878                         break;
 879                 }
 880 #endif
 881         }
 882
 883         return dimm_mask;
 884 }
 885
 886 /*-----------------------------------------------------------------------------
 887 SDRAM configuration functions:
 888 -----------------------------------------------------------------------------*/
 889
 890 /**
 891  * Send the specified command to all DIMMs.
 892  *
 893  * @param command Specifies the command to be sent to the DIMMs.
 894  * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
 895  *                        register value in JEDEC format.
 896  */
 897 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 898 {
 899         uint8_t dimm_start_64M_multiple;
 900         uint32_t dimm_start_address;
 901         uint32_t dram_controller_mode;
 902         uint8_t i;
 903
 904         // Configure the RAM command
 905         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
 906         dram_controller_mode &= 0xFFFFFF8F;
 907         dram_controller_mode |= command;
 908         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
 909
 910         // RAM_COMMAND_NORMAL is an exception.
 911         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 912         if (command == RAM_COMMAND_NORMAL)
 913                 return;
 914
 915         // NOTE: for mode select commands, some of the location address bits are part of the command
 916         // Map JEDEC mode bits to E7505
 917         if (command == RAM_COMMAND_MRS) {
 918                 // Host address lines [25:18] map to DIMM address lines [7:0]
 919                 // Host address lines [17:16] map to DIMM address lines [9:8]
 920                 // Host address lines [15:4] map to DIMM address lines [11:0]
 921                 dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;
 922                 dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;
 923                 dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;
 924         } else if (command == RAM_COMMAND_EMRS) {
 925                 // Host address lines [15:4] map to DIMM address lines [11:0]
 926                 dimm_start_address = (jedec_mode_bits << 4);
 927         } else {
 928                 ASSERT(jedec_mode_bits == 0);
 929                 dimm_start_address = 0;
 930         }
 931
 932         // Send the command to all DIMMs by accessing a memory location within each
 933
 934         dimm_start_64M_multiple = 0;
 935
 936         for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
 937
 938                 uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
 939
 940                 if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
 941                         dimm_start_address &= 0x3ffffff;
 942                         dimm_start_address |= dimm_start_64M_multiple << 26;
 943                         read32(dimm_start_address);
 944                                 // Set the start of the next DIMM
 945                         dimm_start_64M_multiple = dimm_end_64M_multiple;
 946                 }
 947         }
 948
 949 }
 950
 951 /**
 952  * Set the mode register of all DIMMs.
 953  *
 954  * The proper CAS# latency setting is added to the mode bits specified
 955  * by the caller.
 956  *
 957  * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
 958  *                        register value in JEDEC format.
 959  */
 960 static void set_ram_mode(uint16_t jedec_mode_bits)
 961 {
 962         ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
 963
 964         uint32_t dram_cas_latency =
 965             pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
 966
 967         switch (dram_cas_latency) {
 968         case DRT_CAS_2_5:
 969                 jedec_mode_bits |= SDRAM_CAS_2_5;
 970                 break;
 971
 972         case DRT_CAS_2_0:
 973                 jedec_mode_bits |= SDRAM_CAS_2_0;
 974                 break;
 975
 976         default:
 977                 BUG();
 978                 break;
 979         }
 980
 981         do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
 982 }
 983
 984 /*-----------------------------------------------------------------------------
 985 DIMM-independant configuration functions:
 986 -----------------------------------------------------------------------------*/
 987
 988 /**
 989  * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory
 990  * present in the specified DIMM.
 991  *
 992  * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of
 993  *                           the DIMM.
 994  * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of
 995  *                                64 MB) for DIMMs < dimm_index.
 996  * @param dimm_index Which DIMM pair is being processed
 997  *                   (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
 998  * @return New multiple of 64 MB total DRAM in the system.
 999  */
1000 static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
1001 {
1002         int i;
1003
1004         ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
1005
1006         // DIMM sides must be at least 32 MB
1007         ASSERT(dimm_log2_num_bits.side1 >= 28);
1008         ASSERT((dimm_log2_num_bits.side2 == 0)
1009                || (dimm_log2_num_bits.side2 >= 28));
1010
1011         // In dual-channel mode, we are called only once for each pair of DIMMs.
1012         // Each time we process twice the capacity of a single DIMM.
1013
1014         // Convert single DIMM capacity to paired DIMM capacity
1015         // (multiply by two ==> add 1 to log2)
1016         dimm_log2_num_bits.side1++;
1017         if (dimm_log2_num_bits.side2 > 0)
1018                 dimm_log2_num_bits.side2++;
1019
1020         // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
1021         // to the total capacity of the system
1022         // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
1023
1024         total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
1025
1026         // Configure the boundary address for the row on side 1
1027         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1),
1028                           total_dram_64M_multiple);
1029
1030         // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
1031         // (as a multiple of 64 MB) to the total capacity of the system
1032         if (dimm_log2_num_bits.side2 >= 29)
1033                 total_dram_64M_multiple +=
1034                     (1 << (dimm_log2_num_bits.side2 - 29));
1035
1036         // Configure the boundary address for the row (if any) on side 2
1037         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1),
1038                           total_dram_64M_multiple);
1039
1040         // Update boundaries for rows subsequent to these.
1041         // These settings will be overridden by a subsequent call if a populated physical slot exists
1042
1043         for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1044                 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1),
1045                                   total_dram_64M_multiple);
1046                 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1),
1047                                   total_dram_64M_multiple);
1048         }
1049
1050         return total_dram_64M_multiple;
1051 }
1052
1053 /**
1054  * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).
1055  *
1056  * If necessary, set up a remap window so we don't waste DRAM that ordinarily
1057  * would lie behind addresses reserved for memory-mapped I/O.
1058  *
1059  * @param ctrl PCI addresses of memory controller functions, and SMBus
1060  *             addresses of DIMM slots on the mainboard.
1061  * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
1062  */
1063 static void configure_e7501_ram_addresses(const struct mem_controller
1064                                           *ctrl, uint8_t dimm_mask)
1065 {
1066         int i;
1067         uint8_t total_dram_64M_multiple = 0;
1068
1069         // Configure the E7501's DRAM row boundaries
1070         // Start by zeroing out the temporary initial configuration
1071         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
1072         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
1073
1074         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1075
1076                 uint16_t dimm_socket_address = ctrl->channel0[i];
1077                 struct dimm_size sz;
1078
1079                 if (!(dimm_mask & (1 << i)))
1080                         continue;       // This DIMM not present
1081
1082                 sz = spd_get_dimm_size(dimm_socket_address);
1083
1084                 RAM_DEBUG_MESSAGE("dimm size =");
1085                 RAM_DEBUG_HEX32((u32)sz.side1);
1086                 RAM_DEBUG_MESSAGE(" ");
1087                 RAM_DEBUG_HEX32((u32)sz.side2);
1088                 RAM_DEBUG_MESSAGE("\n");
1089
1090                 if (sz.side1 == 0)
1091                         die("Bad SPD value\n");
1092
1093                 total_dram_64M_multiple =
1094                     configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
1095         }
1096
1097         // Configure the Top Of Low Memory (TOLM) in the E7501
1098         // This address must be a multiple of 128 MB that is less than 4 GB.
1099         // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1100         //               in the highest 5 bits.
1101
1102         // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1103         // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1104         // such as flash and memory-mapped I/O.
1105
1106         // If there is more than 3 GB of DRAM, we define a remap window which
1107         // makes the DRAM "behind" the reserved region available above the top of physical
1108         // memory.
1109
1110         // NOTE: 0xC0000000 / (64 MB) == 0x30
1111
1112         if (total_dram_64M_multiple <= 0x30) {
1113
1114                 // <= 3 GB total RAM
1115
1116                 /* I should really adjust all of this in C after I have resources
1117                  * to all of the pci devices.
1118                  */
1119
1120                 // Round up to 128MB granularity
1121                 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1122
1123                 uint8_t total_dram_128M_multiple =
1124                     (total_dram_64M_multiple + 1) >> 1;
1125
1126                 // Convert to high 16 bits of address
1127                 uint16_t top_of_low_memory =
1128                     total_dram_128M_multiple << 11;
1129
1130                 pci_write_config16(PCI_DEV(0, 0, 0), TOLM,
1131                                    top_of_low_memory);
1132
1133         } else {
1134
1135                 // > 3 GB total RAM
1136
1137                 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1138                 uint16_t remap_base = total_dram_64M_multiple;  // A[25:0] == 0
1139                 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1;      // A[25:0] == 0xF
1140
1141                 // Put TOLM at 3 GB
1142
1143                 pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
1144
1145                 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1146                 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1147                 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1148                 //               (i.e. a multiple of 64 MB) in the lowest 10 bits.
1149                 // NOTE: 0x100000000 / (64 MB) == 0x40
1150
1151                 if (total_dram_64M_multiple < 0x40) {
1152                         remap_base = 0x40;      // 0x100000000
1153                         remap_limit =
1154                             0x40 + (total_dram_64M_multiple - 0x30) - 1;
1155                 }
1156
1157                 pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE,
1158                                    remap_base);
1159                 pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT,
1160                                    remap_limit);
1161         }
1162 }
1163
1164 /**
1165  * If we're configured to use ECC, initialize the SDRAM and clear the E7501's
1166  * ECC error flags.
1167  */
1168 static void initialize_ecc(void)
1169 {
1170         uint32_t dram_controller_mode;
1171
1172         /* Test to see if ECC support is enabled */
1173         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1174         dram_controller_mode >>= 20;
1175         dram_controller_mode &= 3;
1176         if (dram_controller_mode == 2) {
1177                 uint8_t byte;
1178
1179                 RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
1180                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x01);
1181
1182                 // Wait for scrub cycle to complete
1183                 do {
1184                         byte =
1185                             pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
1186                 } while ((byte & 0x08) == 0);
1187
1188                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, (byte & 0xfc) | 0x04);
1189                 RAM_DEBUG_MESSAGE("ECC state initialized.\n");
1190
1191                 /* Clear the ECC error bits */
1192                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
1193                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
1194
1195                 // Clear DRAM Interface error bits (write-one-clear)
1196                 pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18);
1197                 pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18);
1198         }
1199
1200 }
1201
1202 /**
1203  * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#
1204  * latency, which is assumed to have been programmed already), based on the
1205  * parameters of the various installed DIMMs.
1206  *
1207  * @param ctrl PCI addresses of memory controller functions, and SMBus
1208  *             addresses of DIMM slots on the mainboard.
1209  * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
1210  */
1211 static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
1212                                         uint8_t dimm_mask)
1213 {
1214         int i;
1215         uint32_t dram_timing;
1216         int value;
1217         uint8_t slowest_row_precharge = 0;
1218         uint8_t slowest_ras_cas_delay = 0;
1219         uint8_t slowest_active_to_precharge_delay = 0;
1220         uint32_t current_cas_latency =
1221             pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
1222
1223         // CAS# latency must be programmed beforehand
1224         ASSERT((current_cas_latency == DRT_CAS_2_0)
1225                || (current_cas_latency == DRT_CAS_2_5));
1226
1227         // Each timing parameter is determined by the slowest DIMM
1228
1229         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1230                 uint16_t dimm_socket_address;
1231
1232                 if (!(dimm_mask & (1 << i)))
1233                         continue;       // This DIMM not present
1234
1235                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1236                         dimm_socket_address = ctrl->channel0[i];
1237                 else
1238                         dimm_socket_address =
1239                             ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1240
1241                 value =
1242                     spd_read_byte(dimm_socket_address,
1243                                   SPD_MIN_ROW_PRECHARGE_TIME);
1244                 if (value < 0)
1245                         goto hw_err;
1246                 if (value > slowest_row_precharge)
1247                         slowest_row_precharge = value;
1248
1249                 value =
1250                     spd_read_byte(dimm_socket_address,
1251                                   SPD_MIN_RAS_TO_CAS_DELAY);
1252                 if (value < 0)
1253                         goto hw_err;
1254                 if (value > slowest_ras_cas_delay)
1255                         slowest_ras_cas_delay = value;
1256
1257                 value =
1258                     spd_read_byte(dimm_socket_address,
1259                                   SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1260                 if (value < 0)
1261                         goto hw_err;
1262                 if (value > slowest_active_to_precharge_delay)
1263                         slowest_active_to_precharge_delay = value;
1264         }
1265
1266         // NOTE for timing parameters:
1267         //              At 133 MHz, 1 clock == 7.52 ns
1268
1269         /* Read the initial state */
1270         dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1271
1272         /* Trp */
1273
1274         // E7501 supports only 2 or 3 clocks for tRP
1275         if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
1276                 die("unsupported DIMM tRP");    // > 22.5 ns: 4 or more clocks
1277         else if (slowest_row_precharge > (15 << 2))
1278                 dram_timing &= ~(1 << 0);       // > 15.0 ns: 3 clocks
1279         else
1280                 dram_timing |= (1 << 0);        // <= 15.0 ns: 2 clocks
1281
1282         /*  Trcd */
1283
1284         // E7501 supports only 2 or 3 clocks for tRCD
1285         // Use the same value for both read & write
1286         dram_timing &= ~((1 << 3) | (3 << 1));
1287         if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
1288                 die("unsupported DIMM tRCD");   // > 22.5 ns: 4 or more clocks
1289         else if (slowest_ras_cas_delay > (15 << 2))
1290                 dram_timing |= (2 << 1);        // > 15.0 ns: 3 clocks
1291         else
1292                 dram_timing |= ((1 << 3) | (3 << 1));   // <= 15.0 ns: 2 clocks
1293
1294         /* Tras */
1295
1296         // E7501 supports only 5, 6, or 7 clocks for tRAS
1297         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1298         dram_timing &= ~(3 << 9);
1299
1300         if (slowest_active_to_precharge_delay > 52)
1301                 die("unsupported DIMM tRAS");   // > 52 ns:      8 or more clocks
1302         else if (slowest_active_to_precharge_delay > 45)
1303                 dram_timing |= (0 << 9);        // 46-52 ns: 7 clocks
1304         else if (slowest_active_to_precharge_delay > 37)
1305                 dram_timing |= (1 << 9);        // 38-45 ns: 6 clocks
1306         else
1307                 dram_timing |= (2 << 9);        // < 38 ns:      5 clocks
1308
1309         /* Trd */
1310
1311         /* Set to a 7 clock read delay. This is for 133Mhz
1312          *  with a CAS latency of 2.5  if 2.0 a 6 clock
1313          *  delay is good  */
1314
1315         dram_timing &= ~(7 << 24);      // 7 clocks
1316         if (current_cas_latency == DRT_CAS_2_0)
1317                 dram_timing |= (1 << 24);       // 6 clocks
1318
1319         /*
1320          * Back to Back Read-Write Turn Around
1321          */
1322         /* Set to a 5 clock back to back read to write turn around.
1323          *  4 is a good delay if the CAS latency is 2.0 */
1324
1325         dram_timing &= ~(1 << 28);      // 5 clocks
1326         if (current_cas_latency == DRT_CAS_2_0)
1327                 dram_timing |= (1 << 28);       // 4 clocks
1328
1329         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1330
1331         return;
1332
1333       hw_err:
1334         die(SPD_ERROR);
1335 }
1336
1337 /**
1338  * Determine the shortest CAS# latency that the E7501 and all DIMMs have in
1339  * common, and program the E7501 to use it.
1340  *
1341  * @param ctrl PCI addresses of memory controller functions, and SMBus
1342  *             addresses of DIMM slots on the mainboard.
1343  * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1344  */
1345 static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
1346                                         uint8_t dimm_mask)
1347 {
1348         int i;
1349         int value;
1350         uint32_t dram_timing;
1351         uint16_t maybe_dram_read_timing;
1352         uint32_t dword;
1353
1354         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1355         // NOTE: E7501 supports only 2.0 and 2.5
1356         uint32_t system_compatible_cas_latencies =
1357             SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1358         uint32_t current_cas_latency;
1359         uint32_t dimm_compatible_cas_latencies;
1360
1361         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1362
1363                 uint16_t dimm_socket_address;
1364
1365                 if (!(dimm_mask & (1 << i)))
1366                         continue;       // This DIMM not usable
1367
1368                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1369                         dimm_socket_address = ctrl->channel0[i];
1370                 else
1371                         dimm_socket_address =
1372                             ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1373
1374                 value =
1375                     spd_read_byte(dimm_socket_address,
1376                                   SPD_ACCEPTABLE_CAS_LATENCIES);
1377                 if (value < 0)
1378                         goto hw_err;
1379
1380                 dimm_compatible_cas_latencies = value & 0x7f;   // Start with all supported by DIMM
1381                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1382
1383                 // Can we support the highest CAS# latency?
1384
1385                 value =
1386                     spd_read_byte(dimm_socket_address,
1387                                   SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1388                 if (value < 0)
1389                         goto hw_err;
1390
1391                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1392                 if (value > 0x75) {
1393                         // Our bus is too fast for this CAS# latency
1394                         // Remove it from the bitmask of those supported by the DIMM that are compatible
1395                         dimm_compatible_cas_latencies &= ~current_cas_latency;
1396                 }
1397                 // Can we support the next-highest CAS# latency (max - 0.5)?
1398
1399                 current_cas_latency >>= 1;
1400                 if (current_cas_latency != 0) {
1401                         value =
1402                             spd_read_byte(dimm_socket_address,
1403                                           SPD_SDRAM_CYCLE_TIME_2ND);
1404                         if (value < 0)
1405                                 goto hw_err;
1406                         if (value > 0x75)
1407                                 dimm_compatible_cas_latencies &=
1408                                     ~current_cas_latency;
1409                 }
1410                 // Can we support the next-highest CAS# latency (max - 1.0)?
1411                 current_cas_latency >>= 1;
1412                 if (current_cas_latency != 0) {
1413                         value =
1414                             spd_read_byte(dimm_socket_address,
1415                                           SPD_SDRAM_CYCLE_TIME_3RD);
1416                         if (value < 0)
1417                                 goto hw_err;
1418                         if (value > 0x75)
1419                                 dimm_compatible_cas_latencies &=
1420                                     ~current_cas_latency;
1421                 }
1422                 // Restrict the system to CAS# latencies compatible with this DIMM
1423                 system_compatible_cas_latencies &=
1424                     dimm_compatible_cas_latencies;
1425
1426                 /* go to the next DIMM */
1427         }
1428
1429         /* After all of the arduous calculation setup with the fastest
1430          * cas latency I can use.
1431          */
1432
1433         dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1434         dram_timing &= ~(DRT_CAS_MASK);
1435
1436         maybe_dram_read_timing =
1437             pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
1438         maybe_dram_read_timing &= 0xF000;
1439
1440         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1441                 dram_timing |= DRT_CAS_2_0;
1442                 maybe_dram_read_timing |= 0x0222;
1443         } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1444
1445                 uint32_t dram_row_attributes =
1446                     pci_read_config32(PCI_DEV(0, 0, 0), DRA);
1447
1448                 dram_timing |= DRT_CAS_2_5;
1449
1450                 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1451                 // different value if all DIMM slots are populated
1452
1453                 if ((dram_row_attributes & 0xff)
1454                     && (dram_row_attributes & 0xff00)
1455                     && (dram_row_attributes & 0xff0000)
1456                     && (dram_row_attributes & 0xff000000)) {
1457
1458                         // All slots populated
1459                         maybe_dram_read_timing |= 0x0882;
1460                 } else {
1461                         // Some unpopulated slots
1462                         maybe_dram_read_timing |= 0x0662;
1463                 }
1464         } else
1465                 die("No CAS# latencies compatible with all DIMMs!!\n");
1466
1467         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1468
1469         /* set master DLL reset */
1470         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
1471         dword |= (1 << 26);
1472         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1473         /* patch try register 88 is undocumented tnz */
1474         dword &= 0x0ca17fff;
1475         dword |= 0xd14a5000;
1476         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1477
1478         pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
1479                            maybe_dram_read_timing);
1480
1481         /* clear master DLL reset */
1482         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
1483         dword &= ~(1 << 26);
1484         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1485
1486         return;
1487
1488 hw_err:
1489         die(SPD_ERROR);
1490 }
1491
1492 /**
1493  * Configure the refresh interval so that we refresh no more often than
1494  * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs
1495  * don't support it.
1496  *
1497  * @param ctrl PCI addresses of memory controller functions, and SMBus
1498  *             addresses of DIMM slots on the mainboard.
1499  * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1500  */
1501 static void configure_e7501_dram_controller_mode(const struct
1502                                                  mem_controller *ctrl,
1503                                                  uint8_t dimm_mask)
1504 {
1505         int i;
1506
1507         // Initial settings
1508         uint32_t controller_mode =
1509             pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1510         uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1511
1512         // Code below assumes that most aggressive settings are in
1513         // force when we are called, either via E7501 reset defaults
1514         // or by sdram_set_registers():
1515         //      - ECC enabled
1516         //      - No refresh
1517
1518         ASSERT((controller_mode & (3 << 20)) == (2 << 20));     // ECC
1519         ASSERT(!(controller_mode & (7 << 8)));  // Refresh
1520
1521         /* Walk through _all_ dimms and find the least-common denominator for:
1522          *  - ECC support
1523          *  - refresh rates
1524          */
1525
1526         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1527
1528                 uint32_t dimm_refresh_mode;
1529                 int value;
1530                 uint16_t dimm_socket_address;
1531
1532                 if (!(dimm_mask & (1 << i))) {
1533                         continue;       // This DIMM not usable
1534                 }
1535
1536                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1537                         dimm_socket_address = ctrl->channel0[i];
1538                 else
1539                         dimm_socket_address =
1540                             ctrl->channel1[i -
1541                                            MAX_DIMM_SOCKETS_PER_CHANNEL];
1542
1543                 // Disable ECC mode if any one of the DIMMs does not support ECC
1544                 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1545
1546                 value =
1547                     spd_read_byte(dimm_socket_address,
1548                                   SPD_DIMM_CONFIG_TYPE);
1549                 die_on_spd_error(value);
1550                 if (value != ERROR_SCHEME_ECC) {
1551                         controller_mode &= ~(3 << 20);
1552                 }
1553
1554                 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1555                 die_on_spd_error(value);
1556                 value &= 0x7f;  // Mask off self-refresh bit
1557                 if (value > MAX_SPD_REFRESH_RATE) {
1558                         print_err("unsupported refresh rate\n");
1559                         continue;
1560                 }
1561                 // Get the appropriate E7501 refresh mode for this DIMM
1562                 dimm_refresh_mode = refresh_rate_map[value];
1563                 if (dimm_refresh_mode > 7) {
1564                         print_err("unsupported refresh rate\n");
1565                         continue;
1566                 }
1567                 // If this DIMM requires more frequent refresh than others,
1568                 // update the system setting
1569                 if (refresh_frequency[dimm_refresh_mode] >
1570                     refresh_frequency[system_refresh_mode])
1571                         system_refresh_mode = dimm_refresh_mode;
1572
1573 #ifdef SUSPICIOUS_LOOKING_CODE
1574 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1575 //                       than the clock period of the memory controller. Also, no other northbridge
1576 //                       looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
1577
1578                 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1579                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1580                 value =
1581                     spd_read_byte(dimm_socket_address,
1582                                   SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
1583                 die_on_spd_error(value);
1584                 if (value >= 0xa0) {    /* At 133MHz this constant should be 0x75 */
1585                         controller_mode &= ~(1 << 16);  /* Use two clock cyles instead of one */
1586                 }
1587 #endif
1588
1589                 /* go to the next DIMM */
1590         }
1591
1592         controller_mode |= (system_refresh_mode << 8);
1593
1594         // Configure the E7501
1595         pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
1596 }
1597
1598 /**
1599  * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM
1600  * parameters read via SPD. This tells the controller the width of the SDRAM
1601  * chips on each DIMM side (x4 or x8) and the page size of each DIMM side
1602  * (4, 8, 16, or 32 KB).
1603  *
1604  * @param ctrl PCI addresses of memory controller functions, and SMBus
1605  *             addresses of DIMM slots on the mainboard.
1606  * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1607  */
1608 static void configure_e7501_row_attributes(const struct mem_controller
1609                                            *ctrl, uint8_t dimm_mask)
1610 {
1611         int i;
1612         uint32_t row_attributes = 0;
1613
1614         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1615
1616                 uint16_t dimm_socket_address = ctrl->channel0[i];
1617                 struct dimm_size page_size;
1618                 struct dimm_size sdram_width;
1619
1620                 if (!(dimm_mask & (1 << i)))
1621                         continue;       // This DIMM not usable
1622
1623                 // Get the relevant parameters via SPD
1624                 page_size = sdram_spd_get_page_size(dimm_socket_address);
1625                 sdram_width = sdram_spd_get_width(dimm_socket_address);
1626
1627                 // Update the DRAM Row Attributes.
1628                 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1629                 // NOTE: 8 Kb = 2^13
1630                 row_attributes |= (page_size.side1 - 13) << (i << 3);   // Side 1 of each DIMM is an EVEN row
1631
1632                 if (sdram_width.side2 > 0)
1633                         row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4);     // Side 2 is ODD
1634
1635                 // Set x4 flags if appropriate
1636                 if (sdram_width.side1 == 4) {
1637                         row_attributes |= 0x08 << (i << 3);
1638                 }
1639
1640                 if (sdram_width.side2 == 4) {
1641                         row_attributes |= 0x08 << ((i << 3) + 4);
1642                 }
1643
1644                 /* go to the next DIMM */
1645         }
1646
1647         /* Write the new row attributes register */
1648         pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
1649 }
1650
1651 /*
1652  * Enable clock signals for populated DIMM sockets and disable them for
1653  * unpopulated sockets (to reduce EMI).
1654  *
1655  * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
1656  */
1657 static void enable_e7501_clocks(uint8_t dimm_mask)
1658 {
1659         int i;
1660         uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
1661
1662         pci_write_config8(PCI_DEV(0,0,0), 0x8e, 0xb0);
1663
1664         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1665
1666                 uint8_t socket_mask = 1 << i;
1667
1668                 if (dimm_mask & socket_mask)
1669                         clock_disable &= ~socket_mask;  // DIMM present, enable clock
1670                 else
1671                         clock_disable |= socket_mask;   // DIMM absent, disable clock
1672         }
1673
1674         pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
1675 }
1676
1677 /* DIMM-dedependent configuration functions */
1678
1679 /**
1680  * DDR Receive FIFO RE-Sync (?)
1681  */
1682 static void RAM_RESET_DDR_PTR(void)
1683 {
1684         uint8_t byte;
1685         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1686         byte |= (1 << 4);
1687         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1688
1689         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1690         byte &= ~(1 << 4);
1691         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1692 }
1693
1694 /**
1695  * Set E7501 registers that are either independent of DIMM specifics, or
1696  * establish default settings that will be overridden when we learn the
1697  * specifics.
1698  *
1699  * This sets PCI configuration registers to known good values based on the
1700  * table 'constant_register_values', which are a triple of configuration
1701  * register offset, mask, and bits to set.
1702  */
1703 static void ram_set_d0f0_regs(void)
1704 {
1705         int i;
1706         int num_values = ARRAY_SIZE(constant_register_values);
1707
1708         ASSERT((num_values % 3) == 0);  // Bad table?
1709
1710         for (i = 0; i < num_values; i += 3) {
1711
1712                 uint32_t register_offset = constant_register_values[i];
1713                 uint32_t bits_to_mask = constant_register_values[i + 1];
1714                 uint32_t bits_to_set = constant_register_values[i + 2];
1715                 uint32_t register_value;
1716
1717                 // It's theoretically possible to set values for something other than D0:F0,
1718                 // but it's not typically done here
1719                 ASSERT(!(register_offset & 0xFFFFFF00));
1720
1721                 // bits_to_mask and bits_to_set should not reference the same bits
1722                 // Again, not strictly an error, but flagged as a potential bug
1723                 ASSERT((bits_to_mask & bits_to_set) == 0);
1724
1725                 register_value =
1726                     pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
1727                 register_value &= bits_to_mask;
1728                 register_value |= bits_to_set;
1729
1730                 pci_write_config32(PCI_DEV(0, 0, 0), register_offset,
1731                                    register_value);
1732         }
1733 }
1734
1735 /**
1736  * Copy 64 bytes from one location to another.
1737  *
1738  * @param src_addr TODO
1739  * @param dst_addr TODO
1740  */
1741 static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
1742 {
1743         int i;
1744         for (i = 0; i < 8; i++) {
1745                 write32(dst_addr, *src_addr);
1746                 src_addr++;
1747                 dst_addr += sizeof(uint32_t);
1748         }
1749 }
1750
1751 /**
1752  * Set the E7501's (undocumented) RCOMP registers.
1753  *
1754  * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,
1755  * RCOMP registers appear to affect drive strength, pullup/pulldown offset,
1756  * and slew rate of various signal groups.
1757  *
1758  * Comments below are conjecture based on apparent similarity between the
1759  * E7501 and these two chips.
1760  */
1761 static void ram_set_rcomp_regs(void)
1762 {
1763         uint32_t dword;
1764         uint8_t maybe_strength_control, revision;
1765
1766         RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
1767
1768         /*enable access to the rcomp bar */
1769         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1770         dword |= (1 << 22);
1771         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1772
1773         // Set the RCOMP MMIO base address
1774         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
1775
1776         // Block RCOMP updates while we configure the registers
1777         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1778         dword |= (1 << 9);
1779         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1780
1781         /* Begin to write the RCOMP registers */
1782         write8(RCOMP_MMIO + 0x2c, 0x0);
1783
1784         // Set CMD and DQ/DQS strength to 2x (?)
1785         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1786         maybe_strength_control |= 0x40;
1787         write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1788         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1789         write16(RCOMP_MMIO + 0x42, 0);
1790
1791         // Set CMD and DQ/DQS strength to 2x (?)
1792         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0xF8;
1793         maybe_strength_control |= 0x04;
1794         write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1795         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x60);
1796         write16(RCOMP_MMIO + 0x40, 0);
1797
1798         // Set RCVEnOut# strength to 2x (?)
1799         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1800         maybe_strength_control |= 0x04;
1801         write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1802         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1803         write16(RCOMP_MMIO + 0x50, 0);
1804
1805         // Set CS# strength for x4 SDRAM to 2x (?)
1806         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x88;
1807         maybe_strength_control |= 0x04;
1808         write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1809         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1810         write16(RCOMP_MMIO + 0x48, 0);
1811
1812         // Set CS# strength for x4 SDRAM to 2x (?)
1813         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x8F;
1814         maybe_strength_control |= 0x40;
1815         write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1816         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x160);
1817         write16(RCOMP_MMIO + 0x4a, 0);
1818
1819         // Set CKE strength for x4 SDRAM to 2x (?)
1820         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x88;
1821         maybe_strength_control |= 0x04;
1822         write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1823         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1824         write16(RCOMP_MMIO + 0x44, 0);
1825
1826         // Set CKE strength for x4 SDRAM to 2x (?)
1827         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x8F;
1828         maybe_strength_control |= 0x40;
1829         write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1830         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xc0);
1831         write16(RCOMP_MMIO + 0x46, 0);
1832
1833         // Set CK strength for x4 SDRAM to 1x (?)
1834         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x88;
1835         maybe_strength_control |= 0x01;
1836         write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1837         write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1838         write16(RCOMP_MMIO + 0x4c, 0);
1839
1840         // Set CK strength for x4 SDRAM to 1x (?)
1841         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x8F;
1842         maybe_strength_control |= 0x10;
1843         write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1844         write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
1845         write16(RCOMP_MMIO + 0x4e, 0);
1846
1847
1848         dword = read32(RCOMP_MMIO + 0x400);
1849         dword &= 0x7f7fffff;
1850         write32(RCOMP_MMIO + 0x400, dword);
1851
1852         dword = read32(RCOMP_MMIO + 0x408);
1853         dword &= 0x7f7fffff;
1854         write32(RCOMP_MMIO + 0x408, dword);
1855
1856         ram_handle_d060_1();
1857
1858         dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
1859         dword &= 0x3fffffff;
1860         pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
1861
1862         revision = pci_read_config8(PCI_DEV(0,0,0), 0x08);
1863         if (revision >= 3) {
1864                 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1865                 dword &= ~0x100;
1866                 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1867                 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1868                 dword |= 0x500;
1869                 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1870         }
1871         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1872         dword &= ~0x203;
1873         dword |= 0x401;
1874         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1875
1876         /* Wait 40 usec */
1877         SLOW_DOWN_IO;
1878
1879         // Clear the RCOMP MMIO base address
1880         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, 0);
1881         /*disable access to the rcomp bar */
1882         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1883         dword &= ~(1 << 22);
1884         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1885
1886 }
1887
1888 /*-----------------------------------------------------------------------------
1889 Public interface:
1890 -----------------------------------------------------------------------------*/
1891
1892 /**
1893  * Go through the JEDEC initialization sequence for all DIMMs, then enable
1894  * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up
1895  * and running.
1896  *
1897  * @param controllers Not used.
1898  * @param ctrl PCI addresses of memory controller functions, and SMBus
1899  *             addresses of DIMM slots on the mainboard.
1900  */
1901 static void sdram_enable(int controllers,
1902                          const struct mem_controller *ctrl)
1903 {
1904         uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
1905         uint32_t dram_controller_mode;
1906
1907         if (dimm_mask == 0)
1908                 return;
1909
1910         /* 1 & 2 Power up and start clocks */
1911         RAM_DEBUG_MESSAGE("Ram Enable 1\n");
1912         RAM_DEBUG_MESSAGE("Ram Enable 2\n");
1913
1914         /* A 200us delay is needed */
1915         DO_DELAY; EXTRA_DELAY;
1916
1917         /* 3. Apply NOP */
1918         RAM_DEBUG_MESSAGE("Ram Enable 3\n");
1919         do_ram_command(RAM_COMMAND_NOP, 0);
1920         EXTRA_DELAY;
1921
1922         /* 4 Precharge all */
1923         RAM_DEBUG_MESSAGE("Ram Enable 4\n");
1924         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1925         EXTRA_DELAY;
1926         /* wait until the all banks idle state... */
1927
1928         /* 5. Issue EMRS to enable DLL */
1929         RAM_DEBUG_MESSAGE("Ram Enable 5\n");
1930         do_ram_command(RAM_COMMAND_EMRS,
1931                        SDRAM_EXTMODE_DLL_ENABLE |
1932                        SDRAM_EXTMODE_DRIVE_NORMAL);
1933         EXTRA_DELAY;
1934
1935         /* 6. Reset DLL */
1936         RAM_DEBUG_MESSAGE("Ram Enable 6\n");
1937         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1938         EXTRA_DELAY;
1939         /* Ensure a 200us delay between the DLL reset in step 6 and the final
1940          * mode register set in step 9.
1941          * Infineon needs this before any other command is sent to the ram.
1942          */
1943         DO_DELAY; EXTRA_DELAY;
1944
1945         /* 7 Precharge all */
1946         RAM_DEBUG_MESSAGE("Ram Enable 7\n");
1947         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1948         EXTRA_DELAY;
1949
1950         /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1951         RAM_DEBUG_MESSAGE("Ram Enable 8\n");
1952         do_ram_command(RAM_COMMAND_CBR, 0);
1953         EXTRA_DELAY;
1954         do_ram_command(RAM_COMMAND_CBR, 0);
1955         EXTRA_DELAY;
1956
1957         /* And for good luck 6 more CBRs */
1958         do_ram_command(RAM_COMMAND_CBR, 0);
1959         EXTRA_DELAY;
1960         do_ram_command(RAM_COMMAND_CBR, 0);
1961         EXTRA_DELAY;
1962         do_ram_command(RAM_COMMAND_CBR, 0);
1963         EXTRA_DELAY;
1964         do_ram_command(RAM_COMMAND_CBR, 0);
1965         EXTRA_DELAY;
1966         do_ram_command(RAM_COMMAND_CBR, 0);
1967         EXTRA_DELAY;
1968         do_ram_command(RAM_COMMAND_CBR, 0);
1969         EXTRA_DELAY;
1970
1971         /* 9 mode register set */
1972         RAM_DEBUG_MESSAGE("Ram Enable 9\n");
1973         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1974         EXTRA_DELAY;
1975
1976         /* 10 DDR Receive FIFO RE-Sync */
1977         RAM_DEBUG_MESSAGE("Ram Enable 10\n");
1978         RAM_RESET_DDR_PTR();
1979         EXTRA_DELAY;
1980
1981         /* 11 normal operation */
1982         RAM_DEBUG_MESSAGE("Ram Enable 11\n");
1983         do_ram_command(RAM_COMMAND_NORMAL, 0);
1984         EXTRA_DELAY;
1985
1986         // Reconfigure the row boundaries and Top of Low Memory
1987         // to match the true size of the DIMMs
1988         configure_e7501_ram_addresses(ctrl, dimm_mask);
1989
1990         /* Finally enable refresh */
1991         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1992         dram_controller_mode |= (1 << 29);
1993         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1994         EXTRA_DELAY;
1995         initialize_ecc();
1996
1997         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);        /* FCS_EN */
1998         dram_controller_mode |= (1 << 17);      // NOTE: undocumented reserved bit
1999         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
2000
2001         RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
2002         DUMPNORTH();
2003 }
2004
2005 /**
2006  * Configure SDRAM controller parameters that depend on characteristics of the
2007  * DIMMs installed in the system. These characteristics are read from the
2008  * DIMMs via the standard Serial Presence Detect (SPD) interface.
2009  *
2010  * @param ctrl PCI addresses of memory controller functions, and SMBus
2011  *             addresses of DIMM slots on the mainboard.
2012  */
2013 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
2014 {
2015         uint8_t dimm_mask;
2016
2017         RAM_DEBUG_MESSAGE("Reading SPD data...\n");
2018
2019         dimm_mask = spd_get_supported_dimms(ctrl);
2020
2021         if (dimm_mask == 0) {
2022                 print_debug("No usable memory for this controller\n");
2023         } else {
2024                 enable_e7501_clocks(dimm_mask);
2025
2026                 RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
2027
2028                 configure_e7501_row_attributes(ctrl, dimm_mask);
2029                 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
2030                 configure_e7501_cas_latency(ctrl, dimm_mask);
2031                 RAM_RESET_DDR_PTR();
2032
2033                 configure_e7501_dram_timing(ctrl, dimm_mask);
2034                 DO_DELAY;
2035                 RAM_DEBUG_MESSAGE("done\n");
2036         }
2037
2038         /* NOTE: configure_e7501_ram_addresses() is NOT called here.
2039          * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
2040          * even though the default mapping is almost certainly incorrect.
2041          * The default mapping makes it easy to initialize all of the DIMMs
2042          * even if the total system memory is > 4 GB.
2043          *
2044          * Save the dimm_mask for when sdram_enable is called, so it can call
2045          * configure_e7501_ram_addresses() without having to regenerate the bitmask
2046          * of usable DIMMs.
2047          */
2048         pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
2049 }
2050
2051 /**
2052  * Do basic RAM setup that does NOT depend on serial presence detect
2053  * information (i.e. independent of DIMM specifics).
2054  *
2055  * @param ctrl PCI addresses of memory controller functions, and SMBus
2056  *             addresses of DIMM slots on the mainboard.
2057  */
2058 static void sdram_set_registers(const struct mem_controller *ctrl)
2059 {
2060         RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
2061         DUMPNORTH();
2062
2063         ram_set_rcomp_regs();
2064         ram_set_d0f0_regs();
2065         ram_handle_d060_2();
2066 }
2067