src/northbridge/intel/e7505/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/cpu.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11
  12 #if CONFIG_WRITE_HIGH_TABLES==1
  13 #include <cbmem.h>
  14 #endif
  15
  16 static void pci_domain_set_resources(device_t dev)
  17 {
  18         device_t mc_dev;
  19         uint32_t pci_tolm;
  20
  21         pci_tolm = find_pci_tolm(dev->link_list);
  22         mc_dev = dev->link_list->children;
  23         if (mc_dev) {
  24                 /* Figure out which areas are/should be occupied by RAM.
  25                  * This is all computed in kilobytes and converted to/from
  26                  * the memory controller right at the edges.
  27                  * Having different variables in different units is
  28                  * too confusing to get right.  Kilobytes are good up to
  29                  * 4 Terabytes of RAM...
  30                  */
  31                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  32                 unsigned long tomk, tolmk;
  33                 unsigned long remapbasek, remaplimitk;
  34                 int idx;
  35
  36                 /* Get the value of the highest DRB. This tells the end of
  37                  * the physical memory.  The units are ticks of 64MB
  38                  * i.e. 1 means 64MB.
  39                  */
  40                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  41                 /* Compute the top of Low memory */
  42                 tolmk = pci_tolm >> 10;
  43                 if (tolmk >= tomk) {
  44                         /* The PCI hole does not overlap memory
  45                          * we won't use the remap window.
  46                          */
  47                         tolmk = tomk;
  48                         remapbasek   = 0x3ff << 16;
  49                         remaplimitk  = 0 << 16;
  50                 }
  51                 else {
  52                         /* The PCI memory hole overlaps memory
  53                          * setup the remap window.
  54                          */
  55                         /* Find the bottom of the remap window
  56                          * is it above 4G?
  57                          */
  58                         remapbasek = 4*1024*1024;
  59                         if (tomk > remapbasek) {
  60                                 remapbasek = tomk;
  61                         }
  62                         /* Find the limit of the remap window */
  63                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
  64                 }
  65                 /* Write the ram configuration registers,
  66                  * preserving the reserved bits.
  67                  */
  68                 tolm_r = pci_read_config16(mc_dev, 0xc4);
  69                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
  70                 pci_write_config16(mc_dev, 0xc4, tolm_r);
  71
  72                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
  73                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
  74                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
  75
  76                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
  77                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
  78                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
  79
  80                 /* Report the memory regions */
  81                 idx = 10;
  82                 ram_resource(dev, idx++, 0, 640);
  83                 ram_resource(dev, idx++, 768, tolmk - 768);
  84                 if (tomk > 4*1024*1024) {
  85                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
  86                 }
  87                 if (remaplimitk >= remapbasek) {
  88                         ram_resource(dev, idx++, remapbasek,
  89                                 (remaplimitk + 64*1024) - remapbasek);
  90                 }
  91
  92 #if CONFIG_WRITE_HIGH_TABLES==1
  93                 /* Leave some space for ACPI, PIRQ and MP tables */
  94                 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
  95                 high_tables_size = HIGH_MEMORY_SIZE;
  96 #endif
  97         }
  98         assign_resources(dev->link_list);
  99 }
 100
 101 static struct device_operations pci_domain_ops = {
 102         .read_resources   = pci_domain_read_resources,
 103         .set_resources    = pci_domain_set_resources,
 104         .enable_resources = NULL,
 105         .init             = NULL,
 106         .scan_bus         = pci_domain_scan_bus,
 107         .ops_pci_bus      = &pci_cf8_conf1,
 108 };
 109
 110 static void cpu_bus_init(device_t dev)
 111 {
 112         initialize_cpus(dev->link_list);
 113 }
 114
 115 static void cpu_bus_noop(device_t dev)
 116 {
 117 }
 118
 119 static struct device_operations cpu_bus_ops = {
 120         .read_resources   = cpu_bus_noop,
 121         .set_resources    = cpu_bus_noop,
 122         .enable_resources = cpu_bus_noop,
 123         .init             = cpu_bus_init,
 124         .scan_bus         = 0,
 125 };
 126
 127 static void enable_dev(struct device *dev)
 128 {
 129         /* Set the operations if it is a special bus type */
 130         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 131                 dev->ops = &pci_domain_ops;
 132         }
 133         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 134                 dev->ops = &cpu_bus_ops;
 135         }
 136 }
 137
 138 struct chip_operations northbridge_intel_e7501_ops = {
 139         CHIP_NAME("Intel E7501 Northbridge")
 140         .enable_dev = enable_dev,
 141 };