src/northbridge/intel/e7505/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/cpu.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "e7505.h"
  12
  13 #if CONFIG_WRITE_HIGH_TABLES==1
  14 #include <cbmem.h>
  15 #endif
  16
  17 static void pci_domain_set_resources(device_t dev)
  18 {
  19         device_t mc_dev;
  20         uint32_t pci_tolm;
  21
  22         pci_tolm = find_pci_tolm(dev->link_list);
  23         mc_dev = dev->link_list->children;
  24         if (mc_dev) {
  25                 /* Figure out which areas are/should be occupied by RAM.
  26                  * This is all computed in kilobytes and converted to/from
  27                  * the memory controller right at the edges.
  28                  * Having different variables in different units is
  29                  * too confusing to get right.  Kilobytes are good up to
  30                  * 4 Terabytes of RAM...
  31                  */
  32                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  33                 unsigned long tomk, tolmk;
  34                 unsigned long remapbasek, remaplimitk;
  35                 int idx;
  36
  37                 /* Get the value of the highest DRB. This tells the end of
  38                  * the physical memory.  The units are ticks of 64MB
  39                  * i.e. 1 means 64MB.
  40                  */
  41                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  42                 /* Compute the top of Low memory */
  43                 tolmk = pci_tolm >> 10;
  44                 if (tolmk >= tomk) {
  45                         /* The PCI hole does not overlap memory
  46                          * we won't use the remap window.
  47                          */
  48                         tolmk = tomk;
  49                         remapbasek   = 0x3ff << 16;
  50                         remaplimitk  = 0 << 16;
  51                 }
  52                 else {
  53                         /* The PCI memory hole overlaps memory
  54                          * setup the remap window.
  55                          */
  56                         /* Find the bottom of the remap window
  57                          * is it above 4G?
  58                          */
  59                         remapbasek = 4*1024*1024;
  60                         if (tomk > remapbasek) {
  61                                 remapbasek = tomk;
  62                         }
  63                         /* Find the limit of the remap window */
  64                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
  65                 }
  66                 /* Write the ram configuration registers,
  67                  * preserving the reserved bits.
  68                  */
  69                 tolm_r = pci_read_config16(mc_dev, TOLM);
  70                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
  71                 pci_write_config16(mc_dev, TOLM, tolm_r);
  72
  73                 remapbase_r = pci_read_config16(mc_dev, REMAPBASE);
  74                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
  75                 pci_write_config16(mc_dev, REMAPBASE, remapbase_r);
  76
  77                 remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT);
  78                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
  79                 pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);
  80
  81                 /* Report the memory regions */
  82                 idx = 10;
  83                 ram_resource(dev, idx++, 0, 640);
  84                 ram_resource(dev, idx++, 768, tolmk - 768);
  85                 if (tomk > 4*1024*1024) {
  86                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
  87                 }
  88                 if (remaplimitk >= remapbasek) {
  89                         ram_resource(dev, idx++, remapbasek,
  90                                 (remaplimitk + 64*1024) - remapbasek);
  91                 }
  92
  93 #if CONFIG_WRITE_HIGH_TABLES==1
  94                 /* Leave some space for ACPI, PIRQ and MP tables */
  95                 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
  96                 high_tables_size = HIGH_MEMORY_SIZE;
  97 #endif
  98         }
  99         assign_resources(dev->link_list);
 100 }
 101
 102 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 103 {
 104         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 105                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 106 }
 107
 108 static struct pci_operations intel_pci_ops = {
 109         .set_subsystem = intel_set_subsystem,
 110 };
 111
 112 static struct device_operations pci_domain_ops = {
 113         .read_resources   = pci_domain_read_resources,
 114         .set_resources    = pci_domain_set_resources,
 115         .enable_resources = NULL,
 116         .init             = NULL,
 117         .scan_bus         = pci_domain_scan_bus,
 118         .ops_pci          = &intel_pci_ops,
 119         .ops_pci_bus      = &pci_cf8_conf1,
 120 };
 121
 122 static void cpu_bus_init(device_t dev)
 123 {
 124         initialize_cpus(dev->link_list);
 125 }
 126
 127 static void cpu_bus_noop(device_t dev)
 128 {
 129 }
 130
 131 static struct device_operations cpu_bus_ops = {
 132         .read_resources   = cpu_bus_noop,
 133         .set_resources    = cpu_bus_noop,
 134         .enable_resources = cpu_bus_noop,
 135         .init             = cpu_bus_init,
 136         .scan_bus         = 0,
 137 };
 138
 139 static void enable_dev(struct device *dev)
 140 {
 141         /* Set the operations if it is a special bus type */
 142         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 143                 dev->ops = &pci_domain_ops;
 144         }
 145         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 146                 dev->ops = &cpu_bus_ops;
 147         }
 148 }
 149
 150 struct chip_operations northbridge_intel_e7505_ops = {
 151         CHIP_NAME("Intel E7505 Northbridge")
 152         .enable_dev = enable_dev,
 153 };
 154