src/northbridge/intel/e7501/raminit.c

   1 /* This was originally for the e7500, modified for e7501
   2  * The primary differences are that 7501 apparently can
   3  * support single channel RAM (i haven't tested),
   4  * CAS1.5 is no longer supported, The ECC scrubber
   5  * now supports a mode to zero RAM and init ECC in one step
   6  * and the undocumented registers at 0x80 require new
   7  * (undocumented) values determined by guesswork and
   8  * comparison w/ OEM BIOS values.
   9  * Steven James 02/06/2003
  10  */
  11
  12 /* converted to C 6/2004 yhlu */
  13
  14 #include <assert.h>
  15 #include <spd.h>
  16 #include <sdram_mode.h>
  17 #include <stdlib.h>
  18 #include "e7501.h"
  19
  20 // Uncomment this to enable run-time checking of DIMM parameters
  21 // for dual-channel operation
  22 // Unfortunately the code seems to chew up several K of space.
  23 //#define VALIDATE_DIMM_COMPATIBILITY
  24
  25 #if CONFIG_DEBUG_RAM_SETUP
  26 #define RAM_DEBUG_MESSAGE(x)    print_debug(x)
  27 #define RAM_DEBUG_HEX32(x)      print_debug_hex32(x)
  28 #define RAM_DEBUG_HEX8(x)       print_debug_hex8(x)
  29 #define DUMPNORTH()             dump_pci_device(PCI_DEV(0, 0, 0))
  30 #else
  31 #define RAM_DEBUG_MESSAGE(x)
  32 #define RAM_DEBUG_HEX32(x)
  33 #define RAM_DEBUG_HEX8(x)
  34 #define DUMPNORTH()
  35 #endif
  36
  37 #define E7501_SDRAM_MODE        (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
  38 #define SPD_ERROR               "Error reading SPD info\n"
  39
  40 // NOTE: This used to be 0x100000.
  41 //       That doesn't work on systems where A20M# is asserted, because
  42 //       attempts to access 0x1000NN end up accessing 0x0000NN.
  43 #define RCOMP_MMIO 0x200000
  44
  45 struct dimm_size {
  46         unsigned long side1;
  47         unsigned long side2;
  48 };
  49
  50 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
  51 /*                              DEFINITIONS                                       */
  52 /**********************************************************************************/
  53
  54 static const uint32_t refresh_frequency[] = {
  55         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  56          * (RMS) value (array index)
  57          * 0 == least frequent refresh (longest interval between refreshes)
  58          * [0] disabled  -> 0
  59          * [1] 15.6 usec -> 2
  60          * [2]  7.8 usec -> 3
  61          * [3] 64   usec -> 1
  62          * [4] reserved  -> 0
  63          * [5] reserved  -> 0
  64          * [6] reserved  -> 0
  65          * [7] 64 clocks -> 4
  66          */
  67         0, 2, 3, 1, 0, 0, 0, 4
  68 };
  69
  70 static const uint32_t refresh_rate_map[] = {
  71         /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
  72          * Select values (array value)
  73          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  74          * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
  75          * 64 clock (481 ns) (7) refresh.
  76          * [0] ==  15.625 us -> 15.6 us
  77          * [1] ==   3.9   us -> 481  ns
  78          * [2] ==   7.8   us ->  7.8 us
  79          * [3] ==  31.3   us -> 15.6 us
  80          * [4] ==  62.5   us -> 15.6 us
  81          * [5] == 125     us -> 64   us
  82          */
  83         1, 7, 2, 1, 1, 3
  84 };
  85
  86 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
  87
  88 // SPD parameters that must match for dual-channel operation
  89 static const uint8_t dual_channel_parameters[] = {
  90         SPD_MEMORY_TYPE,
  91         SPD_MODULE_VOLTAGE,
  92         SPD_NUM_COLUMNS,
  93         SPD_NUM_ROWS,
  94         SPD_NUM_DIMM_BANKS,
  95         SPD_PRIMARY_SDRAM_WIDTH,
  96         SPD_NUM_BANKS_PER_SDRAM
  97 };
  98
  99         /*
 100          * Table:       constant_register_values
 101          */
 102 static const long constant_register_values[] = {
 103         /* SVID - Subsystem Vendor Identification Register
 104          * 0x2c - 0x2d
 105          * [15:00] Subsytem Vendor ID (Indicates system board vendor)
 106          */
 107         /* SID - Subsystem Identification Register
 108          * 0x2e - 0x2f
 109          * [15:00] Subsystem ID
 110          */
 111         // Not everyone wants to be Super Micro Computer, Inc.
 112         // The mainboard should set this if desired.
 113         // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
 114
 115         /* Undocumented
 116          * (DRAM Read Timing Control, if similar to 855PM?)
 117          * 0x80 - 0x81
 118          * This register has something to do with CAS latencies,
 119          * possibily this is the real chipset control.
 120          * At 0x00 CAS latency 1.5 works.
 121          * At 0x06 CAS latency 2.5 works.
 122          * At 0x01 CAS latency 2.0 works.
 123          */
 124         /* This is still undocumented in e7501, but with different values
 125          * CAS 2.0 values taken from Intel BIOS settings, others are a guess
 126          * and may be terribly wrong. Old values preserved as comments until I
 127          * figure this out for sure.
 128          * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
 129          * work at all.
 130          * Steven James 02/06/2003
 131          */
 132         /* NOTE: values now configured in configure_e7501_cas_latency() based
 133          *       on SPD info and total number of DIMMs (per Intel)
 134          */
 135
 136         /* FDHC - Fixed DRAM Hole Control
 137          * 0x58
 138          * [7:7] Hole_Enable
 139          *       0 == No memory Hole
 140          *       1 == Memory Hole from 15MB to 16MB
 141          * [6:0] Reserved
 142          *
 143          * PAM - Programmable Attribute Map
 144          * 0x59 [1:0] Reserved
 145          * 0x59 [5:4] 0xF0000 - 0xFFFFF
 146          * 0x5A [1:0] 0xC0000 - 0xC3FFF
 147          * 0x5A [5:4] 0xC4000 - 0xC7FFF
 148          * 0x5B [1:0] 0xC8000 - 0xCBFFF
 149          * 0x5B [5:4] 0xCC000 - 0xCFFFF
 150          * 0x5C [1:0] 0xD0000 - 0xD3FFF
 151          * 0x5C [5:4] 0xD4000 - 0xD7FFF
 152          * 0x5D [1:0] 0xD8000 - 0xDBFFF
 153          * 0x5D [5:4] 0xDC000 - 0xDFFFF
 154          * 0x5E [1:0] 0xE0000 - 0xE3FFF
 155          * 0x5E [5:4] 0xE4000 - 0xE7FFF
 156          * 0x5F [1:0] 0xE8000 - 0xEBFFF
 157          * 0x5F [5:4] 0xEC000 - 0xEFFFF
 158          *       00 == DRAM Disabled (All Access go to memory mapped I/O space)
 159          *       01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
 160          *       10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
 161          *       11 == Normal (All Access go to DRAM)
 162          */
 163
 164         // Map all legacy ranges to DRAM
 165         0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
 166         0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
 167
 168         /* DRB - DRAM Row Boundary Registers
 169          * 0x60 - 0x6F
 170          *     An array of 8 byte registers, which hold the ending
 171          *     memory address assigned  to each pair of DIMMS, in 64MB
 172          *     granularity.
 173          */
 174         // Conservatively say each row has 64MB of ram, we will fix this up later
 175         // NOTE: These defaults allow us to prime all of the DIMMs on the board
 176         //               without jumping through 36-bit adddressing hoops, even if the
 177         //               total memory is > 4 GB. Changing these values may break do_ram_command()!
 178         0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
 179         0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
 180
 181         /* DRA - DRAM Row Attribute Register
 182          * 0x70 Row 0,1
 183          * 0x71 Row 2,3
 184          * 0x72 Row 4,5
 185          * 0x73 Row 6,7
 186          * [7:7] Device width for Odd numbered rows
 187          *       0 == 8 bits wide x8
 188          *       1 == 4 bits wide x4
 189          * [6:4] Row Attributes for Odd numbered rows
 190          *       010 == 8KB (for dual-channel)
 191          *       011 == 16KB (for dual-channel)
 192          *       100 == 32KB (for dual-channel)
 193          *       101 == 64KB (for dual-channel)
 194          *       Others == Reserved
 195          * [3:3] Device width for Even numbered rows
 196          *       0 == 8 bits wide x8
 197          *       1 == 4 bits wide x4
 198          * [2:0] Row Attributes for Even numbered rows
 199          *       010 == 8KB (for dual-channel)
 200          *       011 == 16KB (for dual-channel)
 201          *       100 == 32KB (for dual-channel)
 202          *       101 == 64KB (This page size appears broken)
 203          *       Others == Reserved
 204          */
 205         // NOTE: overridden by configure_e7501_row_attributes(), later
 206         0x70, 0x00000000, 0,
 207
 208         /* DRT - DRAM Timing Register
 209          * 0x78
 210          * [31:30] Reserved
 211          * [29:29] Back to Back Write-Read Turn Around
 212          *         0 == 3 clocks between WR-RD commands
 213          *         1 == 2 clocks between WR-RD commands
 214          * [28:28] Back to Back Read-Write Turn Around
 215          *         0 == 5 clocks between RD-WR commands
 216          *         1 == 4 clocks between RD-WR commands
 217          * [27:27] Back to Back Read Turn Around
 218          *         0 == 4 clocks between RD commands
 219          *         1 == 3 clocks between RD commands
 220          * [26:24] Read Delay (tRD)
 221          *         000 == 7 clocks
 222          *         001 == 6 clocks
 223          *         010 == 5 clocks
 224          *         Others == Reserved
 225          * [23:19] Reserved
 226          * [18:16] DRAM idle timer
 227          *      000 == infinite
 228          *      011 == 16 dram clocks
 229          *      001 == 0 clocks
 230          * [15:11] Reserved
 231          * [10:09] Active to Precharge (tRAS)
 232          *         00 == 7 clocks
 233          *         01 == 6 clocks
 234          *         10 == 5 clocks
 235          *         11 == Reserved
 236          * [08:06] Reserved
 237          * [05:04] Cas Latency (tCL)
 238          *         00 == 2.5 Clocks
 239          *         01 == 2.0 Clocks
 240          *         10 == Reserved (was 1.5 Clocks for E7500)
 241          *         11 == Reserved
 242          * [03:03] Write Ras# to Cas# Delay (tRCD)
 243          *         0 == 3 DRAM Clocks
 244          *         1 == 2 DRAM Clocks
 245          * [02:01] Read RAS# to CAS# Delay (tRCD)
 246          *         00 == reserved
 247          *         01 == reserved
 248          *         10 == 3 DRAM Clocks
 249          *         11 == 2 DRAM Clocks
 250          * [00:00] DRAM RAS# to Precharge (tRP)
 251          *         0 == 3 DRAM Clocks
 252          *         1 == 2 DRAM Clocks
 253          */
 254
 255         // Some earlier settings:
 256         /* Most aggressive settings possible */
 257 //      0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
 258 //      0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 259 //      0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 260
 261         // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
 262         // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
 263         0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16),
 264
 265         /* FIXME why was I attempting to set a reserved bit? */
 266         /* 0x0100040f */
 267
 268         /* DRC - DRAM Contoller Mode Register
 269          * 0x7c
 270          * [31:30] Reserved
 271          * [29:29] Initialization Complete
 272          *         0 == Not Complete
 273          *         1 == Complete
 274          * [28:23] Reserved
 275          * [22:22]         Channels
 276          *              0 == Single channel
 277          *              1 == Dual Channel
 278          * [21:20] DRAM Data Integrity Mode
 279          *         00 == Disabled, no ECC
 280          *         01 == Reserved
 281          *         10 == Error checking, using chip-kill, with correction
 282          *         11 == Reserved
 283          * [19:18] DRB Granularity (Read-Only)
 284          *         00 == 32 MB quantities (single channel mode)
 285          *                 01 == 64 MB quantities (dual-channel mode)
 286          *                 10 == Reserved
 287          *                 11 == Reserved
 288          * [17:17] (Intel Undocumented) should always be set to 1       (SJM: comment inconsistent with current setting, below)
 289          * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
 290          *         0 == 2n Rule
 291          *         1 == 1n rule
 292          * [15:11] Reserved
 293          * [10:08] Refresh mode select
 294          *         000 == Refresh disabled
 295          *         001 == Refresh interval 15.6 usec
 296          *         010 == Refresh interval 7.8 usec
 297          *         011 == Refresh interval 64 usec
 298          *         111 == Refresh every 64 clocks (fast refresh)
 299          * [07:07] Reserved
 300          * [06:04] Mode Select (SMS)
 301          *         000 == Reserved (was Self Refresh Mode in E7500)
 302          *         001 == NOP Command
 303          *         010 == All Banks Precharge
 304          *         011 == Mode Register Set
 305          *         100 == Extended Mode Register Set
 306          *         101 == Reserved
 307          *         110 == CBR Refresh
 308          *         111 == Normal Operation
 309          * [03:00] Reserved
 310          */
 311 //      .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
 312 //      .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
 313 //      .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
 314
 315         // Default to dual-channel mode, ECC, 1-clock address/cmd hold
 316         // NOTE: configure_e7501_dram_controller_mode() configures further
 317         0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
 318
 319         /* Another Intel undocumented register
 320          * 0x88 - 0x8B
 321          * [31:31]      Purpose unknown
 322          * [26:26]      Master DLL Reset?
 323          *                      0 == Normal operation?
 324          *                      1 == Reset?
 325          * [07:07]      Periodic memory recalibration?
 326          *                      0 == Disabled?
 327          *                      1 == Enabled?
 328          * [04:04]      Receive FIFO RE-Sync?
 329          *                      0 == Normal operation?
 330          *                      1 == Reset?
 331          */
 332         // NOTE: Some factory BIOSs don't do this.
 333         //               Doesn't seem to matter either way.
 334         0x88, 0xffffff00, 0x80,
 335
 336         /* CLOCK_DIS - CK/CK# Disable Register
 337          * 0x8C
 338          * [7:7] DDR Frequency
 339          *               0 == 100 MHz (200 MHz data rate)
 340          *               1 == 133 MHz (266 MHz data rate)
 341          * [6:4] Reserved
 342          * [3:3] CK3
 343          *       0 == Enable
 344          *       1 == Disable
 345          * [2:2] CK2
 346          *       0 == Enable
 347          *       1 == Disable
 348          * [1:1] CK1
 349          *       0 == Enable
 350          *       1 == Disable
 351          * [0:0] CK0
 352          *       0 == Enable
 353          *       1 == Disable
 354          */
 355         // NOTE: Disable all clocks initially; turn ones we need back on
 356         //               in enable_e7501_clocks()
 357         0x8C, 0xfffffff0, 0xf,
 358
 359         /* TOLM - Top of Low Memory Register
 360          * 0xC4 - 0xC5
 361          * [15:11] Top of low memory (TOLM)
 362          *         The address below 4GB that should be treated as RAM,
 363          *         on a 128MB granularity.
 364          * [10:00] Reserved
 365          */
 366         /* REMAPBASE - Remap Base Address Regsiter
 367          * 0xC6 - 0xC7
 368          * [15:10] Reserved
 369          * [09:00] Remap Base Address [35:26] 64M aligned
 370          *         Bits [25:0] are assumed to be 0.
 371          */
 372
 373         // NOTE: TOLM overridden by configure_e7501_ram_addresses()
 374         0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
 375
 376         /* REMAPLIMIT - Remap Limit Address Register
 377          * 0xC8 - 0xC9
 378          * [15:10] Reserved
 379          * [09:00] Remap Limit Address [35:26] 64M aligned
 380          * When remaplimit < remapbase the remap window is disabled.
 381          */
 382         0xc8, 0xfffffc00, 0,
 383
 384         /* DVNP - Device Not Present Register
 385          * 0xE0 - 0xE1
 386          * [15:05] Reserved
 387          * [04:04] Device 4 Function 1 Present
 388          *         0 == Present
 389          *         1 == Absent
 390          * [03:03] Device 3 Function 1 Present
 391          *         0 == Present
 392          *         1 == Absent
 393          * [02:02] Device 2 Function 1 Present
 394          *         0 == Present
 395          *         1 == Absent
 396          * [01:01] Reserved
 397          * [00:00] Device 0 Function 1 Present
 398          *         0 == Present
 399          *         1 == Absent
 400          */
 401
 402         // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
 403         0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0),
 404
 405         // Undocumented
 406         0xd8, 0xffff9fff, 0x00000000,
 407
 408         // Undocumented - this is pure conjecture based on similarity to 855PM
 409         /* MCHTST - MCH Test Register
 410          * 0xF4 - 0xF7
 411          * [31:31] Purpose unknown
 412          * [30:30] Purpose unknown
 413          * [29:23] Unknown - not used?
 414          * [22:22] System Memory MMR Enable
 415          *         0 == Disable: mem space and BAR at 0x14 are not accessible
 416          *         1 == Enable: mem space and BAR at 0x14 are accessible
 417          * [21:20] Purpose unknown
 418          * [19:02] Unknown - not used?
 419          * [01:01] D6EN (Device #6 enable)
 420          *         0 == Disable
 421          *         1 == Enable
 422          * [00:00] Unknown - not used?
 423          */
 424
 425         0xf4, 0x3f8ffffd, 0x40300002,
 426
 427 #ifdef SUSPICIOUS_LOOKING_CODE
 428         // SJM: Undocumented.
 429         //              This will access D2:F0:0x50, is this correct??
 430         0x1050, 0xffffffcf, 0x00000030,
 431 #endif
 432 };
 433
 434         /* DDR RECOMP tables */
 435
 436 // Slew table for 1x drive?
 437 static const uint32_t maybe_1x_slew_table[] = {
 438         0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
 439         0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
 440 };
 441
 442 // Slew table for 2x drive?
 443 static const uint32_t maybe_2x_slew_table[] = {
 444         0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
 445         0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
 446 };
 447
 448 // Pull Up / Pull Down offset table, if analogous to IXP2800?
 449 static const uint32_t maybe_pull_updown_offset_table[] = {
 450         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 451         0x88888888, 0x88888888, 0x88888888, 0x88888888,
 452 };
 453
 454 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 455 /*                                                                              TABLES                                                                    */
 456 /**********************************************************************************/
 457 #define SLOW_DOWN_IO inb(0x80)
 458 //#define SLOW_DOWN_IO udelay(40);
 459
 460         /* Estimate that SLOW_DOWN_IO takes about 50&76us */
 461         /* delay for 200us */
 462
 463 #if 1
 464 static void do_delay(void)
 465 {
 466         int i;
 467         for (i = 0; i < 16; i++) {
 468                 SLOW_DOWN_IO;
 469         }
 470 }
 471
 472 #define DO_DELAY do_delay()
 473 #else
 474 #define DO_DELAY \
 475         udelay(200)
 476 #endif
 477
 478 #define EXTRA_DELAY DO_DELAY
 479
 480 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 481 /*                              DELAY FUNCTIONS                                   */
 482 /**********************************************************************************/
 483
 484 static void die_on_spd_error(int spd_return_value)
 485 {
 486         if (spd_return_value < 0)
 487                 die("Error reading SPD info\n");
 488 }
 489
 490 //----------------------------------------------------------------------------------
 491 // Function:            sdram_spd_get_page_size
 492 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 493 // Return Value:        struct dimm_size - log2(page size) for each side of the DIMM.
 494 // Description:         Calculate the page size for each physical bank of the DIMM:
 495 //                                              log2(page size) = (# columns) + log2(data width)
 496 //
 497 //                                      NOTE: page size is the total number of data bits in a row.
 498 //
 499 static struct dimm_size sdram_spd_get_page_size(uint16_t
 500                                                 dimm_socket_address)
 501 {
 502         uint16_t module_data_width;
 503         int value;
 504         struct dimm_size pgsz;
 505
 506         pgsz.side1 = 0;
 507         pgsz.side2 = 0;
 508
 509         // Side 1
 510         value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 511         if (value < 0)
 512                 goto hw_err;
 513         pgsz.side1 = value & 0xf;       // # columns in bank 1
 514
 515         /* Get the module data width and convert it to a power of two */
 516         value =
 517             spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 518         if (value < 0)
 519                 goto hw_err;
 520         module_data_width = (value & 0xff) << 8;
 521
 522         value =
 523             spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 524         if (value < 0)
 525                 goto hw_err;
 526         module_data_width |= (value & 0xff);
 527
 528         pgsz.side1 += log2(module_data_width);
 529
 530         /* side two */
 531         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 532         if (value < 0)
 533                 goto hw_err;
 534         if (value > 2)
 535                 die("Bad SPD value\n");
 536         if (value == 2) {
 537
 538                 pgsz.side2 = pgsz.side1;        // Assume symmetric banks until we know differently
 539                 value =
 540                     spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 541                 if (value < 0)
 542                         goto hw_err;
 543                 if ((value & 0xf0) != 0) {
 544                         // Asymmetric banks
 545                         pgsz.side2 -= value & 0xf;      /* Subtract out columns on side 1 */
 546                         pgsz.side2 += (value >> 4) & 0xf;       /* Add in columns on side 2 */
 547                 }
 548         }
 549
 550         return pgsz;
 551
 552       hw_err:
 553         die(SPD_ERROR);
 554         return pgsz;            // Never reached
 555 }
 556
 557 //----------------------------------------------------------------------------------
 558 // Function:            sdram_spd_get_width
 559 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 560 // Return Value:        dimm_size - width in bits of each DIMM side's DRAMs.
 561 // Description:         Read the width in bits of each DIMM side's DRAMs via SPD.
 562 //                                      (i.e. 4, 8, 16)
 563 //
 564 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 565 {
 566         int value;
 567         struct dimm_size width;
 568
 569         width.side1 = 0;
 570         width.side2 = 0;
 571
 572         value =
 573             spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 574         die_on_spd_error(value);
 575
 576         width.side1 = value & 0x7f;     // Mask off bank 2 flag
 577
 578         if (value & 0x80) {
 579                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 580         } else {
 581                 // If bank 2 exists, it's the same width as bank 1
 582                 value =
 583                     spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 584                 die_on_spd_error(value);
 585
 586 #ifdef ROMCC_IF_BUG_FIXED
 587                 if (value == 2)
 588                         width.side2 = width.side1;
 589 #else
 590                 switch (value) {
 591                 case 2:
 592                         width.side2 = width.side1;
 593                         break;
 594
 595                 default:
 596                         break;
 597                 }
 598 #endif
 599         }
 600
 601         return width;
 602 }
 603
 604 //----------------------------------------------------------------------------------
 605 // Function:            spd_get_dimm_size
 606 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 607 // Return Value:        dimm_size - log2(number of bits) for each side of the DIMM
 608 // Description:         Calculate the log base 2 size in bits of both DIMM sides.
 609 //                      log2(# bits) = (# columns) + log2(data width) +
 610 //                                         (# rows) + log2(banks per SDRAM)
 611 //
 612 //                      Note that it might be easier to use SPD byte 31 here, it has the
 613 //                      DIMM size as a multiple of 4MB.  The way we do it now we can size
 614 //                      both sides of an asymmetric dimm.
 615 //
 616 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
 617 {
 618         int value;
 619
 620         // Start with log2(page size)
 621         struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
 622
 623         if (sz.side1 > 0) {
 624
 625                 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
 626                 die_on_spd_error(value);
 627
 628                 sz.side1 += value & 0xf;
 629
 630                 if (sz.side2 > 0) {
 631
 632                         // Double-sided DIMM
 633                         if (value & 0xF0)
 634                                 sz.side2 += value >> 4; // Asymmetric
 635                         else
 636                                 sz.side2 += value;      // Symmetric
 637                 }
 638
 639                 value =
 640                     spd_read_byte(dimm_socket_address,
 641                                   SPD_NUM_BANKS_PER_SDRAM);
 642                 die_on_spd_error(value);
 643
 644                 value = log2(value);
 645                 sz.side1 += value;
 646                 if (sz.side2 > 0)
 647                         sz.side2 += value;
 648         }
 649
 650         return sz;
 651 }
 652
 653 #ifdef VALIDATE_DIMM_COMPATIBILITY
 654 //----------------------------------------------------------------------------------
 655 // Function:            are_spd_values_equal
 656 // Parameters:          spd_byte_number -
 657 //                      dimmN_address - SMBus addresses of DIMM sockets to interrogate
 658 // Return Value:        1 if both DIMM sockets report the same value for the specified
 659 //                      SPD parameter; 0 if the values differed or an error occurred.
 660 // Description:         Determine whether two DIMMs have the same value for a SPD parameter.
 661 //
 662 static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
 663                                     uint16_t dimm0_address,
 664                                     uint16_t dimm1_address)
 665 {
 666         uint8_t bEqual = 0;
 667
 668         int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
 669         int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
 670
 671         if ((dimm0_value >= 0) && (dimm1_value >= 0)
 672             && (dimm0_value == dimm1_value))
 673                 bEqual = 1;
 674
 675         return bEqual;
 676 }
 677 #endif
 678
 679 //----------------------------------------------------------------------------------
 680 // Function:            spd_get_supported_dimms
 681 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 682 //                                              SMBus addresses of DIMM slots on the mainboard
 683 // Return Value:        uint8_t - a bitmask indicating which of the possible sockets
 684 //                      for each channel was found to contain a compatible DIMM.
 685 //                      Bit 0 corresponds to the closest socket for channel 0,
 686 //                      Bit 1 to the next socket for channel 0,
 687 //                      ...
 688 //                      Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
 689 //                      Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
 690 //                      ...
 691 //                      Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
 692 // Description:         Scan for compatible DIMMs.
 693 //                      The code in this module only supports dual-channel operation,
 694 //                      so we test that compatible DIMMs are paired.
 695 //
 696 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 697 {
 698         int i;
 699         uint8_t dimm_mask = 0;
 700
 701         // Have to increase size of dimm_mask if this assertion is violated
 702         ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
 703
 704         // Find DIMMs we can support on channel 0.
 705         // Then see if the corresponding channel 1 DIMM has the same parameters,
 706         // since we only support dual-channel.
 707
 708         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 709
 710                 uint16_t channel0_dimm = ctrl->channel0[i];
 711                 uint16_t channel1_dimm = ctrl->channel1[i];
 712                 uint8_t bDualChannel = 1;
 713 #ifdef VALIDATE_DIMM_COMPATIBILITY
 714                 struct dimm_size page_size;
 715                 struct dimm_size sdram_width;
 716 #endif
 717                 int spd_value;
 718
 719                 if (channel0_dimm == 0)
 720                         continue;       // No such socket on this mainboard
 721
 722                 if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
 723                     SPD_MEMORY_TYPE_SDRAM_DDR)
 724                         continue;
 725
 726 #ifdef VALIDATE_DIMM_COMPATIBILITY
 727                 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
 728                     SPD_VOLTAGE_SSTL2)
 729                         continue;       // Unsupported voltage
 730
 731                 // E7501 does not support unregistered DIMMs
 732                 spd_value =
 733                     spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
 734                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
 735                         continue;
 736
 737                 // Must support burst = 4 for dual-channel operation on E7501
 738                 // NOTE: for single-channel, burst = 8 is required
 739                 spd_value =
 740                     spd_read_byte(channel0_dimm,
 741                                   SPD_SUPPORTED_BURST_LENGTHS);
 742                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 743                         continue;
 744
 745                 page_size = sdram_spd_get_page_size(channel0_dimm);
 746                 sdram_width = sdram_spd_get_width(channel0_dimm);
 747
 748                 // Validate DIMM page size
 749                 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
 750                 // NOTE: 4 KB =  32 Kb = 2^15
 751                 //              32 KB = 262 Kb = 2^18
 752
 753                 if ((page_size.side1 < 15) || (page_size.side1 > 18))
 754                         continue;
 755
 756                 // If DIMM is double-sided, verify side2 page size
 757                 if (page_size.side2 != 0) {
 758                         if ((page_size.side2 < 15)
 759                             || (page_size.side2 > 18))
 760                                 continue;
 761                 }
 762                 // Validate SDRAM width
 763                 // The E7501 only supports x4 and x8 devices
 764
 765                 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
 766                         continue;
 767
 768                 // If DIMM is double-sided, verify side2 width
 769                 if (sdram_width.side2 != 0) {
 770                         if ((sdram_width.side2 != 4)
 771                             && (sdram_width.side2 != 8))
 772                                 continue;
 773                 }
 774 #endif
 775                 // Channel 0 DIMM looks compatible.
 776                 // Now see if it is paired with the proper DIMM on channel 1.
 777
 778                 ASSERT(channel1_dimm != 0);     // No such socket on this mainboard??
 779
 780                 // NOTE: unpopulated DIMMs cause read to fail
 781                 spd_value =
 782                     spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
 783                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 784
 785                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 786                         continue;
 787                 }
 788 #ifdef VALIDATE_DIMM_COMPATIBILITY
 789                 spd_value =
 790                     spd_read_byte(channel1_dimm,
 791                                   SPD_SUPPORTED_BURST_LENGTHS);
 792                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 793                         continue;
 794
 795                 int j;
 796                 for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
 797                         if (!are_spd_values_equal
 798                             (dual_channel_parameters[j], channel0_dimm,
 799                              channel1_dimm)) {
 800
 801                                 bDualChannel = 0;
 802                                 break;
 803                         }
 804                 }
 805 #endif
 806
 807                 // Code around ROMCC bug in optimization of "if" statements
 808 #ifdef ROMCC_IF_BUG_FIXED
 809                 if (bDualChannel) {
 810                         // Made it through all the checks, this DIMM pair is usable
 811                         dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
 812                 } else
 813                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 814 #else
 815                 switch (bDualChannel) {
 816                 case 0:
 817                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 818                         break;
 819
 820                 default:
 821                         // Made it through all the checks, this DIMM pair is usable
 822                         dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i));
 823                         break;
 824                 }
 825 #endif
 826         }
 827
 828         return dimm_mask;
 829 }
 830
 831 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 832 /*                                              SPD (SERIAL PRESENCE DETECT) FUNCTIONS                                    */
 833 /**********************************************************************************/
 834
 835 //----------------------------------------------------------------------------------
 836 // Function:            do_ram_command
 837 // Parameters:
 838 //                                      command - specifies the command to be sent to the DIMMs:
 839 //                                              RAM_COMMAND_NOP                 - No Operation
 840 //                                              RAM_COMMAND_PRECHARGE   - Precharge all banks
 841 //                                              RAM_COMMAND_MRS                 - Load Mode Register
 842 //                                              RAM_COMMAND_EMRS                - Load Extended Mode Register
 843 //                                              RAM_COMMAND_CBR                 - Auto Refresh ("CAS-before-RAS")
 844 //                                              RAM_COMMAND_NORMAL              - Normal operation
 845 //                                      jedec_mode_bits - for mode register set & extended mode register set
 846 //                                              commands, bits 0-12 contain the register value in JEDEC format.
 847 // Return Value:        None
 848 // Description:         Send the specified command to all DIMMs.
 849 //
 850 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 851 {
 852         int i;
 853         uint32_t dram_controller_mode;
 854         uint8_t dimm_start_64M_multiple = 0;
 855         uint16_t e7501_mode_bits = jedec_mode_bits;
 856
 857         // Configure the RAM command
 858         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
 859         dram_controller_mode &= 0xFFFFFF8F;
 860         dram_controller_mode |= command;
 861         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
 862
 863         // RAM_COMMAND_NORMAL is an exception.
 864         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 865
 866         if (command != RAM_COMMAND_NORMAL) {
 867
 868                 // Send the command to all DIMMs by accessing a memory location within each
 869                 // NOTE: for mode select commands, some of the location address bits
 870                 // are part of the command
 871
 872                 // Map JEDEC mode bits to E7501
 873                 if (command == RAM_COMMAND_MRS) {
 874                         // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
 875                         // The E7501 hard-sets DIMM address lines 10 & 0 to zero
 876
 877                         ASSERT(!(jedec_mode_bits & 0x0401));
 878
 879                         e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) |   // JEDEC bits 11-12 move to bits 14-15
 880                             ((jedec_mode_bits & 0x03FE) << (13 - 9));   // JEDEC bits 1-9 move to bits 5-13
 881
 882                 } else if (command == RAM_COMMAND_EMRS) {
 883                         // Host address lines [15:3] map to DIMM address lines [12:0]
 884                         e7501_mode_bits = jedec_mode_bits <<= 3;
 885                 } else
 886                         ASSERT(jedec_mode_bits == 0);
 887
 888                 dimm_start_64M_multiple = 0;
 889
 890                 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
 891
 892                         uint8_t dimm_end_64M_multiple =
 893                             pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
 894                         if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
 895
 896                                 // This code assumes DRAM row boundaries are all set below 4 GB
 897                                 // NOTE: 0x40 * 64 MB == 4 GB
 898                                 ASSERT(dimm_start_64M_multiple < 0x40);
 899
 900                                 // NOTE: 2^26 == 64 MB
 901
 902                                 uint32_t dimm_start_address =
 903                                     dimm_start_64M_multiple << 26;
 904
 905                                 RAM_DEBUG_MESSAGE("    Sending RAM command to 0x");
 906                                 RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
 907                                 RAM_DEBUG_MESSAGE("\n");
 908
 909                                 read32(dimm_start_address + e7501_mode_bits);
 910
 911                                 // Set the start of the next DIMM
 912                                 dimm_start_64M_multiple =
 913                                     dimm_end_64M_multiple;
 914                         }
 915                 }
 916         }
 917 }
 918
 919 //----------------------------------------------------------------------------------
 920 // Function:            set_ram_mode
 921 // Parameters:          jedec_mode_bits - for mode register set & extended mode register set
 922 //                      commands, bits 0-12 contain the register value in JEDEC format.
 923 // Return Value:        None
 924 // Description:         Set the mode register of all DIMMs. The proper CAS# latency
 925 //                                      setting is added to the mode bits specified by the caller.
 926 //
 927 static void set_ram_mode(uint16_t jedec_mode_bits)
 928 {
 929         ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
 930
 931         uint32_t dram_cas_latency =
 932             pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
 933
 934         switch (dram_cas_latency) {
 935         case DRT_CAS_2_5:
 936                 jedec_mode_bits |= SDRAM_CAS_2_5;
 937                 break;
 938
 939         case DRT_CAS_2_0:
 940                 jedec_mode_bits |= SDRAM_CAS_2_0;
 941                 break;
 942
 943         default:
 944                 BUG();
 945                 break;
 946         }
 947
 948         do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
 949 }
 950
 951 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 952 /*                              SDRAM CONFIGURATION FUNCTIONS                     */
 953 /**********************************************************************************/
 954
 955 //----------------------------------------------------------------------------------
 956 // Function:            configure_dimm_row_boundaries
 957 // Parameters:
 958 //                      dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
 959 //                      total_dram_64M_multiple - total DRAM in the system (as a
 960 //                      multiple of 64 MB) for DIMMs < dimm_index
 961 //                      dimm_index - which DIMM pair is being processed
 962 //                      (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
 963 // Return Value:        New multiple of 64 MB total DRAM in the system
 964 // Description:         Configure the E7501's DRAM Row Boundary registers for the memory
 965 //                      present in the specified DIMM.
 966 //
 967 static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
 968 {
 969         int i;
 970
 971         ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
 972
 973         // DIMM sides must be at least 32 MB
 974         ASSERT(dimm_log2_num_bits.side1 >= 28);
 975         ASSERT((dimm_log2_num_bits.side2 == 0)
 976                || (dimm_log2_num_bits.side2 >= 28));
 977
 978         // In dual-channel mode, we are called only once for each pair of DIMMs.
 979         // Each time we process twice the capacity of a single DIMM.
 980
 981         // Convert single DIMM capacity to paired DIMM capacity
 982         // (multiply by two ==> add 1 to log2)
 983         dimm_log2_num_bits.side1++;
 984         if (dimm_log2_num_bits.side2 > 0)
 985                 dimm_log2_num_bits.side2++;
 986
 987         // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
 988         // to the total capacity of the system
 989         // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
 990
 991         total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
 992
 993         // Configure the boundary address for the row on side 1
 994         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1),
 995                           total_dram_64M_multiple);
 996
 997         // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
 998         // (as a multiple of 64 MB) to the total capacity of the system
 999         if (dimm_log2_num_bits.side2 >= 29)
1000                 total_dram_64M_multiple +=
1001                     (1 << (dimm_log2_num_bits.side2 - 29));
1002
1003         // Configure the boundary address for the row (if any) on side 2
1004         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1),
1005                           total_dram_64M_multiple);
1006
1007         // Update boundaries for rows subsequent to these.
1008         // These settings will be overridden by a subsequent call if a populated physical slot exists
1009
1010         for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1011                 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1),
1012                                   total_dram_64M_multiple);
1013                 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1),
1014                                   total_dram_64M_multiple);
1015         }
1016
1017         return total_dram_64M_multiple;
1018 }
1019
1020 //----------------------------------------------------------------------------------
1021 // Function:            configure_e7501_ram_addresses
1022 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1023 //                                              SMBus addresses of DIMM slots on the mainboard
1024 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1025 //                                                              spd_get_supported_dimms()
1026 // Return Value:        None
1027 // Description:         Program the E7501's DRAM row boundary addresses and its Top Of
1028 //                                      Low Memory (TOLM). If necessary, set up a remap window so we
1029 //                                      don't waste DRAM that ordinarily would lie behind addresses
1030 //                                      reserved for memory-mapped I/O.
1031 //
1032 static void configure_e7501_ram_addresses(const struct mem_controller
1033                                           *ctrl, uint8_t dimm_mask)
1034 {
1035         int i;
1036         uint8_t total_dram_64M_multiple = 0;
1037
1038         // Configure the E7501's DRAM row boundaries
1039         // Start by zeroing out the temporary initial configuration
1040         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
1041         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
1042
1043         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1044
1045                 uint16_t dimm_socket_address = ctrl->channel0[i];
1046                 struct dimm_size sz;
1047
1048                 if (!(dimm_mask & (1 << i)))
1049                         continue;       // This DIMM not present
1050
1051                 sz = spd_get_dimm_size(dimm_socket_address);
1052
1053                 RAM_DEBUG_MESSAGE("dimm size =");
1054                 RAM_DEBUG_HEX32(sz.side1);
1055                 RAM_DEBUG_MESSAGE(" ");
1056                 RAM_DEBUG_HEX32(sz.side2);
1057                 RAM_DEBUG_MESSAGE("\n");
1058
1059                 if (sz.side1 == 0)
1060                         die("Bad SPD value\n");
1061
1062                 total_dram_64M_multiple =
1063                     configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
1064         }
1065
1066         // Configure the Top Of Low Memory (TOLM) in the E7501
1067         // This address must be a multiple of 128 MB that is less than 4 GB.
1068         // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1069         //               in the highest 5 bits.
1070
1071         // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1072         // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1073         // such as flash and memory-mapped I/O.
1074
1075         // If there is more than 3 GB of DRAM, we define a remap window which
1076         // makes the DRAM "behind" the reserved region available above the top of physical
1077         // memory.
1078
1079         // NOTE: 0xC0000000 / (64 MB) == 0x30
1080
1081         if (total_dram_64M_multiple <= 0x30) {
1082
1083                 // <= 3 GB total RAM
1084
1085                 /* I should really adjust all of this in C after I have resources
1086                  * to all of the pci devices.
1087                  */
1088
1089                 // Round up to 128MB granularity
1090                 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1091
1092                 uint8_t total_dram_128M_multiple =
1093                     (total_dram_64M_multiple + 1) >> 1;
1094
1095                 // Convert to high 16 bits of address
1096                 uint16_t top_of_low_memory =
1097                     total_dram_128M_multiple << 11;
1098
1099                 pci_write_config16(PCI_DEV(0, 0, 0), TOLM,
1100                                    top_of_low_memory);
1101
1102         } else {
1103
1104                 // > 3 GB total RAM
1105
1106                 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1107                 uint16_t remap_base = total_dram_64M_multiple;  // A[25:0] == 0
1108                 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1;      // A[25:0] == 0xF
1109
1110                 // Put TOLM at 3 GB
1111
1112                 pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
1113
1114                 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1115                 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1116                 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1117                 //               (i.e. a multiple of 64 MB) in the lowest 10 bits.
1118                 // NOTE: 0x100000000 / (64 MB) == 0x40
1119
1120                 if (total_dram_64M_multiple < 0x40) {
1121                         remap_base = 0x40;      // 0x100000000
1122                         remap_limit =
1123                             0x40 + (total_dram_64M_multiple - 0x30) - 1;
1124                 }
1125
1126                 pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE,
1127                                    remap_base);
1128                 pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT,
1129                                    remap_limit);
1130         }
1131 }
1132
1133 //----------------------------------------------------------------------------------
1134 // Function:            initialize_ecc
1135 // Parameters:          None
1136 // Return Value:        None
1137 // Description:         If we're configured to use ECC, initialize the SDRAM and
1138 //                                      clear the E7501's ECC error flags.
1139 //
1140 static void initialize_ecc(void)
1141 {
1142         uint32_t dram_controller_mode;
1143
1144         /* Test to see if ECC support is enabled */
1145         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1146         dram_controller_mode >>= 20;
1147         dram_controller_mode &= 3;
1148         if (dram_controller_mode == 2) {
1149
1150                 uint8_t byte;
1151
1152                 RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
1153                 /* Initialize ECC bits , use ECC zero mode (new to 7501) */
1154                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
1155                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
1156
1157                 // Wait for scrub cycle to complete
1158                 do {
1159                         byte =
1160                             pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
1161                 } while ((byte & 0x08) == 0);
1162
1163                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
1164                 RAM_DEBUG_MESSAGE("ECC state initialized.\n");
1165
1166                 /* Clear the ECC error bits */
1167                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
1168                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
1169
1170                 // Clear DRAM Interface error bits (write-one-clear)
1171                 pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18);
1172                 pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18);
1173
1174                 // Start normal ECC scrub
1175                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
1176         }
1177
1178 }
1179
1180 //----------------------------------------------------------------------------------
1181 // Function:            configure_e7501_dram_timing
1182 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1183 //                                              SMBus addresses of DIMM slots on the mainboard
1184 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1185 //                                                              spd_get_supported_dimms()
1186 // Return Value:        None
1187 // Description:         Program the DRAM Timing register of the E7501 (except for CAS#
1188 //                                      latency, which is assumed to have been programmed already), based
1189 //                                      on the parameters of the various installed DIMMs.
1190 //
1191 static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
1192                                         uint8_t dimm_mask)
1193 {
1194         int i;
1195         uint32_t dram_timing;
1196         int value;
1197         uint8_t slowest_row_precharge = 0;
1198         uint8_t slowest_ras_cas_delay = 0;
1199         uint8_t slowest_active_to_precharge_delay = 0;
1200         uint32_t current_cas_latency =
1201             pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
1202
1203         // CAS# latency must be programmed beforehand
1204         ASSERT((current_cas_latency == DRT_CAS_2_0)
1205                || (current_cas_latency == DRT_CAS_2_5));
1206
1207         // Each timing parameter is determined by the slowest DIMM
1208
1209         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1210                 uint16_t dimm_socket_address;
1211
1212                 if (!(dimm_mask & (1 << i)))
1213                         continue;       // This DIMM not present
1214
1215                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1216                         dimm_socket_address = ctrl->channel0[i];
1217                 else
1218                         dimm_socket_address =
1219                             ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1220
1221                 value =
1222                     spd_read_byte(dimm_socket_address,
1223                                   SPD_MIN_ROW_PRECHARGE_TIME);
1224                 if (value < 0)
1225                         goto hw_err;
1226                 if (value > slowest_row_precharge)
1227                         slowest_row_precharge = value;
1228
1229                 value =
1230                     spd_read_byte(dimm_socket_address,
1231                                   SPD_MIN_RAS_TO_CAS_DELAY);
1232                 if (value < 0)
1233                         goto hw_err;
1234                 if (value > slowest_ras_cas_delay)
1235                         slowest_ras_cas_delay = value;
1236
1237                 value =
1238                     spd_read_byte(dimm_socket_address,
1239                                   SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1240                 if (value < 0)
1241                         goto hw_err;
1242                 if (value > slowest_active_to_precharge_delay)
1243                         slowest_active_to_precharge_delay = value;
1244         }
1245
1246         // NOTE for timing parameters:
1247         //              At 133 MHz, 1 clock == 7.52 ns
1248
1249         /* Read the initial state */
1250         dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1251
1252         /* Trp */
1253
1254         // E7501 supports only 2 or 3 clocks for tRP
1255         if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
1256                 die("unsupported DIMM tRP");    // > 22.5 ns: 4 or more clocks
1257         else if (slowest_row_precharge > (15 << 2))
1258                 dram_timing &= ~(1 << 0);       // > 15.0 ns: 3 clocks
1259         else
1260                 dram_timing |= (1 << 0);        // <= 15.0 ns: 2 clocks
1261
1262         /*  Trcd */
1263
1264         // E7501 supports only 2 or 3 clocks for tRCD
1265         // Use the same value for both read & write
1266         dram_timing &= ~((1 << 3) | (3 << 1));
1267         if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
1268                 die("unsupported DIMM tRCD");   // > 22.5 ns: 4 or more clocks
1269         else if (slowest_ras_cas_delay > (15 << 2))
1270                 dram_timing |= (2 << 1);        // > 15.0 ns: 3 clocks
1271         else
1272                 dram_timing |= ((1 << 3) | (3 << 1));   // <= 15.0 ns: 2 clocks
1273
1274         /* Tras */
1275
1276         // E7501 supports only 5, 6, or 7 clocks for tRAS
1277         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1278         dram_timing &= ~(3 << 9);
1279
1280         if (slowest_active_to_precharge_delay > 52)
1281                 die("unsupported DIMM tRAS");   // > 52 ns:      8 or more clocks
1282         else if (slowest_active_to_precharge_delay > 45)
1283                 dram_timing |= (0 << 9);        // 46-52 ns: 7 clocks
1284         else if (slowest_active_to_precharge_delay > 37)
1285                 dram_timing |= (1 << 9);        // 38-45 ns: 6 clocks
1286         else
1287                 dram_timing |= (2 << 9);        // < 38 ns:      5 clocks
1288
1289         /* Trd */
1290
1291         /* Set to a 7 clock read delay. This is for 133Mhz
1292          *  with a CAS latency of 2.5  if 2.0 a 6 clock
1293          *  delay is good  */
1294
1295         dram_timing &= ~(7 << 24);      // 7 clocks
1296         if (current_cas_latency == DRT_CAS_2_0)
1297                 dram_timing |= (1 << 24);       // 6 clocks
1298
1299         /*
1300          * Back to Back Read-Write Turn Around
1301          */
1302         /* Set to a 5 clock back to back read to write turn around.
1303          *  4 is a good delay if the CAS latency is 2.0 */
1304
1305         dram_timing &= ~(1 << 28);      // 5 clocks
1306         if (current_cas_latency == DRT_CAS_2_0)
1307                 dram_timing |= (1 << 28);       // 4 clocks
1308
1309         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1310
1311         return;
1312
1313       hw_err:
1314         die(SPD_ERROR);
1315 }
1316
1317 //----------------------------------------------------------------------------------
1318 // Function:            configure_e7501_cas_latency
1319 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1320 //                                              SMBus addresses of DIMM slots on the mainboard
1321 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1322 //                                                              spd_get_supported_dimms()
1323 // Return Value:        None
1324 // Description:         Determine the shortest CAS# latency that the E7501 and all DIMMs
1325 //                                      have in common, and program the E7501 to use it.
1326 //
1327 static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
1328                                         uint8_t dimm_mask)
1329 {
1330         int i;
1331         int value;
1332         uint32_t dram_timing;
1333         uint16_t maybe_dram_read_timing;
1334         uint32_t dword;
1335
1336         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1337         // NOTE: E7501 supports only 2.0 and 2.5
1338         uint32_t system_compatible_cas_latencies =
1339             SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1340         uint32_t current_cas_latency;
1341         uint32_t dimm_compatible_cas_latencies;
1342
1343         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1344
1345                 uint16_t dimm_socket_address;
1346
1347                 if (!(dimm_mask & (1 << i)))
1348                         continue;       // This DIMM not usable
1349
1350                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1351                         dimm_socket_address = ctrl->channel0[i];
1352                 else
1353                         dimm_socket_address =
1354                             ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1355
1356                 value =
1357                     spd_read_byte(dimm_socket_address,
1358                                   SPD_ACCEPTABLE_CAS_LATENCIES);
1359                 if (value < 0)
1360                         goto hw_err;
1361
1362                 dimm_compatible_cas_latencies = value & 0x7f;   // Start with all supported by DIMM
1363                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1364
1365                 // Can we support the highest CAS# latency?
1366
1367                 value =
1368                     spd_read_byte(dimm_socket_address,
1369                                   SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1370                 if (value < 0)
1371                         goto hw_err;
1372
1373                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1374                 if (value > 0x75) {
1375                         // Our bus is too fast for this CAS# latency
1376                         // Remove it from the bitmask of those supported by the DIMM that are compatible
1377                         dimm_compatible_cas_latencies &= ~current_cas_latency;
1378                 }
1379                 // Can we support the next-highest CAS# latency (max - 0.5)?
1380
1381                 current_cas_latency >>= 1;
1382                 if (current_cas_latency != 0) {
1383                         value =
1384                             spd_read_byte(dimm_socket_address,
1385                                           SPD_SDRAM_CYCLE_TIME_2ND);
1386                         if (value < 0)
1387                                 goto hw_err;
1388                         if (value > 0x75)
1389                                 dimm_compatible_cas_latencies &=
1390                                     ~current_cas_latency;
1391                 }
1392                 // Can we support the next-highest CAS# latency (max - 1.0)?
1393                 current_cas_latency >>= 1;
1394                 if (current_cas_latency != 0) {
1395                         value =
1396                             spd_read_byte(dimm_socket_address,
1397                                           SPD_SDRAM_CYCLE_TIME_3RD);
1398                         if (value < 0)
1399                                 goto hw_err;
1400                         if (value > 0x75)
1401                                 dimm_compatible_cas_latencies &=
1402                                     ~current_cas_latency;
1403                 }
1404                 // Restrict the system to CAS# latencies compatible with this DIMM
1405                 system_compatible_cas_latencies &=
1406                     dimm_compatible_cas_latencies;
1407
1408                 /* go to the next DIMM */
1409         }
1410
1411         /* After all of the arduous calculation setup with the fastest
1412          * cas latency I can use.
1413          */
1414
1415         dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1416         dram_timing &= ~(DRT_CAS_MASK);
1417
1418         maybe_dram_read_timing =
1419             pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
1420         maybe_dram_read_timing &= 0xF00C;
1421
1422         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1423                 dram_timing |= DRT_CAS_2_0;
1424                 maybe_dram_read_timing |= 0xBB1;
1425         } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1426
1427                 uint32_t dram_row_attributes =
1428                     pci_read_config32(PCI_DEV(0, 0, 0), DRA);
1429
1430                 dram_timing |= DRT_CAS_2_5;
1431
1432                 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1433                 // different value if all DIMM slots are populated
1434
1435                 if ((dram_row_attributes & 0xff)
1436                     && (dram_row_attributes & 0xff00)
1437                     && (dram_row_attributes & 0xff0000)
1438                     && (dram_row_attributes & 0xff000000)) {
1439
1440                         // All slots populated
1441                         maybe_dram_read_timing |= 0x0882;
1442                 } else {
1443                         // Some unpopulated slots
1444                         maybe_dram_read_timing |= 0x0662;
1445                 }
1446         } else
1447                 die("No CAS# latencies compatible with all DIMMs!!\n");
1448
1449         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1450
1451         /* set master DLL reset */
1452         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
1453         dword |= (1 << 26);
1454         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1455
1456         dword &= 0x0c0007ff;    /* patch try register 88 is undocumented tnz */
1457         dword |= 0xd2109800;
1458
1459         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1460
1461         pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
1462                            maybe_dram_read_timing);
1463
1464         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);      /* reset master DLL reset */
1465         dword &= ~(1 << 26);
1466         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1467
1468         return;
1469
1470       hw_err:
1471         die(SPD_ERROR);
1472 }
1473
1474 //----------------------------------------------------------------------------------
1475 // Function:            configure_e7501_dram_controller_mode
1476 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1477 //                                              SMBus addresses of DIMM slots on the mainboard
1478 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1479 //                                                              spd_get_supported_dimms()
1480 // Return Value:        None
1481 // Description:         Configure the refresh interval so that we refresh no more often
1482 //                                      than required by the "most needy" DIMM. Also disable ECC if any
1483 //                                      of the DIMMs don't support it.
1484 //
1485 static void configure_e7501_dram_controller_mode(const struct
1486                                                  mem_controller *ctrl,
1487                                                  uint8_t dimm_mask)
1488 {
1489         int i;
1490
1491         // Initial settings
1492         uint32_t controller_mode =
1493             pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1494         uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1495
1496         // Code below assumes that most aggressive settings are in
1497         // force when we are called, either via E7501 reset defaults
1498         // or by sdram_set_registers():
1499         //      - ECC enabled
1500         //      - No refresh
1501
1502         ASSERT((controller_mode & (3 << 20)) == (2 << 20));     // ECC
1503         ASSERT(!(controller_mode & (7 << 8)));  // Refresh
1504
1505         /* Walk through _all_ dimms and find the least-common denominator for:
1506          *  - ECC support
1507          *  - refresh rates
1508          */
1509
1510         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1511
1512                 uint32_t dimm_refresh_mode;
1513                 int value;
1514                 uint16_t dimm_socket_address;
1515
1516                 if (!(dimm_mask & (1 << i))) {
1517                         continue;       // This DIMM not usable
1518                 }
1519
1520                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1521                         dimm_socket_address = ctrl->channel0[i];
1522                 else
1523                         dimm_socket_address =
1524                             ctrl->channel1[i -
1525                                            MAX_DIMM_SOCKETS_PER_CHANNEL];
1526
1527                 // Disable ECC mode if any one of the DIMMs does not support ECC
1528                 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1529
1530                 value =
1531                     spd_read_byte(dimm_socket_address,
1532                                   SPD_DIMM_CONFIG_TYPE);
1533                 die_on_spd_error(value);
1534                 if (value != ERROR_SCHEME_ECC) {
1535                         controller_mode &= ~(3 << 20);
1536                 }
1537
1538                 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1539                 die_on_spd_error(value);
1540                 value &= 0x7f;  // Mask off self-refresh bit
1541                 if (value > MAX_SPD_REFRESH_RATE) {
1542                         print_err("unsupported refresh rate\n");
1543                         continue;
1544                 }
1545                 // Get the appropriate E7501 refresh mode for this DIMM
1546                 dimm_refresh_mode = refresh_rate_map[value];
1547                 if (dimm_refresh_mode > 7) {
1548                         print_err("unsupported refresh rate\n");
1549                         continue;
1550                 }
1551                 // If this DIMM requires more frequent refresh than others,
1552                 // update the system setting
1553                 if (refresh_frequency[dimm_refresh_mode] >
1554                     refresh_frequency[system_refresh_mode])
1555                         system_refresh_mode = dimm_refresh_mode;
1556
1557 #ifdef SUSPICIOUS_LOOKING_CODE
1558 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1559 //                       than the clock period of the memory controller. Also, no other northbridge
1560 //                       looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
1561
1562                 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1563                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1564                 value =
1565                     spd_read_byte(dimm_socket_address,
1566                                   SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
1567                 die_on_spd_error(value);
1568                 if (value >= 0xa0) {    /* At 133MHz this constant should be 0x75 */
1569                         controller_mode &= ~(1 << 16);  /* Use two clock cyles instead of one */
1570                 }
1571 #endif
1572
1573                 /* go to the next DIMM */
1574         }
1575
1576         controller_mode |= (system_refresh_mode << 8);
1577
1578         // Configure the E7501
1579         pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
1580 }
1581
1582 //----------------------------------------------------------------------------------
1583 // Function:            configure_e7501_row_attributes
1584 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1585 //                                              SMBus addresses of DIMM slots on the mainboard
1586 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1587 //                                                              spd_get_supported_dimms()
1588 // Return Value:        None
1589 // Description:         Configure the E7501's DRAM Row Attributes (DRA) registers
1590 //                                      based on DIMM parameters read via SPD. This tells the controller
1591 //                                      the width of the SDRAM chips on each DIMM side (x4 or x8) and
1592 //                                      the page size of each DIMM side (4, 8, 16, or 32 KB).
1593 //
1594 static void configure_e7501_row_attributes(const struct mem_controller
1595                                            *ctrl, uint8_t dimm_mask)
1596 {
1597         int i;
1598         uint32_t row_attributes = 0;
1599
1600         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1601
1602                 uint16_t dimm_socket_address = ctrl->channel0[i];
1603                 struct dimm_size page_size;
1604                 struct dimm_size sdram_width;
1605
1606                 if (!(dimm_mask & (1 << i)))
1607                         continue;       // This DIMM not usable
1608
1609                 // Get the relevant parameters via SPD
1610                 page_size = sdram_spd_get_page_size(dimm_socket_address);
1611                 sdram_width = sdram_spd_get_width(dimm_socket_address);
1612
1613                 // Update the DRAM Row Attributes.
1614                 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1615                 // NOTE: 8 Kb = 2^13
1616                 row_attributes |= (page_size.side1 - 13) << (i << 3);   // Side 1 of each DIMM is an EVEN row
1617
1618                 if (sdram_width.side2 > 0)
1619                         row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4);     // Side 2 is ODD
1620
1621                 // Set x4 flags if appropriate
1622                 if (sdram_width.side1 == 4) {
1623                         row_attributes |= 0x08 << (i << 3);
1624                 }
1625
1626                 if (sdram_width.side2 == 4) {
1627                         row_attributes |= 0x08 << ((i << 3) + 4);
1628                 }
1629
1630                 /* go to the next DIMM */
1631         }
1632
1633         /* Write the new row attributes register */
1634         pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
1635 }
1636
1637 //----------------------------------------------------------------------------------
1638 // Function:            enable_e7501_clocks
1639 // Parameters:          dimm_mask - bitmask of populated DIMMs on the board - see
1640 //                                                              spd_get_supported_dimms()
1641 // Return Value:        None
1642 // Description:         Enable clock signals for populated DIMM sockets and disable them
1643 //                                      for unpopulated sockets (to reduce EMI).
1644 //
1645 static void enable_e7501_clocks(uint8_t dimm_mask)
1646 {
1647         int i;
1648         uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
1649
1650         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1651
1652                 uint8_t socket_mask = 1 << i;
1653
1654                 if (dimm_mask & socket_mask)
1655                         clock_disable &= ~socket_mask;  // DIMM present, enable clock
1656                 else
1657                         clock_disable |= socket_mask;   // DIMM absent, disable clock
1658         }
1659
1660         pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
1661 }
1662
1663 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1664 /*                                              DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS                                  */
1665 /**********************************************************************************/
1666
1667 //----------------------------------------------------------------------------------
1668 // Function:            RAM_RESET_DDR_PTR
1669 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1670 //                                              SMBus addresses of DIMM slots on the mainboard
1671 // Return Value:        None
1672 // Description:         DDR Receive FIFO RE-Sync (?)
1673 //
1674 static void RAM_RESET_DDR_PTR(void)
1675 {
1676         uint8_t byte;
1677         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1678         byte |= (1 << 4);
1679         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1680
1681         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1682         byte &= ~(1 << 4);
1683         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1684 }
1685
1686 //----------------------------------------------------------------------------------
1687 // Function:            ram_set_d0f0_regs
1688 // Parameters:          None
1689 // Return Value:        None
1690 // Description:         Set E7501 registers that are either independent of DIMM specifics,
1691 //                                      or establish default settings that will be overridden when we
1692 //                                      learn the specifics.
1693 //                                      This sets PCI configuration registers to known good values based
1694 //                                      on the table 'constant_register_values', which are a triple of
1695 //                                      configuration register offset, mask, and bits to set.
1696 //
1697 static void ram_set_d0f0_regs(void)
1698 {
1699         int i;
1700         int num_values = ARRAY_SIZE(constant_register_values);
1701
1702         ASSERT((num_values % 3) == 0);  // Bad table?
1703
1704         for (i = 0; i < num_values; i += 3) {
1705
1706                 uint32_t register_offset = constant_register_values[i];
1707                 uint32_t bits_to_mask = constant_register_values[i + 1];
1708                 uint32_t bits_to_set = constant_register_values[i + 2];
1709                 uint32_t register_value;
1710
1711                 // It's theoretically possible to set values for something other than D0:F0,
1712                 // but it's not typically done here
1713                 ASSERT(!(register_offset & 0xFFFFFF00));
1714
1715                 // bits_to_mask and bits_to_set should not reference the same bits
1716                 // Again, not strictly an error, but flagged as a potential bug
1717                 ASSERT((bits_to_mask & bits_to_set) == 0);
1718
1719                 register_value =
1720                     pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
1721                 register_value &= bits_to_mask;
1722                 register_value |= bits_to_set;
1723
1724                 pci_write_config32(PCI_DEV(0, 0, 0), register_offset,
1725                                    register_value);
1726         }
1727 }
1728
1729 //----------------------------------------------------------------------------------
1730 // Function:            write_8dwords
1731 // Parameters:          src_addr
1732 //                                      dst_addr
1733 // Return Value:        None
1734 // Description:         Copy 64 bytes from one location to another.
1735 //
1736 static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr)
1737 {
1738         int i;
1739         for (i = 0; i < 8; i++) {
1740                 write32(dst_addr, *src_addr);
1741                 src_addr++;
1742                 dst_addr += sizeof(uint32_t);
1743         }
1744 }
1745
1746 //----------------------------------------------------------------------------------
1747 // Function:            ram_set_rcomp_regs
1748 // Parameters:          None
1749 // Return Value:        None
1750 // Description:         Set the E7501's (undocumented) RCOMP registers.
1751 //                                      Per the 855PM datasheet and IXP2800 HW Initialization Reference
1752 //                                      Manual, RCOMP registers appear to affect drive strength,
1753 //                                      pullup/pulldown offset, and slew rate of various signal groups.
1754 //                                      Comments below are conjecture based on apparent similarity
1755 //                                      between the E7501 and these two chips.
1756 //
1757 static void ram_set_rcomp_regs(void)
1758 {
1759         uint32_t dword;
1760         uint8_t maybe_strength_control;
1761
1762         RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
1763
1764         /*enable access to the rcomp bar */
1765         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1766         dword |= (1 << 22);
1767         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1768
1769         // Set the RCOMP MMIO base address
1770         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
1771
1772         // Block RCOMP updates while we configure the registers
1773         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1774         dword |= (1 << 9);
1775         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1776
1777         /* Begin to write the RCOMP registers */
1778
1779         // Set CMD and DQ/DQS strength to 2x (?)
1780         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1781         maybe_strength_control |= 0x44;
1782         write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1783
1784         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1785         write16(RCOMP_MMIO + 0x42, 0);
1786
1787         write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
1788
1789         // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
1790         write16(RCOMP_MMIO + 0x40, 0);
1791
1792         // Set RCVEnOut# strength to 2x (?)
1793         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1794         maybe_strength_control |= 4;
1795         write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1796
1797         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1798         write16(RCOMP_MMIO + 0x50, 0);
1799
1800         // Set CS# strength for x4 SDRAM to 2x (?)
1801         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
1802         maybe_strength_control |= 4;
1803         write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1804
1805         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1806         write16(RCOMP_MMIO + 0x48, 0);
1807
1808         // Set CKE strength for x4 SDRAM to 2x (?)
1809         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
1810         maybe_strength_control |= 4;
1811         write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1812
1813         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1814         write16(RCOMP_MMIO + 0x44, 0);
1815
1816         // Set CK strength for x4 SDRAM to 1x (?)
1817         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
1818         maybe_strength_control |= 1;
1819         write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1820
1821         write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1822         write16(RCOMP_MMIO + 0x4c, 0);
1823
1824         write8(RCOMP_MMIO + 0x2c, 0xff);
1825
1826         // Set the digital filter length to 8 (?)
1827         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1828
1829         // NOTE: Some factory BIOS don't do this.
1830         //               Doesn't seem to matter either way.
1831         dword &= ~2;
1832
1833         dword |= 1;
1834         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1835
1836         /* Wait 40 usec */
1837         SLOW_DOWN_IO;
1838
1839         /* unblock updates */
1840         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1841         dword &= ~(1 << 9);
1842         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1843
1844         // Force a RCOMP measurement cycle?
1845         dword |= (1 << 8);
1846         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1847         dword &= ~(1 << 8);
1848         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1849
1850         /* Wait 40 usec */
1851         SLOW_DOWN_IO;
1852
1853         /*disable access to the rcomp bar */
1854         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1855         dword &= ~(1 << 22);
1856         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1857
1858 }
1859
1860 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1861 /*                                      DIMM-INDEPENDENT CONFIGURATION FUNCTIONS                                          */
1862 /**********************************************************************************/
1863
1864 //----------------------------------------------------------------------------------
1865 // Function:            sdram_enable
1866 // Parameters:          controllers - not used
1867 //                                      ctrl - PCI addresses of memory controller functions, and
1868 //                                              SMBus addresses of DIMM slots on the mainboard
1869 // Return Value:        None
1870 // Description:         Go through the JEDEC initialization sequence for all DIMMs,
1871 //                                      then enable refresh and initialize ECC and memory to zero.
1872 //                                      Upon exit, SDRAM is up and running.
1873 //
1874 static void sdram_enable(int controllers,
1875                          const struct mem_controller *ctrl)
1876 {
1877         uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
1878         uint32_t dram_controller_mode;
1879
1880         if (dimm_mask == 0)
1881                 return;
1882
1883         /* 1 & 2 Power up and start clocks */
1884         RAM_DEBUG_MESSAGE("Ram Enable 1\n");
1885         RAM_DEBUG_MESSAGE("Ram Enable 2\n");
1886
1887         /* A 200us delay is needed */
1888         DO_DELAY; EXTRA_DELAY;
1889
1890         /* 3. Apply NOP */
1891         RAM_DEBUG_MESSAGE("Ram Enable 3\n");
1892         do_ram_command(RAM_COMMAND_NOP, 0);
1893         EXTRA_DELAY;
1894
1895         /* 4 Precharge all */
1896         RAM_DEBUG_MESSAGE("Ram Enable 4\n");
1897         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1898         EXTRA_DELAY;
1899         /* wait until the all banks idle state... */
1900
1901         /* 5. Issue EMRS to enable DLL */
1902         RAM_DEBUG_MESSAGE("Ram Enable 5\n");
1903         do_ram_command(RAM_COMMAND_EMRS,
1904                        SDRAM_EXTMODE_DLL_ENABLE |
1905                        SDRAM_EXTMODE_DRIVE_NORMAL);
1906         EXTRA_DELAY;
1907
1908         /* 6. Reset DLL */
1909         RAM_DEBUG_MESSAGE("Ram Enable 6\n");
1910         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1911         EXTRA_DELAY;
1912         /* Ensure a 200us delay between the DLL reset in step 6 and the final
1913          * mode register set in step 9.
1914          * Infineon needs this before any other command is sent to the ram.
1915          */
1916         DO_DELAY; EXTRA_DELAY;
1917
1918         /* 7 Precharge all */
1919         RAM_DEBUG_MESSAGE("Ram Enable 7\n");
1920         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1921         EXTRA_DELAY;
1922
1923         /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1924         RAM_DEBUG_MESSAGE("Ram Enable 8\n");
1925         do_ram_command(RAM_COMMAND_CBR, 0);
1926         EXTRA_DELAY;
1927         do_ram_command(RAM_COMMAND_CBR, 0);
1928         EXTRA_DELAY;
1929
1930         /* And for good luck 6 more CBRs */
1931         do_ram_command(RAM_COMMAND_CBR, 0);
1932         EXTRA_DELAY;
1933         do_ram_command(RAM_COMMAND_CBR, 0);
1934         EXTRA_DELAY;
1935         do_ram_command(RAM_COMMAND_CBR, 0);
1936         EXTRA_DELAY;
1937         do_ram_command(RAM_COMMAND_CBR, 0);
1938         EXTRA_DELAY;
1939         do_ram_command(RAM_COMMAND_CBR, 0);
1940         EXTRA_DELAY;
1941         do_ram_command(RAM_COMMAND_CBR, 0);
1942         EXTRA_DELAY;
1943
1944         /* 9 mode register set */
1945         RAM_DEBUG_MESSAGE("Ram Enable 9\n");
1946         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1947         EXTRA_DELAY;
1948
1949         /* 10 DDR Receive FIFO RE-Sync */
1950         RAM_DEBUG_MESSAGE("Ram Enable 10\n");
1951         RAM_RESET_DDR_PTR();
1952         EXTRA_DELAY;
1953
1954         /* 11 normal operation */
1955         RAM_DEBUG_MESSAGE("Ram Enable 11\n");
1956         do_ram_command(RAM_COMMAND_NORMAL, 0);
1957         EXTRA_DELAY;
1958
1959         // Reconfigure the row boundaries and Top of Low Memory
1960         // to match the true size of the DIMMs
1961         configure_e7501_ram_addresses(ctrl, dimm_mask);
1962
1963         /* Finally enable refresh */
1964         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1965         dram_controller_mode |= (1 << 29);
1966         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1967         EXTRA_DELAY;
1968         initialize_ecc();
1969
1970         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);        /* FCS_EN */
1971         dram_controller_mode |= (1 << 17);      // NOTE: undocumented reserved bit
1972         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1973
1974         RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
1975         DUMPNORTH();
1976 }
1977
1978 //----------------------------------------------------------------------------------
1979 // Function:            sdram_set_spd_registers
1980 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1981 //                                              SMBus addresses of DIMM slots on the mainboard
1982 // Return Value:        None
1983 // Description:         Configure SDRAM controller parameters that depend on
1984 //                                      characteristics of the DIMMs installed in the system. These
1985 //                                      characteristics are read from the DIMMs via the standard Serial
1986 //                                      Presence Detect (SPD) interface.
1987 //
1988 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1989 {
1990         uint8_t dimm_mask;
1991
1992         RAM_DEBUG_MESSAGE("Reading SPD data...\n");
1993
1994         dimm_mask = spd_get_supported_dimms(ctrl);
1995
1996         if (dimm_mask == 0) {
1997                 print_debug("No usable memory for this controller\n");
1998         } else {
1999                 enable_e7501_clocks(dimm_mask);
2000
2001                 RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
2002
2003                 configure_e7501_row_attributes(ctrl, dimm_mask);
2004                 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
2005                 configure_e7501_cas_latency(ctrl, dimm_mask);
2006                 RAM_RESET_DDR_PTR();
2007
2008                 configure_e7501_dram_timing(ctrl, dimm_mask);
2009                 DO_DELAY;
2010                 RAM_DEBUG_MESSAGE("done\n");
2011         }
2012
2013         /* NOTE: configure_e7501_ram_addresses() is NOT called here.
2014          * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
2015          * even though the default mapping is almost certainly incorrect.
2016          * The default mapping makes it easy to initialize all of the DIMMs
2017          * even if the total system memory is > 4 GB.
2018          *
2019          * Save the dimm_mask for when sdram_enable is called, so it can call
2020          * configure_e7501_ram_addresses() without having to regenerate the bitmask
2021          * of usable DIMMs.
2022          */
2023         pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
2024 }
2025
2026 //----------------------------------------------------------------------------------
2027 // Function:            sdram_set_registers
2028 // Parameters:          ctrl - PCI addresses of memory controller functions, and
2029 //                             SMBus addresses of DIMM slots on the mainboard
2030 // Return Value:        None
2031 // Description:         Do basic ram setup that does NOT depend on serial presence detect
2032 //                      information (i.e. independent of DIMM specifics).
2033 //
2034 static void sdram_set_registers(const struct mem_controller *ctrl)
2035 {
2036         RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
2037         DUMPNORTH();
2038
2039         ram_set_rcomp_regs();
2040         ram_set_d0f0_regs();
2041 }
2042
2043 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
2044 /*                      PUBLIC INTERFACE                                          */
2045 /**********************************************************************************/