src/northbridge/intel/e7501/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/cpu.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11
  12 static void pci_domain_read_resources(device_t dev)
  13 {
  14         struct resource *resource;
  15         unsigned reg;
  16
  17         /* Initialize the system wide io space constraints */
  18         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  19         resource->base = 0x400; //yhlu
  20         resource->limit = 0xffffUL;
  21         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  22
  23         /* Initialize the system wide memory resources constraints */
  24         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  25         resource->limit = 0xffffffffULL;
  26         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  27 }
  28
  29 static void ram_resource(device_t dev, unsigned long index,
  30         unsigned long basek, unsigned long sizek)
  31 {
  32         struct resource *resource;
  33
  34         if (!sizek) {
  35                 return;
  36         }
  37         resource = new_resource(dev, index);
  38         resource->base  = ((resource_t)basek) << 10;
  39         resource->size  = ((resource_t)sizek) << 10;
  40         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  41                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  42 }
  43
  44 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  45 {
  46         struct resource **best_p = gp;
  47         struct resource *best;
  48         best = *best_p;
  49         if (!best || (best->base > new->base)) {
  50                 best = new;
  51         }
  52         *best_p = best;
  53 }
  54
  55 static uint32_t find_pci_tolm(struct bus *bus)
  56 {
  57         struct resource *min;
  58         uint32_t tolm;
  59         min = 0;
  60         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  61         tolm = 0xffffffffUL;
  62         if (min && tolm > min->base) {
  63                 tolm = min->base;
  64         }
  65         return tolm;
  66 }
  67
  68 static void pci_domain_set_resources(device_t dev)
  69 {
  70         device_t mc_dev;
  71         uint32_t pci_tolm;
  72
  73         pci_tolm = find_pci_tolm(&dev->link[0]);
  74         mc_dev = dev->link[0].children;
  75         if (mc_dev) {
  76                 /* Figure out which areas are/should be occupied by RAM.
  77                  * This is all computed in kilobytes and converted to/from
  78                  * the memory controller right at the edges.
  79                  * Having different variables in different units is
  80                  * too confusing to get right.  Kilobytes are good up to
  81                  * 4 Terabytes of RAM...
  82                  */
  83                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  84                 unsigned long tomk, tolmk;
  85                 unsigned long remapbasek, remaplimitk;
  86                 int idx;
  87
  88                 /* Get the value of the highest DRB. This tells the end of
  89                  * the physical memory.  The units are ticks of 64MB
  90                  * i.e. 1 means 64MB.
  91                  */
  92                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  93                 /* Compute the top of Low memory */
  94                 tolmk = pci_tolm >> 10;
  95                 if (tolmk >= tomk) {
  96                         /* The PCI hole does not overlap memory
  97                          * we won't use the remap window.
  98                          */
  99                         tolmk = tomk;
 100                         remapbasek   = 0x3ff << 16;
 101                         remaplimitk  = 0 << 16;
 102                 }
 103                 else {
 104                         /* The PCI memory hole overlaps memory
 105                          * setup the remap window.
 106                          */
 107                         /* Find the bottom of the remap window
 108                          * is it above 4G?
 109                          */
 110                         remapbasek = 4*1024*1024;
 111                         if (tomk > remapbasek) {
 112                                 remapbasek = tomk;
 113                         }
 114                         /* Find the limit of the remap window */
 115                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 116                 }
 117                 /* Write the ram configuration registers,
 118                  * preserving the reserved bits.
 119                  */
 120                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 121                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 122                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 123
 124                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 125                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 126                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 127
 128                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 129                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 130                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 131
 132                 /* Report the memory regions */
 133                 idx = 10;
 134                 ram_resource(dev, idx++, 0, 640);
 135                 ram_resource(dev, idx++, 768, tolmk - 768);
 136                 if (tomk > 4*1024*1024) {
 137                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 138                 }
 139                 if (remaplimitk >= remapbasek) {
 140                         ram_resource(dev, idx++, remapbasek,
 141                                 (remaplimitk + 64*1024) - remapbasek);
 142                 }
 143         }
 144         assign_resources(&dev->link[0]);
 145 }
 146
 147 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 148 {
 149         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 150         return max;
 151 }
 152
 153 static struct device_operations pci_domain_ops = {
 154         .read_resources   = pci_domain_read_resources,
 155         .set_resources    = pci_domain_set_resources,
 156         .enable_resources = enable_childrens_resources,
 157         .init             = 0,
 158         .scan_bus         = pci_domain_scan_bus,
 159         .ops_pci_bus      = &pci_cf8_conf1,
 160 };
 161
 162 static void cpu_bus_init(device_t dev)
 163 {
 164         initialize_cpus(&dev->link[0]);
 165 }
 166
 167 static void cpu_bus_noop(device_t dev)
 168 {
 169 }
 170
 171 static struct device_operations cpu_bus_ops = {
 172         .read_resources   = cpu_bus_noop,
 173         .set_resources    = cpu_bus_noop,
 174         .enable_resources = cpu_bus_noop,
 175         .init             = cpu_bus_init,
 176         .scan_bus         = 0,
 177 };
 178
 179 static void enable_dev(struct device *dev)
 180 {
 181         /* Set the operations if it is a special bus type */
 182         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 183                 dev->ops = &pci_domain_ops;
 184         }
 185         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 186                 dev->ops = &cpu_bus_ops;
 187         }
 188 }
 189
 190 struct chip_operations northbridge_intel_e7501_ops = {
 191         CHIP_NAME("Intel E7501 Northbridge")
 192         .enable_dev = enable_dev,
 193 };