1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
12 #if CONFIG_WRITE_HIGH_TABLES==1
13 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
14 extern uint64_t high_tables_base, high_tables_size;
17 static void pci_domain_set_resources(device_t dev)
22 pci_tolm = find_pci_tolm(dev->link_list);
23 mc_dev = dev->link_list->children;
25 /* Figure out which areas are/should be occupied by RAM.
26 * This is all computed in kilobytes and converted to/from
27 * the memory controller right at the edges.
28 * Having different variables in different units is
29 * too confusing to get right. Kilobytes are good up to
30 * 4 Terabytes of RAM...
32 uint16_t tolm_r, remapbase_r, remaplimit_r;
33 unsigned long tomk, tolmk;
34 unsigned long remapbasek, remaplimitk;
37 /* Get the value of the highest DRB. This tells the end of
38 * the physical memory. The units are ticks of 64MB
41 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
42 /* Compute the top of Low memory */
43 tolmk = pci_tolm >> 10;
45 /* The PCI hole does not overlap memory
46 * we won't use the remap window.
49 remapbasek = 0x3ff << 16;
50 remaplimitk = 0 << 16;
53 /* The PCI memory hole overlaps memory
54 * setup the remap window.
56 /* Find the bottom of the remap window
59 remapbasek = 4*1024*1024;
60 if (tomk > remapbasek) {
63 /* Find the limit of the remap window */
64 remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
66 /* Write the ram configuration registers,
67 * preserving the reserved bits.
69 tolm_r = pci_read_config16(mc_dev, 0xc4);
70 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
71 pci_write_config16(mc_dev, 0xc4, tolm_r);
73 remapbase_r = pci_read_config16(mc_dev, 0xc6);
74 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
75 pci_write_config16(mc_dev, 0xc6, remapbase_r);
77 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
78 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
79 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
81 /* Report the memory regions */
83 ram_resource(dev, idx++, 0, 640);
84 ram_resource(dev, idx++, 768, tolmk - 768);
85 if (tomk > 4*1024*1024) {
86 ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
88 if (remaplimitk >= remapbasek) {
89 ram_resource(dev, idx++, remapbasek,
90 (remaplimitk + 64*1024) - remapbasek);
93 #if CONFIG_WRITE_HIGH_TABLES==1
94 /* Leave some space for ACPI, PIRQ and MP tables */
95 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
96 high_tables_size = HIGH_TABLES_SIZE * 1024;
99 assign_resources(dev->link_list);
102 static struct device_operations pci_domain_ops = {
103 .read_resources = pci_domain_read_resources,
104 .set_resources = pci_domain_set_resources,
105 .enable_resources = NULL,
107 .scan_bus = pci_domain_scan_bus,
108 .ops_pci_bus = &pci_cf8_conf1,
111 static void cpu_bus_init(device_t dev)
113 initialize_cpus(dev->link_list);
116 static void cpu_bus_noop(device_t dev)
120 static struct device_operations cpu_bus_ops = {
121 .read_resources = cpu_bus_noop,
122 .set_resources = cpu_bus_noop,
123 .enable_resources = cpu_bus_noop,
124 .init = cpu_bus_init,
128 static void enable_dev(struct device *dev)
130 /* Set the operations if it is a special bus type */
131 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
132 dev->ops = &pci_domain_ops;
134 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
135 dev->ops = &cpu_bus_ops;
139 struct chip_operations northbridge_intel_e7501_ops = {
140 CHIP_NAME("Intel E7501 Northbridge")
141 .enable_dev = enable_dev,