src/northbridge/intel/e7501/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/cpu.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11
  12 static void pci_domain_read_resources(device_t dev)
  13 {
  14         struct resource *resource;
  15         unsigned reg;
  16
  17         /* Initialize the system wide io space constraints */
  18         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  19         resource->base = 0x400; //yhlu
  20         resource->limit = 0xffffUL;
  21         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  22
  23         /* Initialize the system wide memory resources constraints */
  24         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  25         resource->limit = 0xffffffffULL;
  26         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  27 }
  28
  29 static void ram_resource(device_t dev, unsigned long index,
  30         unsigned long basek, unsigned long sizek)
  31 {
  32         struct resource *resource;
  33
  34         if (!sizek) {
  35                 return;
  36         }
  37         resource = new_resource(dev, index);
  38         resource->base  = ((resource_t)basek) << 10;
  39         resource->size  = ((resource_t)sizek) << 10;
  40         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  41                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  42 }
  43
  44 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  45 {
  46         struct resource **best_p = gp;
  47         struct resource *best;
  48         best = *best_p;
  49         if (!best || (best->base > new->base)) {
  50                 best = new;
  51         }
  52         *best_p = best;
  53 }
  54
  55 static uint32_t find_pci_tolm(struct bus *bus)
  56 {
  57         struct resource *min;
  58         uint32_t tolm;
  59         min = 0;
  60         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  61         tolm = 0xffffffffUL;
  62         if (min && tolm > min->base) {
  63                 tolm = min->base;
  64         }
  65         return tolm;
  66 }
  67
  68 #if HAVE_HIGH_TABLES==1
  69 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  70 extern uint64_t high_tables_base, high_tables_size;
  71 #endif
  72
  73 static void pci_domain_set_resources(device_t dev)
  74 {
  75         device_t mc_dev;
  76         uint32_t pci_tolm;
  77
  78         pci_tolm = find_pci_tolm(&dev->link[0]);
  79         mc_dev = dev->link[0].children;
  80         if (mc_dev) {
  81                 /* Figure out which areas are/should be occupied by RAM.
  82                  * This is all computed in kilobytes and converted to/from
  83                  * the memory controller right at the edges.
  84                  * Having different variables in different units is
  85                  * too confusing to get right.  Kilobytes are good up to
  86                  * 4 Terabytes of RAM...
  87                  */
  88                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  89                 unsigned long tomk, tolmk;
  90                 unsigned long remapbasek, remaplimitk;
  91                 int idx;
  92
  93                 /* Get the value of the highest DRB. This tells the end of
  94                  * the physical memory.  The units are ticks of 64MB
  95                  * i.e. 1 means 64MB.
  96                  */
  97                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  98                 /* Compute the top of Low memory */
  99                 tolmk = pci_tolm >> 10;
 100                 if (tolmk >= tomk) {
 101                         /* The PCI hole does not overlap memory
 102                          * we won't use the remap window.
 103                          */
 104                         tolmk = tomk;
 105                         remapbasek   = 0x3ff << 16;
 106                         remaplimitk  = 0 << 16;
 107                 }
 108                 else {
 109                         /* The PCI memory hole overlaps memory
 110                          * setup the remap window.
 111                          */
 112                         /* Find the bottom of the remap window
 113                          * is it above 4G?
 114                          */
 115                         remapbasek = 4*1024*1024;
 116                         if (tomk > remapbasek) {
 117                                 remapbasek = tomk;
 118                         }
 119                         /* Find the limit of the remap window */
 120                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 121                 }
 122                 /* Write the ram configuration registers,
 123                  * preserving the reserved bits.
 124                  */
 125                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 126                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 127                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 128
 129                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 130                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 131                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 132
 133                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 134                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 135                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 136
 137                 /* Report the memory regions */
 138                 idx = 10;
 139                 ram_resource(dev, idx++, 0, 640);
 140                 ram_resource(dev, idx++, 768, tolmk - 768);
 141                 if (tomk > 4*1024*1024) {
 142                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 143                 }
 144                 if (remaplimitk >= remapbasek) {
 145                         ram_resource(dev, idx++, remapbasek,
 146                                 (remaplimitk + 64*1024) - remapbasek);
 147                 }
 148
 149 #if HAVE_HIGH_TABLES==1
 150                 /* Leave some space for ACPI, PIRQ and MP tables */
 151                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 152                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 153 #endif
 154         }
 155         assign_resources(&dev->link[0]);
 156 }
 157
 158 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 159 {
 160         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 161         return max;
 162 }
 163
 164 static struct device_operations pci_domain_ops = {
 165         .read_resources   = pci_domain_read_resources,
 166         .set_resources    = pci_domain_set_resources,
 167         .enable_resources = enable_childrens_resources,
 168         .init             = 0,
 169         .scan_bus         = pci_domain_scan_bus,
 170         .ops_pci_bus      = &pci_cf8_conf1,
 171 };
 172
 173 static void cpu_bus_init(device_t dev)
 174 {
 175         initialize_cpus(&dev->link[0]);
 176 }
 177
 178 static void cpu_bus_noop(device_t dev)
 179 {
 180 }
 181
 182 static struct device_operations cpu_bus_ops = {
 183         .read_resources   = cpu_bus_noop,
 184         .set_resources    = cpu_bus_noop,
 185         .enable_resources = cpu_bus_noop,
 186         .init             = cpu_bus_init,
 187         .scan_bus         = 0,
 188 };
 189
 190 static void enable_dev(struct device *dev)
 191 {
 192         /* Set the operations if it is a special bus type */
 193         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 194                 dev->ops = &pci_domain_ops;
 195         }
 196         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 197                 dev->ops = &cpu_bus_ops;
 198         }
 199 }
 200
 201 struct chip_operations northbridge_intel_e7501_ops = {
 202         CHIP_NAME("Intel E7501 Northbridge")
 203         .enable_dev = enable_dev,
 204 };