src/northbridge/intel/e7501/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <bitops.h>
   9 #include "chip.h"
  10
  11 static void pci_domain_read_resources(device_t dev)
  12 {
  13         struct resource *resource;
  14         unsigned reg;
  15
  16         /* Initialize the system wide io space constraints */
  17         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  18         resource->base = 0x400; //yhlu
  19         resource->limit = 0xffffUL;
  20         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  21
  22         /* Initialize the system wide memory resources constraints */
  23         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  24         resource->limit = 0xffffffffULL;
  25         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  26 }
  27
  28 static void ram_resource(device_t dev, unsigned long index,
  29         unsigned long basek, unsigned long sizek)
  30 {
  31         struct resource *resource;
  32
  33         if (!sizek) {
  34                 return;
  35         }
  36         resource = new_resource(dev, index);
  37         resource->base  = ((resource_t)basek) << 10;
  38         resource->size  = ((resource_t)sizek) << 10;
  39         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  40                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  41 }
  42
  43 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  44 {
  45         struct resource **best_p = gp;
  46         struct resource *best;
  47         best = *best_p;
  48         if (!best || (best->base > new->base)) {
  49                 best = new;
  50         }
  51         *best_p = best;
  52 }
  53
  54 static uint32_t find_pci_tolm(struct bus *bus)
  55 {
  56         struct resource *min;
  57         uint32_t tolm;
  58         min = 0;
  59         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  60         tolm = 0xffffffffUL;
  61         if (min && tolm > min->base) {
  62                 tolm = min->base;
  63         }
  64         return tolm;
  65 }
  66
  67 static void pci_domain_set_resources(device_t dev)
  68 {
  69         device_t mc_dev;
  70         uint32_t pci_tolm;
  71
  72         pci_tolm = find_pci_tolm(&dev->link[0]);
  73         mc_dev = dev->link[0].children;
  74         if (mc_dev) {
  75                 /* Figure out which areas are/should be occupied by RAM.
  76                  * This is all computed in kilobytes and converted to/from
  77                  * the memory controller right at the edges.
  78                  * Having different variables in different units is
  79                  * too confusing to get right.  Kilobytes are good up to
  80                  * 4 Terabytes of RAM...
  81                  */
  82                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  83                 unsigned long tomk, tolmk;
  84                 unsigned long remapbasek, remaplimitk;
  85                 int idx;
  86
  87                 /* Get the value of the highest DRB. This tells the end of
  88                  * the physical memory.  The units are ticks of 64MB
  89                  * i.e. 1 means 64MB.
  90                  */
  91                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  92                 /* Compute the top of Low memory */
  93                 tolmk = pci_tolm >> 10;
  94                 if (tolmk >= tomk) {
  95                         /* The PCI hole does not overlap memory
  96                          * we won't use the remap window.
  97                          */
  98                         tolmk = tomk;
  99                         remapbasek   = 0x3ff << 16;
 100                         remaplimitk  = 0 << 16;
 101                 }
 102                 else {
 103                         /* The PCI memory hole overlaps memory
 104                          * setup the remap window.
 105                          */
 106                         /* Find the bottom of the remap window
 107                          * is it above 4G?
 108                          */
 109                         remapbasek = 4*1024*1024;
 110                         if (tomk > remapbasek) {
 111                                 remapbasek = tomk;
 112                         }
 113                         /* Find the limit of the remap window */
 114                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 115                 }
 116                 /* Write the ram configuration registers,
 117                  * preserving the reserved bits.
 118                  */
 119                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 120                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 121                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 122
 123                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 124                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 125                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 126
 127                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 128                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 129                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 130
 131                 /* Report the memory regions */
 132                 idx = 10;
 133                 ram_resource(dev, idx++, 0, 640);
 134                 ram_resource(dev, idx++, 768, tolmk - 768);
 135                 if (tomk > 4*1024*1024) {
 136                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 137                 }
 138                 if (remaplimitk >= remapbasek) {
 139                         ram_resource(dev, idx++, remapbasek,
 140                                 (remaplimitk + 64*1024) - remapbasek);
 141                 }
 142         }
 143         assign_resources(&dev->link[0]);
 144 }
 145
 146 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 147 {
 148         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 149         return max;
 150 }
 151
 152 static struct device_operations pci_domain_ops = {
 153         .read_resources   = pci_domain_read_resources,
 154         .set_resources    = pci_domain_set_resources,
 155         .enable_resources = enable_childrens_resources,
 156         .init             = 0,
 157         .scan_bus         = pci_domain_scan_bus,
 158         .ops_pci_bus      = &pci_cf8_conf1,
 159 };
 160
 161 static void cpu_bus_init(device_t dev)
 162 {
 163         initialize_cpus(&dev->link[0]);
 164 }
 165
 166 static void cpu_bus_noop(device_t dev)
 167 {
 168 }
 169
 170 static struct device_operations cpu_bus_ops = {
 171         .read_resources   = cpu_bus_noop,
 172         .set_resources    = cpu_bus_noop,
 173         .enable_resources = cpu_bus_noop,
 174         .init             = cpu_bus_init,
 175         .scan_bus         = 0,
 176 };
 177
 178 static void enable_dev(struct device *dev)
 179 {
 180         /* Set the operations if it is a special bus type */
 181         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 182                 dev->ops = &pci_domain_ops;
 183         }
 184         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 185                 dev->ops = &cpu_bus_ops;
 186         }
 187 }
 188
 189 struct chip_operations northbridge_intel_e7501_ops = {
 190         CHIP_NAME("Intel E7501 Northbridge")
 191         .enable_dev = enable_dev,
 192 };