src/northbridge/intel/e7501/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/cpu.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11
  12 static void ram_resource(device_t dev, unsigned long index,
  13         unsigned long basek, unsigned long sizek)
  14 {
  15         struct resource *resource;
  16
  17         if (!sizek) {
  18                 return;
  19         }
  20         resource = new_resource(dev, index);
  21         resource->base  = ((resource_t)basek) << 10;
  22         resource->size  = ((resource_t)sizek) << 10;
  23         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  24                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  25 }
  26
  27 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  28 {
  29         struct resource **best_p = gp;
  30         struct resource *best;
  31         best = *best_p;
  32         if (!best || (best->base > new->base)) {
  33                 best = new;
  34         }
  35         *best_p = best;
  36 }
  37
  38 static uint32_t find_pci_tolm(struct bus *bus)
  39 {
  40         struct resource *min;
  41         uint32_t tolm;
  42         min = 0;
  43         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  44         tolm = 0xffffffffUL;
  45         if (min && tolm > min->base) {
  46                 tolm = min->base;
  47         }
  48         return tolm;
  49 }
  50
  51 #if CONFIG_WRITE_HIGH_TABLES==1
  52 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  53 extern uint64_t high_tables_base, high_tables_size;
  54 #endif
  55
  56 static void pci_domain_set_resources(device_t dev)
  57 {
  58         device_t mc_dev;
  59         uint32_t pci_tolm;
  60
  61         pci_tolm = find_pci_tolm(dev->link_list);
  62         mc_dev = dev->link_list->children;
  63         if (mc_dev) {
  64                 /* Figure out which areas are/should be occupied by RAM.
  65                  * This is all computed in kilobytes and converted to/from
  66                  * the memory controller right at the edges.
  67                  * Having different variables in different units is
  68                  * too confusing to get right.  Kilobytes are good up to
  69                  * 4 Terabytes of RAM...
  70                  */
  71                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  72                 unsigned long tomk, tolmk;
  73                 unsigned long remapbasek, remaplimitk;
  74                 int idx;
  75
  76                 /* Get the value of the highest DRB. This tells the end of
  77                  * the physical memory.  The units are ticks of 64MB
  78                  * i.e. 1 means 64MB.
  79                  */
  80                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  81                 /* Compute the top of Low memory */
  82                 tolmk = pci_tolm >> 10;
  83                 if (tolmk >= tomk) {
  84                         /* The PCI hole does not overlap memory
  85                          * we won't use the remap window.
  86                          */
  87                         tolmk = tomk;
  88                         remapbasek   = 0x3ff << 16;
  89                         remaplimitk  = 0 << 16;
  90                 }
  91                 else {
  92                         /* The PCI memory hole overlaps memory
  93                          * setup the remap window.
  94                          */
  95                         /* Find the bottom of the remap window
  96                          * is it above 4G?
  97                          */
  98                         remapbasek = 4*1024*1024;
  99                         if (tomk > remapbasek) {
 100                                 remapbasek = tomk;
 101                         }
 102                         /* Find the limit of the remap window */
 103                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 104                 }
 105                 /* Write the ram configuration registers,
 106                  * preserving the reserved bits.
 107                  */
 108                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 109                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 110                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 111
 112                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 113                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 114                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 115
 116                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 117                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 118                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 119
 120                 /* Report the memory regions */
 121                 idx = 10;
 122                 ram_resource(dev, idx++, 0, 640);
 123                 ram_resource(dev, idx++, 768, tolmk - 768);
 124                 if (tomk > 4*1024*1024) {
 125                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 126                 }
 127                 if (remaplimitk >= remapbasek) {
 128                         ram_resource(dev, idx++, remapbasek,
 129                                 (remaplimitk + 64*1024) - remapbasek);
 130                 }
 131
 132 #if CONFIG_WRITE_HIGH_TABLES==1
 133                 /* Leave some space for ACPI, PIRQ and MP tables */
 134                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 135                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 136 #endif
 137         }
 138         assign_resources(dev->link_list);
 139 }
 140
 141 static struct device_operations pci_domain_ops = {
 142         .read_resources   = pci_domain_read_resources,
 143         .set_resources    = pci_domain_set_resources,
 144         .enable_resources = NULL,
 145         .init             = NULL,
 146         .scan_bus         = pci_domain_scan_bus,
 147         .ops_pci_bus      = &pci_cf8_conf1,
 148 };
 149
 150 static void cpu_bus_init(device_t dev)
 151 {
 152         initialize_cpus(dev->link_list);
 153 }
 154
 155 static void cpu_bus_noop(device_t dev)
 156 {
 157 }
 158
 159 static struct device_operations cpu_bus_ops = {
 160         .read_resources   = cpu_bus_noop,
 161         .set_resources    = cpu_bus_noop,
 162         .enable_resources = cpu_bus_noop,
 163         .init             = cpu_bus_init,
 164         .scan_bus         = 0,
 165 };
 166
 167 static void enable_dev(struct device *dev)
 168 {
 169         /* Set the operations if it is a special bus type */
 170         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 171                 dev->ops = &pci_domain_ops;
 172         }
 173         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 174                 dev->ops = &cpu_bus_ops;
 175         }
 176 }
 177
 178 struct chip_operations northbridge_intel_e7501_ops = {
 179         CHIP_NAME("Intel E7501 Northbridge")
 180         .enable_dev = enable_dev,
 181 };