src/northbridge/ibm/cpc710/cpc710_northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <bitops.h>
   9 #include <cpu/cpu.h>
  10 #include "chip.h"
  11
  12 static void pci_domain_read_resources(device_t dev)
  13 {
  14         struct resource *resource;
  15
  16         /* Initialize the system wide io space constraints */
  17         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  18         resource->base  = 0;
  19         resource->limit = 0xffffUL;
  20         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  21
  22         /* Initialize the system wide memory resources constraints */
  23         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  24         resource->base  = 0x80000000ULL;
  25         resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
  26         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  27 }
  28
  29 static void ram_resource(device_t dev, unsigned long index,
  30         unsigned long basek, unsigned long sizek)
  31 {
  32         struct resource *resource;
  33
  34         if (!sizek) {
  35                 return;
  36         }
  37         resource = new_resource(dev, index);
  38         resource->base  = ((resource_t)basek) << 10;
  39         resource->size  = ((resource_t)sizek) << 10;
  40         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  41                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  42 }
  43
  44 static void pci_domain_set_resources(device_t dev)
  45 {
  46         int idx;
  47
  48         /* Report the memory regions */
  49         idx = 10;
  50         ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
  51
  52         /* And assign the resources */
  53         assign_resources(&dev->link[0]);
  54 }
  55
  56
  57 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
  58 {
  59         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
  60         return max;
  61 }
  62
  63 static struct device_operations pci_domain_ops = {
  64         .read_resources   = pci_domain_read_resources,
  65         .set_resources    = pci_domain_set_resources,
  66         .enable_resources = enable_childrens_resources,
  67         .init             = 0,
  68         .scan_bus         = pci_domain_scan_bus,
  69         .ops_pci_bus      = &pci_ppc_conf1,
  70 };
  71
  72 static void cpu_bus_init(device_t dev)
  73 {
  74         initialize_cpus(&dev->link[0]);
  75 }
  76
  77 static void cpu_bus_noop(device_t dev)
  78 {
  79 }
  80
  81 static struct device_operations cpu_bus_ops = {
  82         .read_resources   = cpu_bus_noop,
  83         .set_resources    = cpu_bus_noop,
  84         .enable_resources = cpu_bus_noop,
  85         .init             = cpu_bus_init,
  86         .scan_bus         = 0,
  87 };
  88
  89 static void enable_dev(struct device *dev)
  90 {
  91         /* Set the operations if it is a special bus type */
  92         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
  93                 dev->ops = &pci_domain_ops;
  94         }
  95         else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
  96                 dev->ops = &cpu_bus_ops;
  97         }
  98 }
  99
 100 struct chip_operations northbridge_ibm_cpc710_ops = {
 101         CHIP_NAME("IBM CPC710 Northbridge")
 102         .enable_dev = enable_dev,
 103 };