2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <cpu/amd/lxdef.h>
23 #include "southbridge/amd/cs5536/cs5536.h"
25 static const unsigned char NumColAddr[] = {
26 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
27 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
30 static void banner(const char *s)
32 printk(BIOS_DEBUG, " * %s\n", s);
38 /* this guarantees we flush the UART fifos (if any) and also
39 * ensures that things, in general, keep going so no debug output
46 static void auto_size_dimm(unsigned int dimm)
48 uint32_t dimm_setting;
55 banner("Check present");
56 /* Check that we have a dimm */
57 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
62 /* Field: Module Banks per DIMM */
63 /* EEPROM byte usage: (5) Number of DIMM Banks */
64 spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
65 if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
66 print_emerg("Number of module banks not compatible\n");
67 post_code(ERROR_BANK_SET);
70 dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
73 /* Field: Banks per SDRAM device */
74 /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
75 spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
76 if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
77 print_emerg("Number of device banks not compatible\n");
78 post_code(ERROR_BANK_SET);
81 dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
85 *; EEPROM byte usage: (3) Number of Row Addresses
86 *; (4) Number of Column Addresses
87 *; (5) Number of DIMM Banks
88 *; (31) Module Bank Density
89 *; Size = Module Density * Module Banks
91 if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
92 || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
93 print_emerg("Assymetirc DIMM not compatible\n");
94 post_code(ERROR_UNSUPPORTED_DIMM);
97 banner("SPDBANKDENSITY");
99 dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
101 dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
102 dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
104 /* Module Density * Module Banks */
105 dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
106 banner("BEFORT CTZ");
107 dimm_size = __builtin_ctz(dimm_size);
108 banner("TEST DIMM SIZE>8");
109 if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
110 print_emerg("Only support up to 1 GB per DIMM\n");
111 post_code(ERROR_DENSITY_DIMM);
114 dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
118 *; EEPROM byte usage: (4) Number of Column Addresses
119 *; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
121 *; But this really works by magic.
122 *;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
123 *;that MC generates, here is how the MC assigns the pa onto the ma pins:
125 *;ma 12 11 10 09 08 07 06 05 04 03 02 01 00
126 *;-------------------------------------------
127 *;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
128 *;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
129 *;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
130 *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
131 *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
132 *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)
133 *; *AP=autoprecharge bit
135 *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
136 *;so lower 3 address bits are dont_cares.So from the table above,
137 *;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
138 *;it adds 3 to get 10, then does 2^10=1K. Get it?*/
140 spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
141 banner("MAXCOLADDR");
142 if (spd_byte > MAX_COL_ADDR) {
143 print_emerg("DIMM page size not compatible\n");
144 post_code(ERROR_SET_PAGE);
147 banner(">12address test");
149 if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
150 spd_byte = 7; /* which means >32k so set to disabled */
152 dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
154 banner("RDMSR CF07");
155 msr = rdmsr(MC_CF07_DATA);
156 banner("WRMSR CF07");
158 msr.hi &= 0xFFFF0000;
159 msr.hi |= dimm_setting;
161 msr.hi &= 0x0000FFFF;
162 msr.hi |= dimm_setting << 16;
164 wrmsr(MC_CF07_DATA, msr);
168 static void checkDDRMax(void)
170 uint8_t spd_byte0, spd_byte1;
173 /* PC133 identifier */
174 spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
175 if (spd_byte0 == 0xFF) {
178 spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
179 if (spd_byte1 == 0xFF) {
183 /* I don't think you need this check.
184 if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
185 print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
186 post_code(POST_PLL_MEM_FAIL);
190 /* Use the slowest DIMM */
191 if (spd_byte0 < spd_byte1) {
192 spd_byte0 = spd_byte1;
195 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
196 speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
198 /* current speed > max speed? */
199 if (GeodeLinkSpeed() > speed) {
200 print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
201 post_code(POST_PLL_MEM_FAIL);
206 const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
208 static void set_refresh_rate(void)
210 uint8_t spd_byte0, spd_byte1;
211 uint16_t rate0, rate1;
214 spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
219 rate0 = REF_RATE[spd_byte0];
221 spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
226 rate1 = REF_RATE[spd_byte1];
228 /* Use the faster rate (lowest number) */
233 msr = rdmsr(MC_CF07_DATA);
234 msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
235 << CF07_LOWER_REF_INT_SHIFT;
236 wrmsr(MC_CF07_DATA, msr);
239 const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
241 static void setCAS(void)
243 /*;*****************************************************************************
246 ;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
247 ;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
248 ;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
250 ;* The CAS setting is based on the information provided in each DIMMs SPD.
251 ;* The speed at which a DIMM can run is described relative to the slowest
252 ;* CAS the DIMM supports. Each speed for the relative CAS settings is
253 ;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
254 ;* speed, the CAS setting is removed from the list of good settings for
255 ;* the DIMM. This is done for both DIMMs and the lists are compared to
256 ;* find the lowest common CAS latency setting. If there are no CAS settings
257 ;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
260 ;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
261 ;* Destroys: We really use everything !
262 ;*****************************************************************************/
263 uint16_t glspeed, dimm_speed;
264 uint8_t spd_byte, casmap0, casmap1, casmap_shift;
267 glspeed = GeodeLinkSpeed();
269 /************************** DIMM0 **********************************/
270 casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
271 if (casmap0 != 0xFF) {
272 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
273 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
275 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
276 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
277 if (dimm_speed >= glspeed) {
278 casmap_shift = 1; /* -.5 is a shift of 1 */
279 /* IF -1 timing is supported, check -1 timing > GeodeLink */
280 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
282 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
283 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
284 if (dimm_speed >= glspeed) {
285 casmap_shift = 2; /* -1 is a shift of 2 */
287 } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
291 } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
292 /* set the casmap based on the shift to limit possible CAS settings */
293 spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
294 /* just want bits in the lower byte since we have to cast to a 32 */
295 casmap0 &= 0xFF << (spd_byte - casmap_shift);
296 } else { /* No DIMM */
300 /************************** DIMM1 **********************************/
301 casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
302 if (casmap1 != 0xFF) {
303 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
304 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
306 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
307 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
308 if (dimm_speed >= glspeed) {
309 casmap_shift = 1; /* -.5 is a shift of 1 */
310 /* IF -1 timing is supported, check -1 timing > GeodeLink */
311 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
313 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
314 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
315 if (dimm_speed >= glspeed) {
316 casmap_shift = 2; /* -1 is a shift of 2 */
318 /* note that the -1 result doesn't need to change the available CAS map */
319 } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
323 } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
324 /* set the casmap based on the shift to limit possible CAS settings */
325 spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
326 /* just want bits in the lower byte since we have to cast to a 32 */
327 casmap1 &= 0xFF << (spd_byte - casmap_shift);
328 } else { /* No DIMM */
332 /********************* CAS_LAT MAP COMPARE ***************************/
334 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
335 } else if (casmap1 == 0) {
336 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
337 } else if ((casmap0 &= casmap1)) {
338 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
340 print_emerg("DIMM CAS Latencies not compatible\n");
341 post_code(ERROR_DIFF_DIMMS);
345 msr = rdmsr(MC_CF8F_DATA);
346 msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
347 msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
348 wrmsr(MC_CF8F_DATA, msr);
351 static void set_latencies(void)
353 uint32_t memspeed, dimm_setting;
354 uint8_t spd_byte0, spd_byte1;
357 memspeed = GeodeLinkSpeed() / 2;
362 spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
363 if (spd_byte0 == 0xFF) {
366 spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
367 if (spd_byte1 == 0xFF) {
370 if (spd_byte0 < spd_byte1) {
371 spd_byte0 = spd_byte1;
374 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
375 spd_byte1 = (spd_byte0 * memspeed) / 1000;
376 if (((spd_byte0 * memspeed) % 1000)) {
379 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
382 spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
383 if (spd_byte0 == 0xFF) {
386 spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
387 if (spd_byte1 == 0xFF) {
390 if (spd_byte0 < spd_byte1) {
391 spd_byte0 = spd_byte1;
394 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
395 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
396 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
399 dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
402 spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
403 if (spd_byte0 == 0xFF) {
406 spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
407 if (spd_byte1 == 0xFF) {
410 if (spd_byte0 < spd_byte1) {
411 spd_byte0 = spd_byte1;
414 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
415 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
416 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
419 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
422 spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
423 if (spd_byte0 == 0xFF) {
426 spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
427 if (spd_byte1 == 0xFF) {
430 if (spd_byte0 < spd_byte1) {
431 spd_byte0 = spd_byte1;
434 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
435 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
436 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
439 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
441 /* tRC = tRP + tRAS */
442 dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
443 ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
444 << CF8F_LOWER_ACT2ACTREF_SHIFT;
446 msr = rdmsr(MC_CF8F_DATA);
447 msr.lo &= 0xF00000FF;
448 msr.lo |= dimm_setting;
449 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
450 wrmsr(MC_CF8F_DATA, msr);
452 /* MC_CF1017 setup */
454 spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
455 if (spd_byte0 == 0xFF) {
458 spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
459 if (spd_byte1 == 0xFF) {
462 if (spd_byte0 < spd_byte1) {
463 spd_byte0 = spd_byte1;
467 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
468 spd_byte1 = (spd_byte0 * memspeed) / 1000;
469 if (((spd_byte0 * memspeed) % 1000)) {
472 } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
473 spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
475 dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
476 msr = rdmsr(MC_CF1017_DATA);
477 msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
478 msr.lo |= dimm_setting;
479 wrmsr(MC_CF1017_DATA, msr);
481 /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
482 if (memspeed > 198) {
483 msr = rdmsr(MC_CF1017_DATA);
484 msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
485 msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
486 wrmsr(MC_CF1017_DATA, msr);
490 static void set_extended_mode_registers(void)
492 uint8_t spd_byte0, spd_byte1;
494 spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
495 if (spd_byte0 == 0xFF) {
498 spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
499 if (spd_byte1 == 0xFF) {
502 spd_byte1 &= spd_byte0;
504 msr = rdmsr(MC_CF07_DATA);
505 if (spd_byte1 & 1) { /* Drive Strength Control */
506 msr.lo |= CF07_LOWER_EMR_DRV_SET;
508 if (spd_byte1 & 2) { /* FET Control */
509 msr.lo |= CF07_LOWER_EMR_QFC_SET;
511 wrmsr(MC_CF07_DATA, msr);
514 #undef TLA_MEMORY_DEBUG
515 #ifdef TLA_MEMORY_DEBUG
516 static void EnableMTest(void)
520 msr = rdmsr(GLCP_DELAY_CONTROLS);
521 msr.hi &= ~(7 << 20); /* clear bits 54:52 */
522 if (GeodeLinkSpeed() < 200) {
525 wrmsr(GLCP_DELAY_CONTROLS, msr);
527 msr = rdmsr(MC_CFCLK_DBUG);
529 CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
530 CFCLK_UPPER_MTST_RBEX_EN_SET;
531 msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
532 wrmsr(MC_CFCLK_DBUG, msr);
534 print_info("Enabled MTest for TLA debug\n");
538 static void sdram_set_registers(const struct mem_controller *ctrl)
543 /* Set Timing Control */
544 msrnum = MC_CF1017_DATA;
546 msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
547 if (GeodeLinkSpeed() < 334) {
548 msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
550 msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
554 /* Set Refresh Staggering */
555 msrnum = MC_CF07_DATA;
558 msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
561 /* Memory Interleave: Set HOI here otherwise default is LOI */
562 /* msrnum = MC_CF8F_DATA;
564 msr.hi |= CF8F_UPPER_HOI_LOI_SET;
565 wrmsr(msrnum, msr); */
568 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
572 banner("sdram_set_spd_register");
573 post_code(POST_MEM_SETUP); // post_70h
575 spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
576 banner("Check DIMM 0");
577 /* Check DIMM is not Register and not Buffered DIMMs. */
578 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
579 print_emerg("DIMM0 NOT COMPATIBLE\n");
580 post_code(ERROR_UNSUPPORTED_DIMM);
583 banner("Check DIMM 1");
584 spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
585 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
586 print_emerg("DIMM1 NOT COMPATIBLE\n");
587 post_code(ERROR_UNSUPPORTED_DIMM);
591 post_code(POST_MEM_SETUP2); // post_72h
592 banner("Check DDR MAX");
594 /* Check that the memory is not overclocked. */
598 post_code(POST_MEM_SETUP3); // post_73h
599 banner("AUTOSIZE DIMM 0");
600 auto_size_dimm(DIMM0);
601 post_code(POST_MEM_SETUP4); // post_74h
602 banner("AUTOSIZE DIMM 1");
603 auto_size_dimm(DIMM1);
605 /* Set CAS latency */
606 banner("set cas latency");
607 post_code(POST_MEM_SETUP5); // post_75h
610 /* Set all the other latencies here (tRAS, tRP....) */
611 banner("set all latency");
614 /* Set Extended Mode Registers */
616 set_extended_mode_registers();
618 banner("set ref rate");
619 /* Set Memory Refresh Rate */
624 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
625 * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
626 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
631 /*********************************************************************
632 ;* Turn on MC/DIMM interface per JEDEC
633 ;* 1) Clock stabilizes > 200us
635 ;* 3) Precharge All to put all banks into an idles state
636 ;* 4) EMRS to enable DLL
637 ;* 6) MRS w/ memory config & reset DLL set
638 ;* 7) Wait 200 clocks (2us)
639 ;* 8) Precharge All and 2 Auto refresh
640 ;* 9) MRS w/ memory config & reset DLL clear
641 ;* 8) DDR SDRAM ready for normal operation
642 ;********************************************************************/
643 post_code(POST_MEM_ENABLE); // post_76h
645 #ifdef TLA_MEMORY_DEBUG
646 /* Only enable MTest for TLA memory debug */
650 /* If both Page Size = "Not Installed" we have a problems and should halt. */
651 msr = rdmsr(MC_CF07_DATA);
652 if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
653 ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
654 print_emerg("No memory in the system\n");
655 post_code(ERROR_NO_DIMMS);
660 msrnum = MC_CFCLK_DBUG;
662 msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
665 /* Force Precharge All on next command, EMRS */
666 msrnum = MC_CFCLK_DBUG;
668 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
671 /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
672 msrnum = MC_CF07_DATA;
674 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
676 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
679 /* Clear Force Precharge All */
680 msrnum = MC_CFCLK_DBUG;
682 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
685 /* MRS Reset DLL - set */
686 msrnum = MC_CF07_DATA;
688 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
690 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
693 /* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
694 /* Wait 2 PORT61 ticks. between 15us and 30us */
695 /* This would be endless if the timer is stuck. */
696 while ((inb(0x61))) ; /* find the first edge */
697 while (!(~inb(0x61))) ;
699 /* Force Precharge All on the next command, auto-refresh */
700 msrnum = MC_CFCLK_DBUG;
702 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
705 /* Manually AUTO refresh #1 */
706 /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
707 msrnum = MC_CF07_DATA;
709 msr.lo |= CF07_LOWER_REF_TEST_SET;
711 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
714 /* Clear Force Precharge All */
715 msrnum = MC_CFCLK_DBUG;
717 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
720 /* Manually AUTO refresh */
721 /* The MC should insert the right delay between the refreshes */
722 msrnum = MC_CF07_DATA;
724 msr.lo |= CF07_LOWER_REF_TEST_SET;
726 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
729 /* MRS Reset DLL - clear */
730 msrnum = MC_CF07_DATA;
732 msr.lo |= CF07_LOWER_PROG_DRAM_SET;
734 msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
737 /* Allow MC to tristate during idle cycles with MTEST OFF */
738 msrnum = MC_CFCLK_DBUG;
740 msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
743 /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
744 msr = rdmsr(MC_CF07_DATA);
745 if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
746 (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
747 msrnum = GLCP_DELAY_CONTROLS;
749 msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
753 /* Set PMode0 Sensitivity Counter */
754 msr.lo = 0; /* pmode 0=0 most aggressive */
755 msr.hi = 0x200; /* pmode 1=200h */
756 wrmsr(MC_CF_PMCTR, msr);
758 /* Set PMode1 Up delay enable */
759 msrnum = MC_CF1017_DATA;
761 msr.lo |= (209 << 8); /* bits[15:8] = 209 */
764 print_emerg("DRAM controller init done.\n");
765 post_code(POST_MEM_SETUP_GOOD); //0x7E
767 /* make sure there is nothing stale in the cache */
768 /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
770 /* The RAM dll needs a write to lock on so generate a few dummy writes */
771 /* Note: The descriptor needs to be enabled to point at memory */
772 volatile unsigned long *ptr;
773 for (i = 0; i < 5; i++) {
775 *ptr = (unsigned long)i;
777 /* SWAPSiF for PBZ 4112 (Errata 34) */
778 /* check for failed DLL settings now that we have done a memory write. */
779 msrnum = GLCP_DELAY_CONTROLS;
781 if ((msr.lo & 0x7FF) == 0x104) {
783 /* If you had it you would need to clear out the fail boot count flag */
784 /* (depending on where it counts from etc). */
786 /* The reset we are about to perform clears the PM_SSC register in the */
787 /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
788 /* it would do a normal boot */
790 /* Reset the system */
791 msrnum = MDD_SOFT_RESET;
796 print_info("RAM DLL lock\n");