1 #include <cpu/amd/gx2def.h>
3 static void sdram_set_registers(const struct mem_controller *ctrl)
7 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
8 * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
9 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
14 /* 2. clock gating for PMode */
15 msr = rdmsr(0x20002004);
18 wrmsr(0x20002004, msr);
19 /* undocmented bits in GX, in LX there are
20 * 8 bits in PM1_UP_DLY */
21 msr = rdmsr(0x2000001a);
23 wrmsr(0x2000001a, msr);
24 //print_debug("sdram_enable step 2\n");
26 /* 3. release CKE mask to enable CKE */
27 msr = rdmsr(0x2000001d);
28 msr.lo &= ~(0x03 << 8);
29 wrmsr(0x2000201d, msr);
30 //print_debug("sdram_enable step 3\n");
32 /* 4. set and clear REF_TST 16 times, more shouldn't hurt
33 * why this is before EMRS and MRS ? */
34 for (i = 0; i < 19; i++) {
35 msr = rdmsr(0x20000018);
36 msr.lo |= (0x01 << 3);
37 wrmsr(0x20000018, msr);
38 msr.lo &= ~(0x01 << 3);
39 wrmsr(0x20000018, msr);
41 //print_debug("sdram_enable step 4\n");
43 /* 5. set refresh interval */
44 msr = rdmsr(0x20000018);
45 msr.lo &= ~(0xffff << 8);
46 msr.lo |= (0x34 << 8);
47 wrmsr(0x20000018, msr);
48 /* set refresh staggering to 4 SDRAM clocks */
49 msr = rdmsr(0x20000018);
50 msr.lo &= ~(0x03 << 6);
51 msr.lo |= (0x00 << 6);
52 wrmsr(0x20000018, msr);
53 //print_debug("sdram_enable step 5\n");
55 /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
56 msr = rdmsr(0x20000018);
57 msr.lo |= ((0x01 << 28) | 0x01);
58 wrmsr(0x20000018, msr);
59 msr.lo &= ~((0x01 << 28) | 0x01);
60 wrmsr(0x20000018, msr);
61 //print_debug("sdram_enable step 6\n");
63 /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
64 * it is documented in LX datasheet */
65 /* load Mode Register by set and clear PROG_DRAM */
66 msr = rdmsr(0x20000018);
67 msr.lo |= ((0x01 << 27) | 0x01);
68 wrmsr(0x20000018, msr);
69 msr.lo &= ~((0x01 << 27) | 0x01);
70 wrmsr(0x20000018, msr);
71 //print_debug("sdram_enable step 7\n");
73 /* 8. load Mode Register by set and clear PROG_DRAM */
74 msr = rdmsr(0x20000018);
76 wrmsr(0x20000018, msr);
78 wrmsr(0x20000018, msr);
79 //print_debug("sdram_enable step 8\n");
82 for (i = 0; i < 200; i++)
86 msr = rdmsr(0x2000001f);
88 /* the above setting is supposed to be good for "slow" ram. We have found that for
89 * some dram, at some clock rates, e.g. hynix at 366/244, this will actually
90 * cause errors. The fix is to just set it to 0x310. Tested on 3 boards
91 * with 3 different type of dram -- Hynix, PSC, infineon.
92 * I am leaving this comment here so that at some future time nobody is tempted
93 * to mess with this setting -- RGM, 9/2006
97 wrmsr(0x2000001f, msr);
99 /* set delay control */
100 msr = rdmsr(0x4c00000f);
103 wrmsr(0x4c00000f, msr);
105 /* The RAM dll needs a write to lock on so generate a few dummy writes */
106 /* Note: The descriptor needs to be enabled to point at memory */
107 volatile unsigned long *ptr;
108 for (i = 0; i < 5; i++) {
110 *ptr = (unsigned long)i;
113 print_info("RAM DLL lock\n");