1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx2def.h>
13 #include <cpu/x86/msr.h>
14 #include <cpu/x86/cache.h>
16 /* put this here for now, we are not sure where it belongs */
19 unsigned long desc_name;
20 unsigned short desc_type;
24 struct gliutable gliu0table[] = {
25 {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
26 {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
27 {.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
28 {.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
29 {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
30 {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
31 {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
32 {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
36 struct gliutable gliu1table[] = {
37 {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
38 {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/
39 {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},/* C0000-Fffff split to MC and PCI (sub decode)*/
40 {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
41 {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
42 {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
43 {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
44 {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/
45 {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
48 struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
55 struct msrinit ClockGatingDefault [] = {
56 {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
57 /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/
58 {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
59 {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
60 {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
61 {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
62 {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
63 {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
64 {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
65 {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on*/
66 {0xffffffff, {0xffffffff, 0xffffffff}},
69 struct msrinit ClockGatingAllOn[] = {
70 {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
71 {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
72 {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
73 {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}},
74 {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}},
75 {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
76 {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
77 {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
78 {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
79 {0xffffffff, {0xffffffff, 0xffffffff}},
83 struct msrinit ClockGatingPerformance[] = {
84 {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
85 {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
86 {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
87 {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
88 {0xffffffff, {0xffffffff, 0xffffffff}},
91 /* SET GeodeLink PRIORITY*/
93 struct msrinit GeodeLinkPriorityTable [] = {
94 {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority.*/
95 {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
96 {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
97 {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
98 {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
99 {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
100 {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
101 {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/
102 {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
105 /* do we have dmi or not? assume yes */
109 writeglmsr(struct gliutable *gl){
114 wrmsr(gl->desc_name, msr);
115 printk_debug("%s: write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
116 /* they do this, so we do this */
117 msr = rdmsr(gl->desc_name);
118 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
122 ShadowInit(struct gliutable *gl)
126 msr = rdmsr(gl->desc_name);
133 /* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
136 /* yes, this duplicates later code, but it seems that is how they want it done.
138 extern int sizeram(void);
140 SysmemInit(struct gliutable *gl)
143 int sizembytes, sizebytes;
145 sizembytes = sizeram();
146 printk_debug("%s: enable for %dm bytes\n", __FUNCTION__, sizembytes);
147 sizebytes = sizembytes << 20;
149 sizebytes -= SMM_SIZE*1024 +1;
152 sizebytes -= DMM_SIZE * 1024 + 1;
155 msr.hi = gl->hi | (sizebytes >> 24);
156 /* set up sizebytes to fit into msr.lo */
157 sizebytes <<= 8; /* what? well, we want bits 23:12 in bytes 31:20. */
158 sizebytes &= 0xfff00000;
161 wrmsr(gl->desc_name, msr);
162 msr = rdmsr(gl->desc_name);
163 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__,
164 gl->desc_name, msr.hi, msr.lo);
168 DMMGL0Init(struct gliutable *gl) {
170 int sizebytes = sizeram()<<20;
176 printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
178 sizebytes -= DMM_SIZE*1024;
179 offset = sizebytes - DMM_OFFSET;
180 printk_debug("%s: offset is 0x%x\n", __FUNCTION__, offset);
182 msr.hi = (gl->hi) | (offset << 8);
183 /* I don't think this is needed */
184 msr.hi &= 0xffffff00;
185 msr.hi |= (DMM_OFFSET >> 24);
186 msr.lo = DMM_OFFSET << 8;
187 msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
189 wrmsr(gl->desc_name, msr);
190 msr = rdmsr(gl->desc_name);
191 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
195 DMMGL1Init(struct gliutable *gl) {
201 printk_debug("%s:\n", __FUNCTION__ );
204 /* I don't think this is needed */
205 msr.hi &= 0xffffff00;
206 msr.hi |= (DMM_OFFSET >> 24);
207 msr.lo = DMM_OFFSET << 8;
208 /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
209 printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __FUNCTION__);
210 msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
212 wrmsr(gl->desc_name, msr);
213 msr = rdmsr(gl->desc_name);
214 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
217 SMMGL0Init(struct gliutable *gl) {
219 int sizebytes = sizeram()<<20;
222 sizebytes -= SMM_SIZE*1024;
225 sizebytes -= DMM_SIZE * 1024;
227 printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
229 offset = sizebytes - SMM_OFFSET;
230 printk_debug("%s: offset is 0x%x\n", __FUNCTION__, offset);
233 msr.hi = offset << 8;
234 msr.hi |= SMM_OFFSET>>24;
236 msr.lo = SMM_OFFSET << 8;
237 msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
239 wrmsr(gl->desc_name, msr);
240 msr = rdmsr(gl->desc_name);
241 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
244 SMMGL1Init(struct gliutable *gl) {
246 printk_debug("%s:\n", __FUNCTION__ );
249 /* I don't think this is needed */
250 msr.hi &= 0xffffff00;
251 msr.hi |= (SMM_OFFSET >> 24);
252 msr.lo = SMM_OFFSET << 8;
253 msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
255 wrmsr(gl->desc_name, msr);
256 msr = rdmsr(gl->desc_name);
257 printk_debug("%s: AFTER write msr 0x%x, val 0x%x:0x%x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
261 GLIUInit(struct gliutable *gl){
263 while (gl->desc_type != GL_END){
264 switch(gl->desc_type){
266 printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ", __FUNCTION__,
267 gl->desc_name, gl->desc_type, gl->hi, gl->hi);
268 printk_err("Must be %x, %x, %x, %x, %x, or %x\n", SC_SHADOW,R_SYSMEM,BMO_DMM,
269 BM_DMM, BMO_SMM,BM_SMM);
271 case SC_SHADOW: /* Check for a Shadow entry*/
275 case R_SYSMEM: /* check for a SYSMEM entry*/
279 case BMO_DMM: /* check for a DMM entry*/
283 case BM_DMM : /* check for a DMM entry*/
287 case BMO_SMM : /* check for a SMM entry*/
291 case BM_SMM : /* check for a SMM entry*/
299 /* ***************************************************************************/
303 /* * Set up GLPCI settings for reads/write into memory*/
305 /* * R1: 1MB - Top of System Memory*/
306 /* * R2: SMM Memory*/
307 /* * R3: Framebuffer? - not set up yet*/
314 /* ***************************************************************************/
315 static void GLPCIInit(void){
316 struct gliutable *gl = 0;
322 /* R0 - GLPCI settings for Conventional Memory space.*/
324 msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT /* 640*/;
326 msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
331 /* R1 - GLPCI settings for SysMem space.*/
333 /* Get systop from GLIU0 SYSTOP Descriptor*/
334 for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
335 if (gliu0table[i].desc_type == R_SYSMEM) {
341 msrnum = gl->desc_name;
344 /* 20 bit address The bottom 12 bits go into bits 20-31 in eax. The top 8 bits go into 0-7 of edx.*/
345 val = msr.hi & 0xff; /* EAX[31:20] = low 12 bits and EAX[7:0] upper 8 bits*/
346 val <<= 12; /* EAX[31:20] = junk EAX[19:0] = 20 bit address*/
348 val <<= GLPCI_RC_UPPER_TOP_SHIFT;
349 msr.hi = val /* Top Set*/;
350 msr.lo = (0x100000 >> 12) << GLPCI_RC_LOWER_BASE_SHIFT /* 1MB >> =20bit address then shift into register*/;
351 msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
357 /* R2 - GLPCI settings for SMM space.*/
359 msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
360 msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
361 msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
365 /* this is done elsewhere already, but it does no harm to do it more than once */
366 /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
367 msr.lo = 0x021212121 /* cache disabled and write serialized*/;
368 msr.hi = 0x021212121 /* cache disabled and write serialized*/;
370 msrnum = CPU_RCONF_A0_BF;
373 msrnum = CPU_RCONF_C0_DF;
376 msrnum = CPU_RCONF_E0_FF;
379 /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
380 msrnum = GLPCI_A0_BF;
385 msrnum = GLPCI_C0_DF;
390 msrnum = GLPCI_E0_FF;
396 msrnum = CPU_DM_CONFIG0;
398 msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
399 msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode.*/
402 /* we are ignoring the 5530 case for now, and perhaps forever. */
409 msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
410 msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
417 msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/
418 msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
420 msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
421 msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
423 msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
424 msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
426 msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
427 msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
429 msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
430 msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
432 msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
433 msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
435 msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
436 msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
438 msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
439 msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
443 /* Set GLPCI Latency Timer.*/
446 msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone.*/
450 msrnum = GLPCI_SPARE;
453 msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
460 /* ***************************************************************************/
462 /* * ClockGatingInit*/
464 /* * Enable Clock Gating.*/
470 /* ***************************************************************************/
472 ClockGatingInit (void){
474 struct msrinit *gating = ClockGatingDefault;
478 mov cx, TOKEN_CLK_GATE
479 NOSTACK bx, GetNVRAMValueBX
480 cmp al, TVALUE_CG_OFF
483 cmp al, TVALUE_CG_DEFAULT
486 lea si, ClockGatingDefault
490 lea si, ClockGatingAllOn
494 lea si, ClockGatingPerformance
497 for(i = 0; gating->msrnum != 0xffffffff; i++) {
498 msr = rdmsr(gating->msrnum);
499 printk_debug("%s: MSR 0x%x is 0x%x:0x%x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo);
500 msr.hi |= gating->msr.hi;
501 msr.lo |= gating->msr.lo;
502 printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
503 gating->msrnum, msr.hi, msr.lo);
504 wrmsr(gating->msrnum, msr);
511 GeodeLinkPriority(void){
513 struct msrinit *prio = GeodeLinkPriorityTable;
516 for(i = 0; prio->msrnum != 0xffffffff; i++) {
517 msr = rdmsr(prio->msrnum);
518 printk_debug("%s: MSR 0x%x is 0x%x:0x%x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo);
519 msr.hi |= prio->msr.hi;
521 msr.lo |= prio->msr.lo;
522 printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
523 prio->msrnum, msr.hi, msr.lo);
524 wrmsr(prio->msrnum, msr);
529 /* ***************************************************************************/
531 /* * northBridgeInit*/
533 /* * Core Logic initialization: Host bridge*/
539 /* ***************************************************************************/
542 northbridgeinit(void)
545 printk_debug("Enter %s\n", __FUNCTION__);
547 for(i = 0; gliutables[i]; i++)
548 GLIUInit(gliutables[i]);
553 /* Now that the descriptor to memory is set up.*/
554 /* The memory controller needs one read to synch it's lines before it can be used.*/
560 /* CPUBugsFix -- called elsewhere */
561 printk_debug("Exit %s\n", __FUNCTION__);