1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx2def.h>
13 #include <cpu/x86/msr.h>
14 #include <cpu/x86/cache.h>
15 #include "southbridge/amd/cs5536/cs5536.h"
17 /* the structs in this file only set msr.lo. But ... that may not always be true */
24 /* Master Configuration Register for Bus Masters. */
25 static struct msrinit SB_MASTER_CONF_TABLE[] = {
26 { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */
27 { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} },
28 { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} },
29 { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} },
30 { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} },
31 /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
32 /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
33 /* GLIU_SB_GLD_MSR_CONF, 0x0*/
37 /* 5535_A3 Clock Gating*/
38 static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
39 { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
40 { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
41 { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} },
42 { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
43 { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} },
44 { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} },
45 { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
46 { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
47 { 0, {.hi=0, .lo=0x000000000} }
50 /* 5536 Clock Gating*/
51 static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
53 { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} },
54 { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
55 { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} },
56 { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
57 { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
58 { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} },
59 { 0, {.hi=0, .lo=0x000000000} }
65 unsigned long regdata;
69 static struct acpiinit acpi_init_table[] = {
70 {ACPI_BASE+0x00, 0x01000000, 4},
71 {ACPI_BASE+0x08, 0, 4},
72 {ACPI_BASE+0x0C, 0, 4},
73 {ACPI_BASE+0x1C, 0, 4},
74 {ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
75 {ACPI_BASE+0x00, 0x0000FFFF, 4},
77 {PM_SCLK, 0x000000E00, 4},
78 {PM_SED, 0x000004601, 4},
79 {PM_SIDD, 0x000008C02, 4},
80 {PM_WKD, 0x0000000A0, 4},
81 {PM_WKXD, 0x0000000A0, 4},
86 /* return 1 if we are a 5536-based system */
87 static int is_5536(void)
90 msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
92 printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
93 return ((msr.lo&0xf) == 5);
97 /*****************************************************************************
101 * Program ACPI LBAR and initialize ACPI registers.
103 *****************************************************************************/
104 static void pmChipsetInit(void)
106 unsigned long val = 0;
109 port = (PMLogic_BASE + 0x010);
110 val = 0x0E00 ; /* 1ms*/
114 /* Make sure bits[3:0]=0000b to clear the*/
116 port = (PMLogic_BASE + 0x034);
117 val = 0x0A0 ; /* 5ms*/
121 port = (PMLogic_BASE + 0x030);
125 port = (PMLogic_BASE + 0x014);
126 val = 0x04601 ; /* 5ms*/
130 port = (PMLogic_BASE + 0x020);
131 val = 0x08C02 ; /* 10ms*/
134 /* GPIO24 OUT_AUX1 function is the external signal for 5535's
135 * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or
136 * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem
137 * and Vstandby. This means GX2 will be fully de-powered if this
138 * control de-asserts in S3/S5.
141 /* GPIO24 is setup in preChipsetInit for two reasons
142 * 1. GPIO24 at reset defaults to disabled, since this signal is
143 * vsb_work_aux on Hawk it controls the FET's for all voltage
144 * rails except Vstanby & Vmem. BIOS needs to enable GPIO24 as
145 * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535.
146 * 2. Non-PM builds will require GPIO24 enabled for instant-off power
150 /* GPIO11 OUT_AUX1 function is the external signal for 5535's
151 * slp_clk_n which is asserted when 5535 enters Sleep(S1) state.
152 * On Hawk, GPIO11 is connected to control input of external clock
153 * generator for 14MHz, PCI, USB & LPC clocks.
154 * Programming of GPIO11 will be done by VSA PM code. During VSA
155 * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks
156 * should be On or Off. This is based on a Setup item. We do not want
157 * to leave GPIO11 enabled because of a Hawk board problem. With
158 * GPIO11 enabled in S3, something is back-driving GPIO11 causing it
159 * to float to 1.6-1.7V.
164 struct FLASH_DEVICE {
165 unsigned char fType; /* Flash type: NOR or NAND */
166 unsigned char fInterface; /* Flash interface: I/O or Memory */
167 unsigned long fMask; /* Flash size/mask */
170 static struct FLASH_DEVICE FlashInitTable[] = {
171 { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
172 { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
173 { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
174 { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
177 #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
179 static uint32_t FlashPort[] = {
186 /***************************************************************************
190 * Flash LBARs need to be setup before VSA init so the PCI BARs have
191 * correct size info. Call this routine only if flash needs to be
192 * configured (don't call it if you want IDE).
194 **************************************************************************/
195 static void ChipsetFlashSetup(void)
201 printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
202 for (i = 0; i < FlashInitTableLen; i++) {
203 if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
204 printk(BIOS_DEBUG, "Enable CS%d\n", i);
205 /* we need to configure the memory/IO mask */
206 msr = rdmsr(FlashPort[i]);
207 msr.hi = 0; /* start with the "enabled" bit clear */
208 if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
209 msr.hi |= 0x00000002;
211 msr.hi &= ~0x00000002;
212 if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
213 msr.hi |= 0x00000004;
215 msr.hi &= ~0x00000004;
216 msr.hi |= FlashInitTable[i].fMask;
217 printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
218 wrmsr(FlashPort[i], msr);
220 /* now write-enable the device */
221 msr = rdmsr(MDD_NORF_CNTRL);
223 printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
224 wrmsr(MDD_NORF_CNTRL, msr);
226 /* update the number enabled */
231 /* enable the flash */
232 if (0 != numEnabled) {
233 msr = rdmsr(MDD_PIN_OPT);
234 msr.lo &= ~1; /* PIN_OPT_IDE */
235 printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
236 wrmsr(MDD_PIN_OPT, msr);
239 printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
244 /****************************************************************************
246 * ChipsetGeodeLinkInit
248 * Handle chipset specific GeodeLink settings here.
249 * Called from GeodeLink init code.
251 ****************************************************************************/
253 ChipsetGeodeLinkInit(void)
256 unsigned long msrnum;
257 unsigned long totalmem;
262 /* SWASIF for A1 DMA */
263 /* Set all memory to "just above systop" PCI so DMA will work */
266 msrnum = MSR_SB_GLCP + 0x17;
268 if ((msr.lo&0xff) == 0x11)
271 totalmem = sizeram() << 20 - 1;
273 totalmem = ~totalmem;
276 msr.hi = 0x20000000; /* Port 1 (PCI) */
277 msrnum = MSR_SB_GLIU + 0x20;
282 gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
287 unsigned long msrnum;
289 outb( P80_CHIPSET_INIT, 0x80);
290 ChipsetGeodeLinkInit();
292 printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535");
295 /* we hope NEVER to be in coreboot when S3 resumes
296 if (! IsS3Resume()) */
298 struct acpiinit *aci = acpi_init_table;
300 if (aci->iolen == 2) {
301 outw(aci->regdata, aci->ioreg);
304 outl(aci->regdata, aci->ioreg);
314 /* Setup USB. Need more details. #118.18 */
315 msrnum = MSR_SB_USB1 + 8;
319 msrnum = MSR_SB_USB2 + 8;
324 outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE);
325 outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
327 /* Allow IO read and writes during a ATA DMA operation. */
328 /* This could be done in the HD rom but do it here for easier debugging. */
330 msrnum = ATA_SB_GLD_MSR_ERR;
335 /* Enable Post Primary IDE. */
336 msrnum = GLPCI_SB_CTRL;
338 msr.lo |= GLPCI_CRTL_PPIDE_SET;
341 /* Set up Master Configuration Register */
342 /* If 5536, use same master config settings as 5535, except for OHCI MSRs */
348 csi = &SB_MASTER_CONF_TABLE[i];
349 for(; csi->msrnum; csi++){
350 msr.lo = csi->msr.lo;
351 msr.hi = csi->msr.hi;
352 wrmsr(csi->msrnum, msr); // MSR - see table above
356 printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n",
357 nb->setupflash ? "" : "NOT ");
362 /* Set up Hardware Clock Gating */
364 /* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
367 csi = CS5536_CLOCK_GATING_TABLE;
369 csi = CS5535_CLOCK_GATING_TABLE;
371 for(; csi->msrnum; csi++){
372 msr.lo = csi->msr.lo;
373 msr.hi = csi->msr.hi;
374 wrmsr(csi->msrnum, msr); // MSR - see table above