src/northbridge/amd/gx1/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12 #include <cpu/amd/gx1def.h>
  13 #include <cpu/x86/cache.h>
  14 #include <cpu/cpu.h>
  15
  16 #define NORTHBRIDGE_FILE "northbridge.c"
  17 /*
  18 */
  19
  20 static void optimize_xbus(device_t dev)
  21 {
  22         /* Optimise X-Bus performance */
  23         pci_write_config8(dev, 0x40, 0x1e);
  24         pci_write_config8(dev, 0x41, 0x52);
  25         pci_write_config8(dev, 0x43, 0xc1);
  26         pci_write_config8(dev, 0x44, 0x00);
  27 }
  28
  29 /**
  30  * Enables memory from 0xC0000 up to 0xFFFFF.
  31  * So this region is read/write and cache able
  32  *
  33  * FIXME: What about PCI master access into
  34  *        this region?
  35  **/
  36
  37 static void enable_shadow(device_t dev)
  38 {
  39        write32(GX_BASE+BC_XMAP_2, 0x77777777);
  40        write32(GX_BASE+BC_XMAP_3, 0x77777777);
  41 }
  42
  43 static void northbridge_init(device_t dev)
  44 {
  45         printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
  46
  47         optimize_xbus(dev);
  48         enable_shadow(dev);
  49         printk(BIOS_SPEW, "Calling enable_cache()\n");
  50         enable_cache();
  51 }
  52
  53
  54 static struct device_operations northbridge_operations = {
  55         .read_resources   = pci_dev_read_resources,
  56         .set_resources    = pci_dev_set_resources,
  57         .enable_resources = pci_dev_enable_resources,
  58         .init             = northbridge_init,
  59         .enable           = 0,
  60         .ops_pci          = 0,
  61 };
  62
  63 static const struct pci_driver northbridge_driver __pci_driver = {
  64         .ops = &northbridge_operations,
  65         .vendor = PCI_VENDOR_ID_CYRIX,
  66         .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
  67 };
  68
  69 #if CONFIG_WRITE_HIGH_TABLES==1
  70 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  71 extern uint64_t high_tables_base, high_tables_size;
  72 #endif
  73
  74 static void pci_domain_set_resources(device_t dev)
  75 {
  76         device_t mc_dev;
  77         uint32_t pci_tolm;
  78
  79         pci_tolm = find_pci_tolm(dev->link_list);
  80         mc_dev = dev->link_list->children;
  81         if (mc_dev) {
  82                 unsigned int tomk, tolmk;
  83                 unsigned int ramreg = 0;
  84                 int i, idx;
  85                 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
  86                 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
  87
  88                 for(i=0; i<0x20; i+= 0x10) {
  89                         unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
  90                         unsigned int mem_config = *mcreg;
  91
  92                         if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
  93                                 continue;
  94                         ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
  95                 }
  96
  97                 tomk = ramreg << 10;
  98
  99                 /* Sort out the framebuffer size */
 100                 tomk -= CONFIG_VIDEO_MB * 1024;
 101                 *bcdramtop = ((tomk << 10) - 1);
 102                 *mcgbaseadd = (tomk >> 9);
 103
 104                 printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
 105                 printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 106
 107                 printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 108
 109                 /* Compute the top of Low memory */
 110                 tolmk = pci_tolm >> 10;
 111                 if (tolmk >= tomk) {
 112                         /* The PCI hole does does not overlap the memory.
 113                          */
 114                         tolmk = tomk;
 115                 }
 116
 117 #if CONFIG_WRITE_HIGH_TABLES==1
 118                 /* Leave some space for ACPI, PIRQ and MP tables */
 119                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 120                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 121 #endif
 122
 123                 /* Report the memory regions */
 124                 idx = 10;
 125                 ram_resource(dev, idx++, 0, tolmk);
 126         }
 127         assign_resources(dev->link_list);
 128 }
 129
 130 static struct device_operations pci_domain_ops = {
 131         .read_resources   = pci_domain_read_resources,
 132         .set_resources    = pci_domain_set_resources,
 133         .enable_resources = NULL,
 134         .init             = NULL,
 135         .scan_bus         = pci_domain_scan_bus,
 136 };
 137
 138 static void cpu_bus_init(device_t dev)
 139 {
 140         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 141         initialize_cpus(dev->link_list);
 142 }
 143
 144 static void cpu_bus_noop(device_t dev)
 145 {
 146 }
 147
 148 static struct device_operations cpu_bus_ops = {
 149         .read_resources   = cpu_bus_noop,
 150         .set_resources    = cpu_bus_noop,
 151         .enable_resources = cpu_bus_noop,
 152         .init             = cpu_bus_init,
 153         .scan_bus         = 0,
 154 };
 155
 156 static void enable_dev(struct device *dev)
 157 {
 158         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 159         /* Set the operations if it is a special bus type */
 160         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 161                 printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
 162                 dev->ops = &pci_domain_ops;
 163                 pci_set_method(dev);
 164         }
 165         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 166                 printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
 167                 dev->ops = &cpu_bus_ops;
 168         } else {
 169                 printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 170         }
 171 }
 172
 173 struct chip_operations northbridge_amd_gx1_ops = {
 174         CHIP_NAME("AMD GX1 Northbridge")
 175         .enable_dev = enable_dev,
 176 };