src/northbridge/amd/gx1/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12 #include <cpu/amd/gx1def.h>
  13 #include <cpu/x86/cache.h>
  14 #include <cpu/cpu.h>
  15
  16 #define NORTHBRIDGE_FILE "northbridge.c"
  17 /*
  18 */
  19
  20 static void optimize_xbus(device_t dev)
  21 {
  22         /* Optimise X-Bus performance */
  23         pci_write_config8(dev, 0x40, 0x1e);
  24         pci_write_config8(dev, 0x41, 0x52);
  25         pci_write_config8(dev, 0x43, 0xc1);
  26         pci_write_config8(dev, 0x44, 0x00);
  27 }
  28
  29 /**
  30  * Enables memory from 0xC0000 up to 0xFFFFF.
  31  * So this region is read/write and cache able
  32  *
  33  * FIXME: What about PCI master access into
  34  *        this region?
  35  **/
  36
  37 static void enable_shadow(device_t dev)
  38 {
  39        write32(GX_BASE+BC_XMAP_2, 0x77777777);
  40        write32(GX_BASE+BC_XMAP_3, 0x77777777);
  41 }
  42
  43 static void northbridge_init(device_t dev)
  44 {
  45         printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
  46
  47         optimize_xbus(dev);
  48         enable_shadow(dev);
  49         printk(BIOS_SPEW, "Calling enable_cache()\n");
  50         enable_cache();
  51 }
  52
  53
  54 static struct device_operations northbridge_operations = {
  55         .read_resources   = pci_dev_read_resources,
  56         .set_resources    = pci_dev_set_resources,
  57         .enable_resources = pci_dev_enable_resources,
  58         .init             = northbridge_init,
  59         .enable           = 0,
  60         .ops_pci          = 0,
  61 };
  62
  63 static const struct pci_driver northbridge_driver __pci_driver = {
  64         .ops = &northbridge_operations,
  65         .vendor = PCI_VENDOR_ID_CYRIX,
  66         .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
  67 };
  68
  69 static void ram_resource(device_t dev, unsigned long index,
  70         unsigned long basek, unsigned long sizek)
  71 {
  72         struct resource *resource;
  73
  74         if (!sizek) {
  75                 return;
  76         }
  77         resource = new_resource(dev, index);
  78         resource->base  = ((resource_t)basek) << 10;
  79         resource->size  = ((resource_t)sizek) << 10;
  80         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  81                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  82 }
  83
  84 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  85 {
  86         struct resource **best_p = gp;
  87         struct resource *best;
  88         best = *best_p;
  89         if (!best || (best->base > new->base)) {
  90                 best = new;
  91         }
  92         *best_p = best;
  93 }
  94
  95 static uint32_t find_pci_tolm(struct bus *bus)
  96 {
  97         struct resource *min;
  98         uint32_t tolm;
  99         min = 0;
 100         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 101         tolm = 0xffffffffUL;
 102         if (min && tolm > min->base) {
 103                 tolm = min->base;
 104         }
 105         return tolm;
 106 }
 107
 108 #if CONFIG_WRITE_HIGH_TABLES==1
 109 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
 110 extern uint64_t high_tables_base, high_tables_size;
 111 #endif
 112
 113 static void pci_domain_set_resources(device_t dev)
 114 {
 115         device_t mc_dev;
 116         uint32_t pci_tolm;
 117
 118         pci_tolm = find_pci_tolm(dev->link_list);
 119         mc_dev = dev->link_list->children;
 120         if (mc_dev) {
 121                 unsigned int tomk, tolmk;
 122                 unsigned int ramreg = 0;
 123                 int i, idx;
 124                 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
 125                 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
 126
 127                 for(i=0; i<0x20; i+= 0x10) {
 128                         unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
 129                         unsigned int mem_config = *mcreg;
 130
 131                         if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
 132                                 continue;
 133                         ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
 134                 }
 135
 136                 tomk = ramreg << 10;
 137
 138                 /* Sort out the framebuffer size */
 139                 tomk -= CONFIG_VIDEO_MB * 1024;
 140                 *bcdramtop = ((tomk << 10) - 1);
 141                 *mcgbaseadd = (tomk >> 9);
 142
 143                 printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
 144                 printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 145
 146                 printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 147
 148                 /* Compute the top of Low memory */
 149                 tolmk = pci_tolm >> 10;
 150                 if (tolmk >= tomk) {
 151                         /* The PCI hole does does not overlap the memory.
 152                          */
 153                         tolmk = tomk;
 154                 }
 155
 156 #if CONFIG_WRITE_HIGH_TABLES==1
 157                 /* Leave some space for ACPI, PIRQ and MP tables */
 158                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 159                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 160 #endif
 161
 162                 /* Report the memory regions */
 163                 idx = 10;
 164                 ram_resource(dev, idx++, 0, tolmk);
 165         }
 166         assign_resources(dev->link_list);
 167 }
 168
 169 static struct device_operations pci_domain_ops = {
 170         .read_resources   = pci_domain_read_resources,
 171         .set_resources    = pci_domain_set_resources,
 172         .enable_resources = NULL,
 173         .init             = NULL,
 174         .scan_bus         = pci_domain_scan_bus,
 175 };
 176
 177 static void cpu_bus_init(device_t dev)
 178 {
 179         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 180         initialize_cpus(dev->link_list);
 181 }
 182
 183 static void cpu_bus_noop(device_t dev)
 184 {
 185 }
 186
 187 static struct device_operations cpu_bus_ops = {
 188         .read_resources   = cpu_bus_noop,
 189         .set_resources    = cpu_bus_noop,
 190         .enable_resources = cpu_bus_noop,
 191         .init             = cpu_bus_init,
 192         .scan_bus         = 0,
 193 };
 194
 195 static void enable_dev(struct device *dev)
 196 {
 197         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 198         /* Set the operations if it is a special bus type */
 199         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 200                 printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
 201                 dev->ops = &pci_domain_ops;
 202                 pci_set_method(dev);
 203         }
 204         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 205                 printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
 206                 dev->ops = &cpu_bus_ops;
 207         } else {
 208                 printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 209         }
 210 }
 211
 212 struct chip_operations northbridge_amd_gx1_ops = {
 213         CHIP_NAME("AMD GX1 Northbridge")
 214         .enable_dev = enable_dev,
 215 };