src/northbridge/amd/amdmct/wrappers/mcti_d.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* Call-backs */
  21 #include <delay.h>
  22 static u16 mctGet_NVbits(u8 index)
  23 {
  24         u16 val = 0;
  25
  26         switch (index) {
  27         case NV_PACK_TYPE:
  28 #if CONFIG_CPU_SOCKET_TYPE == 0x10      /* Socket F */
  29                 val = 0;
  30 #elif CONFIG_CPU_SOCKET_TYPE == 0x11    /* AM3 */
  31                 val = 1;
  32 #elif CONFIG_CPU_SOCKET_TYPE == 0x13    /* ASB2 */
  33                 val = 4;
  34 //#elif SYSTEM_TYPE == MOBILE
  35 //              val = 2;
  36 #endif
  37                 break;
  38         case NV_MAX_NODES:
  39                 val = MAX_NODES_SUPPORTED;
  40                 break;
  41         case NV_MAX_DIMMS:
  42                 //val = MAX_DIMMS_SUPPORTED;
  43                 val = 8;
  44                 break;
  45         case NV_MAX_MEMCLK:
  46                 /* Maximum platform supported memclk */
  47                 //val =  200;   /* 200MHz(DDR400) */
  48                 //val =  266;   /* 266MHz(DDR533) */
  49                 //val =  333;   /* 333MHz(DDR667) */
  50                 val =  400;     /* 400MHz(DDR800) */
  51                 break;
  52         case NV_ECC_CAP:
  53 #if SYSTEM_TYPE == SERVER
  54                 val = 1;        /* memory bus ECC capable */
  55 #else
  56                 val = 0;        /* memory bus ECC not capable */
  57 #endif
  58                 break;
  59         case NV_4RANKType:
  60                 /* Quad Rank DIMM slot type */
  61                 val = 0;        /* normal */
  62                 //val = 1;      /* R4 (registered DIMMs in AMD server configuration) */
  63                 //val = 2;      /* S4 (Unbuffered SO-DIMMS) */
  64                 break;
  65         case NV_BYPMAX:
  66 #if   (UMA_SUPPORT == 0)
  67                 val = 4;
  68 #elif  (UMA_SUPPORT == 1)
  69                 val = 7;
  70 #endif
  71                 break;
  72         case NV_RDWRQBYP:
  73 #if  (UMA_SUPPORT == 0)
  74                 val = 2;
  75 #elif (UMA_SUPPORT == 1)
  76                 val = 3;
  77 #endif
  78                 break;
  79         case NV_MCTUSRTMGMODE:
  80                 val = 0;        /* Automatic (recommended) */
  81                 //val = 1;      /* Limited */
  82                 //val = 2;      /* Manual */
  83                 break;
  84         case NV_MemCkVal:
  85                 //val = 0;      /* 200MHz */
  86                 //val = 1;      /* 266MHz */
  87                 val = 2;        /* 333MHz */
  88                 break;
  89         case NV_BankIntlv:
  90                 /* Bank (chip select) interleaving */
  91                 //val = 0;      /* disabled */
  92                 val = 1;        /* enabled (recommended) */
  93                 break;
  94         case NV_MemHole:
  95                 //val = 0;      /* Disabled */
  96                 val = 1;        /* Enabled (recommended) */
  97                 break;
  98         case NV_AllMemClks:
  99                 val = 0;        /* Normal (only to slots that have enabled DIMMs) */
 100                 //val = 1;      /* Enable all memclocks */
 101                 break;
 102         case NV_SPDCHK_RESTRT:
 103                 val = 0;        /* Exit current node initialization if any DIMM has SPD checksum error */
 104                 //val = 1;      /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
 105                 break;
 106         case NV_DQSTrainCTL:
 107                 //val = 0;      /*Skip dqs training */
 108                 val = 1;        /* Perform dqs training */
 109                 break;
 110         case NV_NodeIntlv:
 111                 val = 0;        /* Disabled (recommended) */
 112                 //val = 1;      /* Enable */
 113                 break;
 114         case NV_BurstLen32:
 115 #if (UMA_SUPPORT == 0)
 116                 val = 0;        /* 64 byte mode */
 117 #elif (UMA_SUPPORT == 1)
 118                 val = 1;        /* 32 byte mode */
 119 #endif
 120                 break;
 121         case NV_CKE_PDEN:
 122                 //val = 0;      /* Disable */
 123                 val = 1;        /* Enable */
 124                 break;
 125         case NV_CKE_CTL:
 126                 val = 0;        /* per channel control */
 127                 //val = 1;      /* per chip select control */
 128                 break;
 129         case NV_CLKHZAltVidC3:
 130                 val = 0;        /* disable */
 131                 //val = 1;      /* enable */
 132                 break;
 133         case NV_BottomIO:
 134                 val = 0xE0;     /* address bits [31:24] */
 135                 break;
 136         case NV_BottomUMA:
 137 #if (UMA_SUPPORT == 0)
 138                 val = 0xE0;     /* address bits [31:24] */
 139 #elif (UMA_SUPPORT == 1)
 140                 val = 0xB0;     /* address bits [31:24] */
 141 #endif
 142                 break;
 143         case NV_ECC:
 144 #if (SYSTEM_TYPE == SERVER)
 145                 val = 1;        /* Enable */
 146 #else
 147                 val = 0;        /* Disable */
 148 #endif
 149                 break;
 150         case NV_NBECC:
 151 #if (SYSTEM_TYPE == SERVER)
 152                 val = 1;        /* Enable */
 153 #else
 154                 val = 0;        /* Disable */
 155 #endif
 156                 break;
 157         case NV_ChipKill:
 158 #if (SYSTEM_TYPE == SERVER)
 159                 val = 1;        /* Enable */
 160 #else
 161                 val = 0;        /* Disable */
 162 #endif
 163                 break;
 164         case NV_ECCRedir:
 165                 val = 0;        /* Disable */
 166                 //val = 1;      /* Enable */
 167                 break;
 168         case NV_DramBKScrub:
 169                 val = 0x00;     /* Disabled */
 170                 //val = 0x01;   /* 40ns */
 171                 //val = 0x02;   /* 80ns */
 172                 //val = 0x03;   /* 160ns */
 173                 //val = 0x04;   /* 320ns */
 174                 //val = 0x05;   /* 640ns */
 175                 //val = 0x06;   /* 1.28us */
 176                 //val = 0x07;   /* 2.56us */
 177                 //val = 0x08;   /* 5.12us */
 178                 //val = 0x09;   /* 10.2us */
 179                 //val = 0x0a;   /* 20.5us */
 180                 //val = 0x0b;   /* 41us */
 181                 //val = 0x0c;   /* 81.9us */
 182                 //val = 0x0d;   /* 163.8us */
 183                 //val = 0x0e;   /* 327.7us */
 184                 //val = 0x0f;   /* 655.4us */
 185                 //val = 0x10;   /* 1.31ms */
 186                 //val = 0x11;   /* 2.62ms */
 187                 //val = 0x12;   /* 5.24ms */
 188                 //val = 0x13;   /* 10.49ms */
 189                 //val = 0x14;   /* 20.97sms */
 190                 //val = 0x15;   /* 42ms */
 191                 //val = 0x16;   /* 84ms */
 192                 break;
 193         case NV_L2BKScrub:
 194                 val = 0;        /* Disabled - See L2Scrub in BKDG */
 195                 break;
 196         case NV_DCBKScrub:
 197                 val = 0;        /* Disabled - See DcacheScrub in BKDG */
 198                 break;
 199         case NV_CS_SpareCTL:
 200                 val = 0;        /* Disabled */
 201                 //val = 1;      /* Enabled */
 202                 break;
 203         case NV_SyncOnUnEccEn:
 204                 val = 0;        /* Disabled */
 205                 //val = 1;      /* Enabled */
 206                 break;
 207         case NV_Unganged:
 208                 /* channel interleave is better performance than ganged mode at this time */
 209                 val = 1;                /* Enabled */
 210                 //val = 0;      /* Disabled */
 211                 break;
 212         case NV_ChannelIntlv:
 213                 val = 5;        /* Not currently checked in mctchi_d.c */
 214         /* Bit 0 =     0 - Disable
 215          *             1 - Enable
 216          * Bits[2:1] = 00b - Address bits 6
 217          *             01b - Address bits 1
 218          *             10b - Hash*, XOR of address bits [20:16, 6]
 219          *             11b - Hash*, XOR of address bits [20:16, 9]
 220          */
 221                 break;
 222         }
 223
 224         return val;
 225 }
 226
 227
 228 static void mctHookAfterDIMMpre(void)
 229 {
 230 }
 231
 232
 233 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 234 {
 235         pDCTstat->PresetmaxFreq = 400;
 236 }
 237
 238 #ifdef UNUSED_CODE
 239 static void mctAdjustAutoCycTmg(void)
 240 {
 241 }
 242 #endif
 243
 244
 245 static void mctAdjustAutoCycTmg_D(void)
 246 {
 247 }
 248
 249
 250 static void mctHookAfterAutoCycTmg(void)
 251 {
 252 }
 253
 254
 255 static void mctGetCS_ExcludeMap(void)
 256 {
 257 }
 258
 259
 260 static void mctHookAfterAutoCfg(void)
 261 {
 262 }
 263
 264
 265 static void mctHookAfterPSCfg(void)
 266 {
 267 }
 268
 269
 270 static void mctHookAfterHTMap(void)
 271 {
 272 }
 273
 274
 275 static void mctHookAfterCPU(void)
 276 {
 277 }
 278
 279
 280 static void mctSaveDQSSigTmg_D(void)
 281 {
 282 }
 283
 284
 285 static void mctGetDQSSigTmg_D(void)
 286 {
 287 }
 288
 289
 290 static void mctHookBeforeECC(void)
 291 {
 292 }
 293
 294
 295 static void mctHookAfterECC(void)
 296 {
 297 }
 298
 299 #ifdef UNUSED_CODE
 300 static void mctInitMemGPIOs_A(void)
 301 {
 302 }
 303 #endif
 304
 305
 306 static void mctInitMemGPIOs_A_D(void)
 307 {
 308 }
 309
 310
 311 static void mctNodeIDDebugPort_D(void)
 312 {
 313 }
 314
 315
 316 #ifdef UNUSED_CODE
 317 static void mctWarmReset(void)
 318 {
 319 }
 320 #endif
 321
 322
 323 static void mctWarmReset_D(void)
 324 {
 325 }
 326
 327
 328 static void mctHookBeforeDramInit(void)
 329 {
 330 }
 331
 332
 333 static void mctHookAfterDramInit(void)
 334 {
 335 }
 336
 337 static void coreDelay (void);
 338
 339
 340 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 341 /* Erratum 350 */
 342 static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 343 {
 344         u8 u8Channel;
 345         u8 u8Receiver;
 346         u32 u32Addr;
 347         u8 u8Valid;
 348         u32 u32DctDev;
 349
 350         // 1. dummy read for each installed DIMM */
 351         for (u8Channel = 0; u8Channel < 2; u8Channel++) {
 352                 // This will be 0 for vaild DIMMS, eles 8
 353                 u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel);
 354
 355                 for (; u8Receiver < 8; u8Receiver += 2) {
 356                         u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
 357
 358                         if(!u8Valid) {  /* Address not supported on current CS */
 359                                 print_t("vErrata350: Address not supported on current CS\n");
 360                                 continue;
 361                         }
 362                         print_t("vErrata350: dummy read \n");
 363                         read32_fs(u32Addr);
 364                 }
 365         }
 366
 367         print_t("vErrata350: step 2a\n");
 368
 369         /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
 370         u32DctDev = pDCTstat->dev_dct;
 371         Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
 372         /*                                                ^--- value
 373                                                 ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
 374                                          ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
 375
 376         if(!pDCTstat->GangedMode) {
 377                 print_t("vErrata350: step 2b\n");
 378                 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
 379                 /*                                                ^--- value
 380                                                         ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
 381                                                 ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
 382         }
 383
 384         print_t("vErrata350: step 3\n");
 385         /* 3. Wait at least 300 nanoseconds. */
 386         coreDelay();
 387
 388         print_t("vErrata350: step 4\n");
 389         /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
 390         Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
 391
 392         if(!pDCTstat->GangedMode) {
 393                 print_t("vErrata350: step 4b\n");
 394                 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
 395         }
 396
 397         print_t("vErrata350: step 5\n");
 398         /* 5. Wait at least 2 microseconds. */
 399         coreDelay();
 400
 401 }
 402 #endif
 403
 404
 405 static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 406 {
 407 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 408         if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
 409                 vErrata350(pMCTstat, pDCTstatA);
 410         }
 411 #endif
 412 }
 413
 414 static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
 415 {
 416         if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
 417                 if (pDCTstatA->Status & (1 << SB_Registered)) {
 418                         val ++;
 419                 }
 420         }
 421         return val;
 422 }
 423
 424 static void mctHookAfterAnyTraining(void)
 425 {
 426 }
 427
 428 static u32 mctGetLogicalCPUID_D(u8 node)
 429 {
 430         return mctGetLogicalCPUID(node);
 431 }
 432
 433 static u8 mctSetNodeBoundary_D(void)
 434 {
 435         return 0;
 436 }
 437