Initial AMD Barcelona support for rev Bx.
[coreboot.git] / src / northbridge / amd / amdmct / mct / mctsrc2p.c
1 /*
2  * This file is part of the LinuxBIOS project.
3  *
4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19  */
20
21
22 u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass)
23 {
24         return 1;
25 }
26
27
28 u32 SetupDqsPattern_PassA(u8 Pass)
29 {
30         u32 ret;
31         if(Pass == FirstPass)
32                 ret = (u32) TestPattern1_D;
33         else
34                 ret = (u32) TestPattern2_D;
35
36         return ret;
37 }
38
39
40 u32 SetupDqsPattern_PassB(u8 Pass)
41 {
42         u32 ret;
43         if(Pass == FirstPass)
44                 ret = (u32) TestPattern0_D;
45         else
46                 ret = (u32) TestPattern2_D;
47
48         return ret;
49 }
50
51
52 u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
53                                         u8 Channel, u8 Receiver,
54                                         u8 Pass)
55 {
56         u8 RcvrEnDly;
57
58         if (Pass == FirstPass)
59                 RcvrEnDly = 0;
60         else {
61                 u8 max = 0;
62                 u8 val;
63                 u8 i;
64                 u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
65                 u8 bn;
66                 bn = 8;
67 //              print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel);
68 //              print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver);
69                 for ( i=0;i<bn; i++) {
70                         val  = p[i];
71 //                      print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i);
72 //                      print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val);
73                         if(val > max) {
74                                 max = val;
75                         }
76                 }
77                 RcvrEnDly = max;
78 //              while(1) {; }
79 //              RcvrEnDly += secPassOffset; //FIXME Why
80         }
81
82         return RcvrEnDly;
83 }
84
85
86
87 u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
88                                 u8 RcvrEnDly, u8 RcvrEnDlyLimit,
89                                 u8 Channel, u8 Receiver, u8 Pass)
90 {
91         u8 i;
92         u8 *p;
93         u8 *p_1;
94         u8 val;
95         u8 val_1;
96         u8 valid = 1;
97         u8 bn;
98
99         bn = 8;
100
101         p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
102
103         if (Pass == SecondPass) { /* second pass must average values */
104                 //FIXME: which byte?
105                 p_1 = pDCTstat->B_RCVRDLY_1;
106 //              p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1];
107                 for(i=0; i<bn; i++) {
108                         val = p[i];
109                         /* left edge */
110                         if (val != (RcvrEnDlyLimit - 1)) {
111                                 val -= Pass1MemClkDly;
112                                 val_1 = p_1[i];
113                                 val += val_1;
114                                 val >>= 1;
115                                 p[i] = val;
116                         } else {
117                                 valid = 0;
118                                 break;
119                         }
120                 }
121                 if (!valid) {
122                         pDCTstat->ErrStatus |= 1<<SB_NORCVREN;
123                 } else {
124                         pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
125                 }
126         } else {
127                 for(i=0; i < bn; i++) {
128                         val = p[i];
129                         /* Add 1/2 Memlock delay */
130                         //val += Pass1MemClkDly;
131                         val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES
132                         //val += 0x02;
133                         p[i] = val;
134                         pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
135                 }
136         }
137
138         return RcvrEnDly;
139 }