2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass)
28 u32 SetupDqsPattern_PassA(u8 Pass)
32 ret = (u32) TestPattern1_D;
34 ret = (u32) TestPattern2_D;
40 u32 SetupDqsPattern_PassB(u8 Pass)
44 ret = (u32) TestPattern0_D;
46 ret = (u32) TestPattern2_D;
52 u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
53 u8 Channel, u8 Receiver,
58 if (Pass == FirstPass)
64 u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
67 // print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel);
68 // print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver);
69 for ( i=0;i<bn; i++) {
71 // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i);
72 // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val);
79 // RcvrEnDly += secPassOffset; //FIXME Why
87 u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
88 u8 RcvrEnDly, u8 RcvrEnDlyLimit,
89 u8 Channel, u8 Receiver, u8 Pass)
101 p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
103 if (Pass == SecondPass) { /* second pass must average values */
105 p_1 = pDCTstat->B_RCVRDLY_1;
106 // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1];
107 for(i=0; i<bn; i++) {
110 if (val != (RcvrEnDlyLimit - 1)) {
111 val -= Pass1MemClkDly;
122 pDCTstat->ErrStatus |= 1<<SB_NORCVREN;
124 pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
127 for(i=0; i < bn; i++) {
129 /* Add 1/2 Memlock delay */
130 //val += Pass1MemClkDly;
131 val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES
134 pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));