src/northbridge/amd/amdmct/mct/mctgr.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 static const u8 Tab_GRCLKDis[] = {      8,0,8,8,0,0,8,0 };
  22
  23
  24 u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct,
  25                                 u32 DramTimingLo)
  26 {
  27         /* Greayhound format -> Griffin format */
  28         u32 NewDramTimingLo;
  29         u32 dev = pDCTstat->dev_dct;
  30         u32 reg;
  31         u32 reg_off = 0x100 * dct;
  32         u32 val;
  33         int i;
  34
  35         DramTimingLo = val;
  36         /* Dram Timing Low (owns Clock Enable bits) */
  37         NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off);
  38         if(mctGet_NVbits(NV_AllMemClks)==0) {
  39                 /*Special Jedec SPD diagnostic bit - "enable all clocks"*/
  40                 if(!(pDCTstat->Status & (1<<SB_DiagClks))) {
  41                         for(i=0; i<MAX_DIMMS_SUPPORTED; i++) {
  42                                 val = Tab_GRCLKDis[i];
  43                                 if(val<8) {
  44                                         if(!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) {
  45                                                 /* disable memclk */
  46                                                 NewDramTimingLo |= (1<<(i+1));
  47                                         }
  48                                 }
  49                         }
  50                 }
  51         }
  52         DramTimingLo &= ~(0xff<<24);
  53         DramTimingLo |= NewDramTimingLo & (0xff<<24);
  54         DramTimingLo &= (0x4d<<24); /* FIXME - enable all MemClks for now */
  55
  56         return DramTimingLo;
  57 }
  58
  59
  60 u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val)
  61 {
  62         /* Greayhound format -> Griffin format */
  63         /*FIXME - BurstLength32 must be 0 when F3x44[DramEccEn]=1. */
  64 /*
  65                         ; mov   cx,PA_NBMISC+44h        ;MCA NB Configuration
  66                         ; call Get_NB32n_D
  67                         ; bt eax,22                             ;EccEn
  68                         ; .if(CARRY?)
  69                                 ; btr eax,BurstLength32
  70                         ; .endif
  71 */
  72         return val;
  73 }
  74
  75
  76 void mct_AdjustMemHoist_GR(struct DCTStatStruc *pDCTstat, u32 base, u32 HoleSize)
  77 {
  78         u32 val;
  79         if(base >= pDCTstat->DCTHoleBase) {
  80                 u32 dev = pDCTstat->dev_dct;
  81                 base += HoleSize;
  82                 base >>= 27 - 8;
  83                 val = Get_NB32(dev, 0x110);
  84                 val &= ~(0xfff<<11);
  85                 val |= (base & 0xfff)<<11;
  86                 Set_NB32(dev, 0x110, val);
  87         }
  88 }