src/northbridge/amd/amdmct/mct/mctardk4.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
  22                                 u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
  23                                 u32 *CMDmode);
  24
  25
  26 void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
  27                          struct DCTStatStruc *pDCTstat, u32 dct)
  28
  29         print_tx("dct: ", dct);
  30         print_tx("Speed: ", pDCTstat->Speed);
  31
  32         Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
  33                                 pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
  34                                 &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
  35                                 &pDCTstat->_2Tmode);
  36
  37 //      print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
  38 //      print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
  39
  40         if(pDCTstat->MAdimms[dct] == 1)
  41                 pDCTstat->CH_ODC_CTL[dct] |= 0x20000000;        /* 75ohms */
  42         else
  43                 pDCTstat->CH_ODC_CTL[dct] |= 0x10000000;        /* 150ohms */
  44
  45
  46         /*
  47          * Overrides and/or workarounds
  48          */
  49         pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]);
  50
  51         print_tx("4 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
  52         print_tx("4 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
  53 }
  54
  55 /*=============================================================================
  56  * Vendor is responsible for correct settings.
  57  * M2/Unbuffered 4 Slot - AMD Design Guideline.
  58  *=============================================================================
  59  * #1, BYTE, Speed (DCTStatstruc.Speed)
  60  * #2, BYTE, number of Address bus loads on the Channel.
  61  *     These must be listed in ascending order.
  62  *     FFh (-1) has special meanying of 'any', and must be listed first for
  63  *     each speed grade.
  64  * #3, DWORD, Address Timing Control Register Value
  65  * #4, DWORD, Output Driver Compensation Control Register Value
  66  */
  67
  68 static const u8 Table_ATC_ODC_D_Bx[] = {
  69         1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
  70         2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
  71         2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
  72         2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
  73         2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
  74         2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
  75         3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
  76         3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
  77         3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
  78         3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
  79         3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
  80         4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
  81         5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
  82         0FFh
  83
  84 static const u8 Table_ATC_ODC_D_Ax[] = {
  85         1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
  86         2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
  87         2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
  88         2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
  89         2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
  90         2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
  91         3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
  92         3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
  93         3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
  94         3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
  95         3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
  96         4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
  97         5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
  98         0xFF
  99 };
 100
 101
 102 static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
 103                                 u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
 104                                 u32 *CMDmode);
 105 {
 106         u8 *p;
 107
 108         *AddrTmgCTL = 0;
 109         *ODC_CTL = 0;
 110         *CMDmode = 1;
 111
 112         // FIXME: add Ax support
 113         if(MAAdimms == 0) {
 114                 *ODC_CTL = 0x00111222;
 115                 if(Speed == 3)
 116                         *AddrTmgCTL = 0x00202220;
 117                 else if (Speed == 2)
 118                         *AddrTmgCTL = 0x002F2F00;
 119                 else if (Speed == 1)
 120                         *AddrTmgCTL = 0x002F2F00;
 121                 else if (Speed == 4)
 122                         *AddrTmgCTL = 0x00202520;
 123                 else if (Speed == 4)
 124                         *AddrTmgCTL = 0x002F2020;
 125                 else
 126                         *AddrTmgCTL = 0x002F2F2F;
 127         } else if(MAAdimms == 1) {
 128                 if(Speed == 4) {
 129                         *CMDmode = 2;
 130                         *AddrTmgCTL = 0x00202520;
 131                         *ODC_CTL = 0x00113222;
 132                 } else if(Speed == 4) {
 133                         *CMDmode = 2;
 134                         *AddrTmgCTL = 0x002F2020;
 135                         *ODC_CTL = 0x00113222;
 136                 } else {
 137                         *CMDmode = 1;
 138                         *ODC_CTL = 0x00111222;
 139                         if(Speed == 3) {
 140                                 *AddrTmgCTL = 0x00202220;
 141                         } else if(Speed == 2) {
 142                                 if (MAAload == 4)
 143                                         *AddrTmgCTL = 0x002B2F00;
 144                                 else if (MAAload == 16)
 145                                         *AddrTmgCTL = 0x002B2F00;
 146                                 else if (MAAload == 8)
 147                                         *AddrTmgCTL = 0x002F2F00;
 148                                 else
 149                                         *AddrTmgCTL = 0x002F2F00;
 150                         } else if(Speed == 1) {
 151                                 *AddrTmgCTL = 0x002F2F00;
 152                         } else if(Speed == 5) {
 153                                 *AddrTmgCTL = 0x002F2020;
 154                         } else {
 155                                 *AddrTmgCTL = 0x002F2F2F;
 156                         }
 157                 }
 158         } else {
 159                 *CMDmode = 2;
 160                 p = Table_ATC_ODC_D_Bx;
 161         do {
 162                 if(Speed == *p) {
 163                         if(MAAload <= *(p+1)) {
 164                                 *AddrTmgCTL = stream_to_int(p+2);
 165                                 *ODC_CTL = stream_to_int(p+6);
 166                                 break;
 167                         }
 168                 }
 169                 p+=10;
 170         } while (0xFF == *p);
 171
 172 }