2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/
21 #define AMD_SAFEMODE 0x80000000 /* Unknown future revision - SAFE MODE */
22 #define AMD_NPT_F0 0x00000001 /* F0 stepping */
23 #define AMD_NPT_F1 0x00000002 /* F1 stepping */
24 #define AMD_NPT_F2C 0x00000004
25 #define AMD_NPT_F2D 0x00000008
26 #define AMD_NPT_F2E 0x00000010 /* F2 stepping E */
27 #define AMD_NPT_F2G 0x00000020 /* F2 stepping G */
28 #define AMD_NPT_F2J 0x00000040
29 #define AMD_NPT_F2K 0x00000080
30 #define AMD_NPT_F3L 0x00000100 /* F3 Stepping */
31 #define AMD_NPT_G0A 0x00000200 /* G0 stepping */
32 #define AMD_NPT_G1B 0x00000400 /* G1 stepping */
33 #define AMD_DR_A0A 0x00010000 /* Barcelona A0 */
34 #define AMD_DR_A1B 0x00020000 /* Barcelona A1 */
35 #define AMD_DR_A2 0x00040000 /* Barcelona A2 */
36 #define AMD_DR_B0 0x00080000 /* Barcelona B0 */
37 #define AMD_DR_B1 0x00100000 /* Barcelona B1 */
38 #define AMD_DR_B2 0x00200000 /* Barcelona B2 */
39 #define AMD_DR_BA 0x00400000 /* Barcelona BA */
42 Groups - Create as many as you wish, from the above public values
44 #define AMD_NPT_F2 (AMD_NPT_F2C + AMD_NPT_F2D + AMD_NPT_F2E + AMD_NPT_F2G + AMD_NPT_F2J + AMD_NPT_F2K)
45 #define AMD_NPT_F3 (AMD_NPT_F3L)
46 #define AMD_NPT_Fx (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2 + AMD_NPT_F3)
47 #define AMD_NPT_Gx (AMD_NPT_G0A + AMD_NPT_G1B)
48 #define AMD_NPT_ALL (AMD_NPT_Fx + AMD_NPT_Gx)
49 #define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
50 #define AMD_FINEDELAY (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2)
51 #define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0)
54 #define CPUID_EXT_PM 0x80000007
59 #define HWCR 0xC0010015
62 #define FidVidStatus 0xC0010042
65 #define FS_Base 0xC0000100
68 #define BU_CFG 0xC0011023
69 #define BU_CFG2 0xC001102A